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Latencies For Different Execution Units: FP Add/Sub: 2 CC FP MUL: 10 CC FP DIV: 25 CC INT ALU op/LD/SD: 1 CC 1. Without Data Forwarding

This document discusses a multi-cycle pipelined MIPS processor with different execution unit latencies. It analyzes hazards in a pipeline without and with data forwarding. In the first example, RAW hazards stall the pipeline in different stages. In the second example with forwarding, some RAW hazards are avoided but a load use data hazard stalls the pipeline. The scoreboard shows register dependencies and execution unit statuses.

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42 views2 pages

Latencies For Different Execution Units: FP Add/Sub: 2 CC FP MUL: 10 CC FP DIV: 25 CC INT ALU op/LD/SD: 1 CC 1. Without Data Forwarding

This document discusses a multi-cycle pipelined MIPS processor with different execution unit latencies. It analyzes hazards in a pipeline without and with data forwarding. In the first example, RAW hazards stall the pipeline in different stages. In the second example with forwarding, some RAW hazards are avoided but a load use data hazard stalls the pipeline. The scoreboard shows register dependencies and execution unit statuses.

Uploaded by

Anum Mansoor
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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20-Sep-2013

CS/EE-520 Computer Architecture Multi-cycle FP MIPS pipeline (Considering pipelined execution units)

Tutorial # 2

Latencies for different execution units: FP ADD/SUB: 2 cc FP MUL: 10 cc 1. Without data forwarding

FP DIV: 25 cc

INT ALU op/LD/SD: 1 cc

INSTRUCTION LD F4, 0(R7)

IF 1 2 3-5 6 7-10 11 12-14

ID 2 3-5 6 7-10 11 12-14 15-17, 17-21

EXE 3 6-7 7-8 11-20 12 15 22-46

MEM 4 8 9 21 13 16 47

WB 5 9 10 22 14 17 48

Comments (Mention different hazards stalling the pipeline) RAW in ID (F4) RAW in ID (F5) RAW in ID (R4) RAW in ID (F6) then WAW in ID for (F8)

ADD.D F6, F4, F3 SUB.D F5, F2, F3 MUL.D F8, F5, F6 DADDU R4, R1, R2 L.D F6, 0(R4) DIV.D F8, F6, F2

2. With data forwarding


INSTRUCTION LD F4, 0(R7) ADD.D F6, F4, F3 SUB.D F5, F2, F3 MUL.D F8, F5, F6 DADDU R4, R1, R2 L.D F6, 0(R4) DIV.D F8, F6, F2 IF 1 2 3-4 5 6-7 8 9 ID 2 3-4 5 6-7 8 9 10-11, 12-18 EXE 3 5-6 6-7 8-17 9 10 19-43 MEM 4 7 8 18 10 11 44 WB 5 8 9 19 11 12 45 RAW in ID (F6, LUD) then WAW in ID (F8) RAW in ID (F5) Comments LUD (RAW) F4

Scoreboard Same latencies as previous example.

INSTRUCTION SUB.D F8, F6, F2 MUL.D F8, F2, F4 ADD.D F3, F8, F9 L.D F5, 0(R3) DIV.D F10, F8, F15 L.D F8, 0(R5)

IS 1 2-6 7 8 9 10-19

RO 2 7 8-19 9 10-19 20

EXE 3-4 8-17 20-21 10 20-44 21

WR 5 18 22 11 45 22

Comments WAW in IS (F8) RAW in RO (F8) RAW in RO (F8) WAW in IS (F8)

Scoreboard status table when MUL.D is about to enter WR stage.


Number 1 2 3 4 Name ADD MUL DIV INT Busy Yes Yes Yes Op ADD.D MUL.D DIV.D Functional Unit Status Fi (Dst) Fj (Src1) Fk (Src2) F3 F8 F9 F8 F2 F4 F10 F8 F15 Qj MUL (2) MUL (2) Qk Rj (Flg) No No No Rk (Flg) Yes No Yes

F0 FU

F1

F2

F3 ADD(1)

F4

F5

Register Result Status F6 F7 F8 F9 MUL(2)

F10 DIV(3)

F11

F12

F13

F14

F15

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