ECE645 Lecture3 Fast Adders
ECE645 Lecture3 Fast Adders
Required Reading
Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7.4, Conditional-Sum Adder Chapter 6.4, Carry Determination as Prefix Computation Chapter 6.5, Alternative Parallel Prefix Networks
Conditional-Sum Adders
Assuming k is a power of two, eventually have an extreme where there are log2k-levels using 1-bit adders
This is a conditional sum adder
xi+1 yi+1
xi yi
branch point
1-bit conditional sum block
concatenation
c=1 c=0 2 1 1
c=1 c=0 2
c=1 c=0 2 1
c=1 c=0 2
1+1
1 1 1 2 2 1 1 2 2
c=1 3
c=0 3 1
c=1 3
c=0 3
2+1
2 2
1 3 3
5 5 c=1 c=0
4+1
10
B g p g p
B g p g p
14
ci = g[0,i-1] + c0p[0,i-1]
xk-1 x0 x1 x2 xk-1
16
17
20
s7
s6
s5
s4
s3
s2
s1
s0
23
s7
s5
s3
s1
24
c critical path c
g[0,7] p[0,7] C c8
g[0,6] p[0,6] C c7 S s7 p7 c6
g[0,5] p[0,5] C S s6
g[0,4] p[0,4] C
g[0,3] p[0,3] C
g[0,2] p[0,2] C
g[0,1] p[0,1] C
g[0,0] p[0,0] C
c0 p0 S s0
25
p6 c5 S s5
p5 c 4 S s4
p4 c3 S s3
p3 c 2 S s2
p2 c 1 S s1
p1
Critical Path
GP
1 gate delay
2 gate delays
2 gate delays
1 gate delay
26
27
28
30
31