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Verilog - Multiplexer PDF

The document discusses using Verilog HDL to design digital circuits. It provides code to design an 8-bit adder, a 4-to-1 multiplexer, and a 2-to-4 decoder. It also includes truth tables and test bench timing diagrams to simulate and verify the designs. The purposes are to learn Verilog HDL design, design basic circuits like an adder using the language, and observe simulation outputs to verify the circuit designs work as intended.

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Rashed Islam
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529 views

Verilog - Multiplexer PDF

The document discusses using Verilog HDL to design digital circuits. It provides code to design an 8-bit adder, a 4-to-1 multiplexer, and a 2-to-4 decoder. It also includes truth tables and test bench timing diagrams to simulate and verify the designs. The purposes are to learn Verilog HDL design, design basic circuits like an adder using the language, and observe simulation outputs to verify the circuit designs work as intended.

Uploaded by

Rashed Islam
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Objectives:

The purposes of the lab activity described here are as follows: 1) 2) 3) To learn about digital system design using Verilog HDL. To design Adder, decoder, multiplexer using Verilog HDL. To observe the simulation output of the Verilog design module using test bench.

Theory:
Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. The hardware description language is used to describe a digital system such as a network switch, a flip flop or a memory. It implies that any hardware can be described at any level using HDL.

Verilog coding for Adder is


module add2309(a,b,cin,sum,cout); input [7:0]a,b; input cin; output [7:0]sum; output cout; assign {cout,sum} = a+b+cin; endmodule

Figure 1: Adder circuit

Verilog as well as test bench coding for 4:1 multiplexer is module Mux(a,b,c,s,s1,s2,d); input a,b,c,s,s1,s2; output d; reg d; always @(s1 or s2) if (s1==1'b0 && s2==1'b0)begin d=a; end else if (s1==1'b0 && s2==1'b1)begin d=b; end else if (s1==1'b1 && s2==1'b0)begin d=c; end else begin d=s; end endmodule

module tb_Mux(); reg a1,b1,c1,s5,s15,s25; wire d1; initial begin a1=2'b00;b1=2'b01;c1=2'b10;s5=2'b11; s15=1'b0;s25=1'b0; #10; s15=1'b0;s25=1'b1; #10; s15=1'b1;s25=1'b0; #10; s15=1'b1;s25=1'b1; #10; s15=1'b0;s25=1'b0; end Mux tt(.a(a1),.b(b1),.c(c1),.s(s5),.s1(s15),.s2(s25),.d(d1)); endmodule

Verilog as well as test bench coding for 2:4 Decoder is module decoder(a,b,w,x,y,z); input a,b; output w,x,y,z; reg w,x,y,z; always @(a or b) if (a==1'b0 && b==1'b0) begin w=1;x=0;y=0;z=0; end else if (a==1'b0 && b==1'b1) begin w=0;x=1;y=0;z=0; end else if (a==1'b1 && b==1'b0) begin w=0;x=0;y=1;z=0; end else begin w=0;x=0;y=0;z=1; end endmodule module tb_decer(); reg a1,b1; wire w1,x1,y1,z1; initial begin a1=1'b0;b1=1'b0; #10; a1=1'b0;b1=1'b1; #10; a1=1'b1;b1=1'b0; #10; a1=1'b1;b1=1'b1; end decoder tt(.a(a1),.b(b1),.w(w1),.x(x1),.y(y1),.z(z1)); endmodule

Truth table for 4:1 multiplexer


Selector S1 0 0 1 1 Selector S2 0 1 0 1 Output (D) a b c s

Truth table for 2:4 Decoders


Input a1 0 0 1 1 Input b1 0 1 0 1 Output (w) 1 0 0 0 Output(x) 0 1 0 0 Output (y) 0 0 1 0 Output(z) 0 0 0 1

Test bench timing diagram for 4:1 multiplexer is

Figure 2: Timing Diagram for 4:1 multiplexer

Test bench timing diagram for 2:4 decoders is

Figure 3: Timing diagram for decoder

Discussion:
Finally in this lab, we had been introduced with Verilog Hardware Description Language. We gathered knowledge about designing adder, multiplexer, decoder circuit using Verilog HDL. We also verified truth table of these circuits using test bench timing diagram.

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