i : i 1993 Linear Applications Handbook Volume II A Guide to Linear Circuit Design es = __al ct Ke Ee aa inci aaeta? OS =Linear Technology Corporation 1993 Linear Applications Handbook Volume Il A Guide to Linear Circuit Design LUFE SUPPORT POLICY LUNEAR'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE [EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF LINEAR TECHNOLOGY CORPORATION, As use erin 42. Life support devices or systems are device or systems which (1) ae intended for surgical implant int the body, or (2 support or sustain ‘ie and whose fale to perform when propery used in accordance with instructions for use provided Inthe labeling canbe reasonably expected to result oa significant inuyto the user. i. Acricl components any component ia ie suppor device or sytem whose flue to perform canbe reasonably expected o cause the {aire of he te support device or systm ort atect ts safety oretectveess Information furnished hetla by Linear Technology Corporation i belived tobe accurate and real. However, no esponsbity fs assumed for its us. Linear Technology Corporation make oo rapresetation thatthe ilrconnecon of seus, as daseobed heel, will nat innge on ating patent rights Linea Technology Corporation +1630 McCarthy Bhd Mints, CA.95035 (408) 4921900 © Linear Technology Corporation 1969 Printed in USA AT WEA 1—_—_ INTRODUCTION Quality, Efficiency and Style The title above describes characteristics we seek in our application publications. This third” edition ofthe Linear Applications Handbook includes our latest attempts at instilling these traits into LTC literature. The 1990 edition’s introduction de- scribed the justification and approach for LTC’s application effort in significant detail. {tis recommended as a guide to using all LTC application notes, regardless of publication date. As such, its included in this edition. The trio of descriptives forming this section’s title heavily abbreviates what has been said, while adding additional perspective. Quality, in particular good quality, is obviously desirable in any publication. A high quality application note requires attentive circuit design, thorough laboratory technique, and completeness in its description. Text and figures should be thoughtfully organized and presented, visually pleasing, and easy to read. The artwork and printing should maintain this care in the form of clean text appearance and easily readable graphics. Application notes should also be efficient. An efficiently written note permits the reader to access desired information quickly, and in readily understandable form, There should be enough depth to satisfy intellectual rigor, but the reader should not ‘need an academic bathyscaphe togetto the bottom of things. Aboveall, the purpose is to communicate useful information clearly and quickly. Finally, style should always show. Too much technical literature is dull reading. We enjoy our work, and we want to share our enthusiasm. Quite simply, we want our Publications to be fun to read. An LTC author's ultimate fantasy features the reader athome inthe living room: relaxed, smiling, and reading (while writing down LTC Part numbers to buy). Style provides psychological lubrication, helping the mind torun smoothly. Clearly, style must only assist the serious purposes of publication ‘and should not be abused; we do our best to maintain the appropriate balance. ‘As noted in previous editions a number of people besides authors make this work Possible. As always, the final acknowledgement must go to our customers, who define our work, products, and company. We hope they are pleased with our latest efforts. James M. Williams April, 1993 Milpitas, California * Previous eton apearedn 1987 and 1990. Ths elon incudes only materia generated snc the 1990 ‘dito, AS suc, dont throw hat 1800 book vay! 2 LT1990 INTRODUCTION Why Write Applications? This. seemingly an odd and unlikely way to begin an applications publication, but itis valid question. As such, the components of the decision to produce this book are worth reviewing. Producing linear application material requires an intensive, extended effort. De- velopment costs for worthwhile materia are extraordinarily high, absorbing sub- stantial amounts of engineering time and money. Further, these same resources Could be directed towards product development, the contribution of which is much more easily measured at the corporate coffers. These are serious issues in any environment, but are particularly critical in a rapidly growing company, where resources must be thoughtfully allocated Linear Technology Corporation's commitment to a concerted applications eftort ‘was made despite these concerns. Specifically, the nature of linear circuit design is so diverse, the devices so sophisticated, and user requirements so demanding that designers require (oratleast welcome) assistance. Ultimately, the procurementand, Use of linear ICs is tie to the user's ability to solve the problems confronting them, ‘Anything which enhances this ability, in both specific and general cases, obviously benefits user and vendor. This isa very simple but powerful argument, and is the basis of LTC’s commitment to applications. Additional benefits include occasional new product concepts and ‘away to test products under “real world” conditions, but the basic justification is as described. Traditionally, application work has involved reviewing considerations for success- fuluse ofa specific product. Additionally, basic circuit suggestions or concepts are sometimes offered, Although this approach is useful and necessary, some expan sion is possible. LTC’s applications are centered on detailed, systems-oriented circuits, (hopefully) similar to the types of designs users are working with. There is a broad tutorial content, reflected in the form of frequent text digressions and liberal use of graphics. Discussions of tradeoffs, options and techniques are ‘emphasized, as opposed to brief descriptions of circuit operation. Many of the application notes contain appended sections which examine related or pertinent topicsin detail. ideally, this treatment provides enough background toallow readers ‘to modity the circuits presented into solutions to their specific problems. Some comment about the circuit examples is appropriate. They range from relatively simple to quite complex and sophisticated. Emphasis is on high perfor mance, in keeping with the capabilities of LTC's products and the market we serve. The circuit's primary function isto serve as a catalyst—once the reader has started thinking, the material has accomplished its mission.— Substantial effort has been expended in working out and documenting these circuits, but they are not finessed to the highest possible degree. All ofthe circuits have been breadboarded and bench-tested at the prototype level. Specifications and performance levels quoted in the text represent measured and extrapolated data derived from the breadboard prototype. The volume of material generated prohibits formal worst-case review or tolerances analysis or production, Addtion- ally, despite our best efforts, errors of various sorts do occasionally creep in along the way to publication. Because of these considerations, readers should contact, LTC when preparing to use a circuit ina production situation. This allows us to advise on specific areas of the circuit which may require a “second look” before ‘going to production. Updates, suggested modifications and just plain mistakes can also be discussed at this time, We have received numerous comments and questions since this book's frst (1987) edition. The most frequent query concerns topic selection. The topics presented are survivors of a selection process involving a number of disparate Considerations. These include reader needs, suitability for magazine publication, LTC’s short and long term commercial aspirations, time constraints and author interest in doing the work. Additionally, we seek a 10 year useful lifetime for application notes. This generally precludes narrowly focused effort towards individual ICs. Topics are broad, witha tutorial and design emphiasis that (ideally) reflects the reader's long term interests. While the circuits presented unabashedly favor our products, they must be conceptually applicable to succeeding genera tions of devices (hopefully ours). Similarly, the circuits should represent a relatively complete and interdiscipinary approach to solving the problem at hand. Solving a problem is usvally the reader's/customer’s overwhelming motivation. ‘The selection and integration of tools and methods towards this endis the priority. For this reason the examples and accompanying text are as complete and practical as possible This may nevessitateeffortin areas where we have no direct economic stake, e.g, the software presented in AN28 or the magnetics developed for AN25, AN29, and AN35.Insomecircumstances this policy necessitates use of competitor's. products (horrors!) where appropriate, Such gallant objectivity is not without calculation; the goal is to have readers associate LTC with realistic advice, useful products and satisfactory results, regardless of the problem encountered. The ong term task is establishing and maintaining credibilty and customer loyalty. If tunabused, these are powerful sales tools. Maintaining this stance involves a significant amount of negotiation and compromise with issues and individuals, but the results are usually favorable for everyone. ‘Asecond common question addresses the time required to produce an individual application note. The work invested varies considerably. AN29 required a year to complete. It involved endless laboratory hours, close coordination with our magnetics supplier and over 300 changes, corrections, band-aids and tweaks before the manuscript was finally released. Conversely, AN31 and AN32 were finished (perhaps therapeutically) within three weeks, Inallcases the actual writing time is a miniscule percentage of the total work time. AN2Q's year of effort was ‘writen up in a week. AN31 and AN32 required less than five hours, 4 7 oA LINEARLT WEAR ‘Another common question involves our photographie documentation. We have received hundreds of inquiries requesting details on instrumentation, particularly for mutttrace oscilloscope photography. Almost all photographic work is done with four (Tektronix 547 with afour trace 14 plug-in) or eight (Tektronix 556 with two 1A4 plug-ins) trace oscilloscopes. Photographs with more than eight traces, utilize multiple exposure or spicing techniques. Tektronix C-12 and C-27 cameras are used on both instruments, with modified graticule illumination on the 556 AN29's Appendix F provides additional discussion. AA final recurring question concerns use of this book as text in university level courses. We certainly welcome this, and find it rewarding. However, we cannot develop, or collaborate in the development of, supplementary material for problem sets and laboratory manuals. This simply strays too far from our charter. Some significant additions since the 1987 edition are the “Design Notes” and the open format used in AN26, AN27 and ANSE. “Design Notes” provide away to cover, a specific topic in concise form and get the material to the reader quickly. Most of these notes are stand-alone efforts. In some cases they are excerpted from application note work in progress and fed directly to print. When the application note becomes available, the material appears in unabbreviated form. Another change is the format used for AN26, AN27 and ANB. The segmented approach allows convenient updating and additions at some sacrifice in text flow. Subjects amenable to this treatment avoid the disruptive surgery required to revise a ‘conventional manuscript Inresponse to reader requests we have included macromodels of components. The present listincludes 28 ICs, all amplifiers. This inventary will grawand dversityinto, other part types. Significant effort has gone towards making these models realistic, ‘and usable, They areintended as powerful adjunct toolsin the design process, and should not be abused. More specifically, they are meant to augment actual breadboards, not eliminate them. Bypassing breadboarding is an extraordinarily hazardous process with @ high fatality rate, even among veteran designers. Although these macromode's cannot eliminate the cold realities involved in making ‘something work, they ease the task and save time. AS such, we encourage readers to use them and invite your comments, ‘Also new is the inclusion of application nates from other sources. These notes, found in the “Reference Reading” section, have proven particularly useful to readers. Theinformation they contains pertinent to problem areas that concernour readers. As such, they meritinclusion.Ifthis approach is well received ths section will be enlarged in succeeding editions. The cooperation of the contributors is appreciated. Finally, the appearance of new authors is applauded, particularly by the under- signed. There is plenty of work to do and many pens (and probes) ease the task while broadening perspective——— Acknowledgements ‘A number of people with a wide variety of talents contributed to this book. LTC’s senior management, most notably R. Swanson, B. Dobkin, and B. Ehrsam, provided continuous support and encouragement. M.J. Yuhas showed special skill inconverting the worst form of “chicken tracks” into legible, expertly prepared and edited manuscripts and is due special recognition B. Essaff prepared some beautiful breadboards (until! corrupted his construction technique) and was a major contributor to the lab work. C. Nelson, T. Redfern, 6. Erdi, W. Rempfer, D. O'Neill, N. Sevastopoulos, and B. Huffman contributed useful comments, most of which were not diluted by tact. Inthe final analysis, however, the ultimate acknowledgement must be reserved for ‘our customers, who are both the beneficiaries and benefactors of this book. Their requests and requirements define our work, and hence this book. If we have listened carefully, they should be pleased. (200m. James M. Wiliams November, 1989 Milpitas, California AT WERTABLE OF CONTENTS lnrRopucrion TABLE OF CONTENTS +1990 EDITION APPLICATION NOTE ABSTRACTS. SUBJECT INDEX. ‘SECTION 1—APPLICATION NOTES ANI aN aN and ANS ANG ANT ANB Na aNto ant ant ants ania ants ANB ant? ante ang anz0 Anat ane N23 N24 ANS NBA AN268 N66 AN260 AN28E AN26F AN266 ANH Understanding and Applying the L11005 Multi-Function Regulator Performance Enhancement Techniques for Three-Terminal Regulators Aplications fora Switched Capacitor Instrumentation Building Block. ‘Aplications fora New Power Buter Thermal Techniques in Measurement and Control Circuitry. Aplications of New Precision Op Amps ‘Some Techniques for Direct Digtzation of Transducer Outputs Power Conditioning Techniques for Batteries ‘Applicaton Considerations and Circuits for a New Chopper Stabilized Op Amp Methods for Measuting Op Amp Setting Time Designing Linear Circuits for 5 Operation Circuit Techniques for Clock Sources High Speed Comparator Techniques Designs for High Performance Vottage to Frequency Converters, Circuitry for Single Cll Operation Unique I Butter Enhances Op Amp Oesigns, Tames Fast Amplifiers Considerations for Successive Approximation A-D Converters Power Gain Stages for Monolithic Amplifiers 11070 Design Manual ‘Application Considerations fr an instrumentation Lowpass iter Composite Ampitors ‘AMonoihic IG for YoOMHz RMS-C Conversion Micropower Circuits or Signal Conditioning Unique Applications fo the LTC4062 Lowpass iter Switching Regulators for Poets Interfacing the LTC1090 tothe 6051 MCU Interfacing the LTC1090 tothe MC6BHCOS MCU. Interfacing the LT1090 to the HDB9705V0 MCU. Interfacing the L71090 to the COP82OC MCU Interfacing the LTC1090 to the TMS7742 MCU Interfacing the LTC1090 to the GOP402N MCU. Interfacing the LTC1091 tothe 8051 MCU Iertacng the LTC109% to the 68HC08 MCU ‘90H8 ‘90H8 "30K "90K 90H 90H "30H "90H ‘30KB ‘30HB 90H 90H8 0H 80H 90H 0H "30H, ‘90H ‘90H8 “90H8 ‘0H ‘90H ‘9048 oH 0H ‘soH8 ‘9048 ‘90H ‘90H ‘90H ‘90H ‘20H ‘90H6 "ot: ulate n BOLD rein is Aopeatns Handbook ates appear inLTCs 1990 Liner Apleatan Hantook (oon Cs 1990 Linear Aplin Handbo. 12 15 ant ane ANB AN ANS ANG ANT ANB AN ANT ANITA ANID ANI ANIA ANS ANE ANT ANB ANIO-t AN20-1 ANI N21 -AN8-1 AND ne5-4 ANQ6A AN26B+1 Nac AN26D-1 ANGE ANQGF-1 AN6G+4 ANBH-T LT WERTABLE OF CONTENTS nasi N26 AN26K AN26L Net ANZBN AN260 AN26P N60 AN26R ANZTA ane ve) AN0 Anat AN ANS ANA ANS ANA ANS6B NSEC ANE ANGE ANSEF N60. ANT ANB No NO ane an ans as ANS ANG ANAT ANB ang Interfacing the LTC1091 tothe COP820C MCU Interfacing the LTC1091 tothe TMS7742 MCU 5 Interfacing the LTG1091 to the COPS02N MCU Interfacing the LTC1091 to the HD63705V0 MCU. Interfacing the T1090 to the TMs320c25 DSP Interfacing the LTC1091/1.TC1092 tothe TMs320025 DSP. Imrfacng the LTC¥090 to the 2-80 MPU. Interfacing the LTC1090 to the HO6410 Interfacing the LTC1O91 to the HOB4t8O. Interfacing the LTC1094 toa Parallel Bus 'ASimple Method of Designing Mutple Order Al Pole Bandpass Filters by Cascading 2nd Order Sections ‘Thermocouple Measurement ‘Some Thoughts on DC-DC Converters Switching Regulator Circuit Collection Liner Circuits for Digital Systems High Etficeney Linear Regulators Converting Light to Digits; LTC1099 Halt Fash 8-8it AD Converter Digitzes Photodiode Array LTC1099 Erables Po Based Data Acquisition Board to Operate 0C-20KHz ‘Step-Down Switching Reguators Interfacing the LTC1290 tothe 8051 MCU. Interfacing the L7C1290 to the MSBHCOS MCU. Interfacing the LTC1290/LTC1090 tothe TMS370 MCU Interfacing the LTC1290 to the COP206 MCU. Interfacing the LTC1290 to the TMS7742 MCU Interfacing the LTC1290 to the COPAO2N MCU Interfacing the LTC1290 tothe 7-80 MPU Fast Charge Circuits for NiCad Batteries FiteCAD User's Manual, Version 1.00 Parasitic Capacitance Eft in Step-Up Transformer Design Take the Mystery Out ofthe Switched Capacitor Filter: The System Designer's Filter Compendium ‘Questions and Answers on the SPICE Macromodel Library Voltage Reference Circuit Collection Bridge Circuits: Marying Gain and Balance 171074/.11076 Design Manual . = ‘Measurement and Control Circuit Collection: Diapers and Designs onthe Night Shit. ficiency and Power Characteristis of Switching Regulator Circus... High Speed Amplifier Techniques: A Designer's Companion for Wideband Circuit... Using the LTC Op Amp Macromodels: Getting the Most from SPICE andthe LTC Lirary. uminatin Circuitry fr Liquid Crystal Displays: Tripping the Light Fanta ‘Not: publatons in BOLD aren options Handbook, ters appear inLTC's 1980 Liner Aoplations Handbook (O0HB - [TC's 800 Lea Appeaons Handbook) ‘90H8 ‘90H8 90H °30H8 AN26i-4 N61 AN26K-1 AN26L-4 '9OHB ANZEM- ‘90HB ‘90H8 ‘90H8 "90H ‘90H 90H8 "90H8 ‘90H ‘90HB ‘90HB "30H ‘90H8 90H ‘0HB ‘90H. ‘90HB ‘90HB ‘90H8 ‘30H8 "90H ‘0H ‘0H8 ‘90HB ‘90HB "30H8 AN26N-1 260-1 AN26P-+1 An260-1 AN2gR-1 ANITA AN2B-1 AN23-1 ANSO-1 ANSt-1 N21 ANG Natt N51 ANA ANS68-1 ANS60-1 AND ANSBE-1 ANSEF AN360-1 ANsT-+ ANSE ANSe-1 ANAo-1 ANA AANA2-A ANAS ANA ANSE ANAG-1 ANAT aNaB-1 NAGA 8 LT WEARTABLE OF CONTENTS AND ANS ANS2 -ANS3 ANS Interfacing to Microprocessor Based SV Systems . Power Conditioning or Notebook and Palmtop Systems Linear Technology Magazine Circuit Collection, Volume + ‘Micropower High Side MOSFET Drivers Power Conversion om Milam to Ang at Utra-High Eien (Upto 85%). ‘SECTION 2—DESIGN NOTES Nt Ne Na. Na NS Ne Nz Na Ng N10 Dnt ont2 N13 Nig DNS N16 DNI7 Nts Nig N20 naw N22 N23 N28 N25 N26 oNz7 N28 N29 Noo Nat ote Al pubis BOLD arin ths Agpsions Handbook ates appearia LT 1980 Lina Apleton Hnatook "New Data Acquistion Systems Communicate with Microprocessors Over 4 Wire ‘Sampling of Signals for Dig Fitering and Gated Measurements (Operational Amplifier Selection Guide for Optimum Noise Performance New Developments in RS232 Interfaces Temperature Measurement Using the LTC109091/92 Series of Data Acquistion Systems Operational Amplier Selection Guide for Optimum Noise Performance 10C Accurate Fiter Eases PLL Design Inductor Selection for T1070 Switching Regulators. (Chopper Ampitiers Complement a DC Accurate Lowpas Fiter Electrical Isolating Data Acquistion Systems Achieving Microamp Quiescent Currentin Switching Regulators ‘An T1019 and LT1014 Op Amp SPICE Macromodel {Closed Loop Control withthe LTC1290 Series of Data Acquistion Systems Extending the Applications of SV Powered RS232 Transceivers Noise Calculations in Op Amp Circuits Switced Capacitor Lowpass Files for Antaiasing Applications Programming Pulse Generators for Flash Memories | Battery Powered Laptop Computer Power Supply /ATwo-Wire Isolated and Powered 10-Bt Data Acquistion System Hex Level Shift Shrinks Board Space Floating Input Extends Regulator Capabilities "New 12-Bit Data Acquisition Systems Communicate with Microprocessors Over 4 Wires, 'Micropower, Single Suply Application: 1) A Sal-Siased,Butred Reference, (2) Megaohm input impedance Dierence Ampifer Complex Data Acquistion System Uses Few Components A Singla Ample, Precision High Voltage Instrument Amp. Auto Zeroing AD Oise Votane Design Consferations for RS232Intertaces A SPICE Op Amp Macromode forthe LT1012 A Single Suply RS232 Interface fr Bipolar Ato O Converters 5252 Transceiver wth Automatic Power Shutdown Control Isolate Power Suppl for Local Area Networks. (G0H@ LTE 1980 Lee ophstons Hardon) ‘90K ‘90H '90KB ‘90H8 "90H8 ‘SOHB ‘90H "90H "90H ‘90K ‘90HB "90H ‘90H ‘90HB 90H ‘90KB ‘90K 30H ‘90K ‘90H "30H, ‘90HB "30H ‘SOHB ‘9048 ‘90H8 “HB ‘90HB ‘90HB "0H ‘SOHB NSO ANS ANS2-1 ANSI co ANSAA ont on DN ons DNs N64 Dwr nas No Duta butt pure-t Duia-t buat DNts-1 Dwi6-1 putt niet Duig-t wao-1 watt wee-t Naat wet wes-1 n26-1 wart wae-t Naat DNso-1 DN3t-1 LT EATABLE OF CONTENTS nse N33 N36 DNS N36 NST N38 N39 pwao wat naz Ns Nas NAS NAS NST nas nag nso DNst ONS2 NSS DNS& ss: Ns: Ns? nse ONS® ‘N60 N61 ‘Nez N63 Ns DNS ‘ONES N67 Ns, N68 ‘A Simple Uta Low Dropout Regulator '9OHB ON32- Powering 3.3V Digital Systems. ‘Active Termination fr SCSI-2 Bus... 12-5 8-Chamel Data Acquistion System neces a BM PC Sei Po. Uttra Low Noise Op Amp Combines Chopper and Bipolar Op Amps High Dynamic Range Bandpass Filters for Communications ‘Applications for a New Micropower, Low Charge Injection Analog Switch Low Power CMOS RS485 Transceiver... Designing with a New Family of instrumentation Ampliirs ‘Switching Regulator Allows Alkalines to Replace NiCads . ‘Chopper vs Bipolar Op Amps—An Unbiased Comparison {LT1056 improved JFET Op Amp Macromodel Slews Asymmetrical. ‘ASimple Utra Low Dropout Regulator. Signal Conditioning for Patinum Temperature Current Feedback Ampliier “Dos and Don's’ Sitehing Repuator Generates Both Positive and Napatv Suppy with aS 'No Design Switehing Regulator SV, 6A Buck (Step-Down) Regulator ‘No Design Switehing Regulator SV Buck-Boost (Positive to Negative) Regulate High Frequency Amplifier Evaluation Board Gain Trimming in Instrumentation Amplitir Based Syst -DC Converters for Portable Computers igh Promance Frequency Cmpenstion Gives DE-DC Comer 75. Response wi High Sti ‘A4-Cell NiCad Regulator/Charger for Notebook Computers ew Law Cex Oiterentl na Video Ample Simpy Deis an improve Prtormanc. '3V Operation of Linear Technology Op Amps. Video Cireuits Collection .. {Simple uface Mout lsh Memory VP Generate. 5V High Current Step-Down Switchers... The LTC109 and LAOS; Mlrpower, S08, 1 ADCs Sample at hz on 3A Suppy Curent. Peak Detectors Gain in Speed and Performance ‘No Design Oitine Power Supply 2 AACalis Replace SV Battery, Extend Operating Life S232 Transceivers for Hand Held Computers withstand 10kV ESD Send Color Video 1000 Feet Over Low Cost Twiste ew 5V and 1, 128i ADCs Sample at 0k on 75m and 1A0KHE on 12m ‘AMV Offset, Clock-Tunable, Monolithic S-Pole Lowpass Filter ‘New Synchronous Step-Down Switching Regulators Achieve 95% Eficiency Low Parts Count DC/OC Converter Circuit with 3.3V and SV Output. v-DNSE-1 DNs7-1 NS-1 \mS8-1 ote: Al pula i BOLO ave he Agpaton Handok otters spear in LTC 1980 ner Applicaton Hanook (HOHE. CTs 1900 Lear options Mando) 10 AT NERTABLE OF CONTENTS SECTION 3—REFERENCE READING ‘Avoiding Passsive-Component Pitfalls ‘Avalog Signal-Handling for High Speed and Accuracy Prevent Emitter-Follower Oscillation . SECTION 3 of 1990 Linear Applications Handbook—MACROMODELS: unona cous uta? wwe unio owe 8 uioba wwe 4 uma oes uso 8 Lwsosa oe riot oe 8 i007 os 8 cries owe 10 cro owt Criotsuriow ms trios on 13 Crier me 4 criss ome 18 crise owe 18 csr ome 17 crore ome 18 Ure ows ia Crit ons 20 units et una ar) uritea ons ora ‘ona 24 oar ‘ona 25 ora? cH 28 ora coe 27 ops wow 28 ‘SECTION 4 of 1990 Linear Applications Handbook—REFERENCE READING Uertaning nretaence Type Nase cove RRA shieting an Guar, ‘one RRA outing Considers fr Pove Semicond wove RGA aero LT UAB "11990 ABSTRACTS 1990 EDITION APPLICATION NOTE ABSTRACTS AN AN AN ANG ANG ANT Understandiog and Appying the LT1005 Muttunction Regulator ‘Ths application note describes the unaue operating character- ‘tics ofthe LT1008 and descives a numberof useful applca- tions which ake advantage oftheregultrs abit to contra the output wit logic conta signa. Performance Enhancement Techniques for 3-Terminal Regiators Tis application note descrtes a number of enhancement circuit techniques used with existing Strmial roguators ‘which extendcurent capably, imtpower dissipation, provide high vttage output, operate from tTOVAC or 220VAC without the needto switch tansormer winginos, and many otheruseul application ideas. ‘oplications for a Switehed-Capactr Instrumentation Bulsing Block ‘This aplication note desribesa wide range ot wsetlapplea- tions forthe T1043 dual precision instrumentation switched capacitor buldgbiock, Some ofthe appkcationsdescrbedare ultrahigh performance instrumetationampiir ack inampl- fier, wide range digtaly controled variable gain ampli, relative humid sensor signal condtaner, LOT signa cond tioner, charge pump FV and VIF corwerters, 12-bit ND con- verter and mor. ‘Application ora New Power Butler ‘The LTIO%0 150m power bate Is described ina number of sell applications suen as boosted op amp, a feed-forward, ‘wide-band OC stabze ute, video ne diver ampli, ast ‘stmpl-toidwith ald step compensation, an overload proectod motor speed controle, anda plezoelecr fan sev. ‘Thermal Techniques in Measurement and Cont Crelry 6 applications utng thermally based circuits are detalles, Indes area SOMH2 RMS toOC converter andanemometer, liquid flowmeter and others. general dscusson of theemody- namic considerations involved in cireiy i aso presente, ‘Aoplcations of New Precision Op Amps ‘Appleton corsideratons and circus for the LT1001 and {T1002 singe and dual precision amples are usted in a umber of ccs, eluding stan gauge signal contioners, tnearaed platinum RTD circus, an uta pedision dead zone circu for motor srs ae eer examples. ‘Some Techniques for Direc Digitization of Transducer Outputs ‘Analog to-dital conversion circuits whic dec dite low level transducer outputs, without OC preampliication, ae pre- soned,Coveedarecicts wich operate wit thermocouples, strain gauges, humidity sensors, level transducers and other Power Conditioning Techniques for Batteries ‘varity of appreachastor paver condoning batteries given. Swtehing anwar regulates and converters ar shown, with attention to etcency and law power operation. 18 circuits are (resented with performance data, aN aNio anit ants ANS: ANG ‘aplication Considerations and Circuits for a New ‘A dscussion of cut, layout and constacton consiertions ‘orloniovelCeutsineudes erroranaiysisof solder wireand connector junctions, Applizatonsinclde sub-mierovt insur ‘mentation and isolation amplifies, staiized butlers and com Barats and precision data converters. ‘Methods fr Measuring Op Amp Setting Time TeANtObepins witha survey of methods for measuringop amp _sting tie. Tiscommentary developsinto cts formeasur ing setting timet0 000054, Construction detaisandesuitsare presented, Appended sections cover sclscope overload i {ations and amp requeney compensation Designing Linear Circuits for SV Operation Thisnate coversthe considerations or designing precision tinear ‘rats ich must operate from asingleSV supply. Applications inctde various transduce signal condones, instrumentation amplifiers, controllers and isolated dala converters. CieutTechques fr Clock Sources Ceuitsforlocksoureasaepresertes Spciaatentionis given to eysta-based designs including TXCOs and VCS. High Speed Comparator Techniques ‘The AN isan extensive discussion ofthe causes and cures of problems in very high spées comparator cicuts. A separate _ppcatios section presenti, incudinga0.026% aceu- fate TH2 to 3OMHe VF conver, 2 2000s 001% sample-hol and a 1OMiz fiberoptic raceer. ve appendices covering related tpies complete this not, Designs for High Frequency Volage-to-Frequency Converters val of high performance iF circus is presente, Incuded area 1H2 to 100MH2 design, a quar-stbiized type and a (0.007% linear unt Oter exc feature 15 operation, sine wave ouput an nonlinear transfer furetions. separate section amines he trada-ofs and aivartages various approachesto ViF conversion. Circa tor Single Cell Operation 115V powered cul for complex lear uncions are deta. Designs include a iF converter, 2 10-bt A, sampie-noa amplifiers, aswtehingreguatorandathecruts’ Alsincuded isasectonoteompanentconsiderations or SV powered feat cious. ‘Unique IC Butler Enhances Op Amp Oesins, Tames Fast Amglitiers ‘Ts note describes some of the nique 10 design techniues Incorporated into a fast, mono power bute, the LT1010. ‘Also, some appleaton ideas are described such as capactve load ‘evng, boosting fast op amp ouput curent and power ‘supply crits, 12 AT WEA1990 ABSTRACTS ANT ang ania ‘AN20 Anza N23 aNza Consideration fr Successive Approximation ND Converters -Atutoiaon SAR type A/D converter, this note contain ete information on several 12-itereuts. Comparator, cocking, and preamplifier designs are discussed. Anal eveut ges a 12-b8 comersion in 1.8. Appended secons expan the tasic SAR technique and explore DIA considerations. Power Gain tages fr Monolith Am ‘Thisnot present output state circus which provide power gain for monolithic amps. The cicuts feature voltage gan cur ‘ent gan or both. leven designs are shown. and performance 's summarize. A generalized method or requencycompensa- tion appears in a separate section. {71070 Design Manual This design manual i an extensive discussion of al standaré ‘witching configurations forthe T1070; including buck, boos, fyback, forward, inverting and “uk” The manual includes comprehensive formation onthe T1070, te external comp ‘en used wth it and complet formulas for calculating compo nent ales. ‘Aplications fora DC Accurate Lowpass Switehed-Capacior Filler Discusssthe principles ofoperatinoftheLTC1062andhelpul hints for ts application. Various application circults are ex plained in deta wt focus on how to cascade two LTCI082s and tow to obtain notches. Noise an distortion performance ae fly iustrate, ‘Composite Amplifiers ‘aplication often requie an amplfer that has extremely high performance in tera areas. For example highspeed and OC ‘rcision are often needed It a single device cannat smut ‘neously achiev the desired characterises, acomposte ampli fiermade up oftwo (ormore) devices canbe conigurestodo the Job. AN2t shows examples of compost approaches in designs ‘combining speed precision, low nose and high power ‘A Monolithic IC for 10OMHe RMS/DC Conversion ‘AN22 detals the theoretical and application aspects of the {T1088 thermal RMS/DC converte. Te Bese theory behind {thermal RMSYDG conversion i isoussed and design deals of the LT1086 ae presented. Cicuty for RMS/DC converters, wide-band input butters and heater protection i shown, ‘Miropower Circuits fr Signal Condtioning Low power operation of eetrnic apparatus has become in creasingly desirable. AN23 describes a vaney of ow power Ceuits for transucer signal condoning. Ao included are Asians for data converters and switching regulators, Three appended sections discuss guidelines fr miropower design, strobed power operation and effects of test equipment on rmicropower creuts, ‘Unique Applications forthe LTCYOE2 Lowpass Filter Fihlghs the LTC1062 as lowpass titer ina phase lack oop Describes how the loops Bandwidth can be increased and the "WOO outut ter reduced when the LTCYOE? I the fop fier ‘Compares wth a passive RC lop fie. Aso discussed i he use of LTC1062 as simple bandpass and bandstop titer, N25 N26 ‘Switching Regulators for Poets ‘Subtle “A Gentle Guid for tha Tepidatious," his sa oi on switching regulator desig, The tet assumes no switching regulator design experience, contains no equations, and requires no inductor constuction to bul the crc described Designs deta incu fyback, slated telecom, off, and cers. Appended sections cover camponent consisrtions, measurement techriques and steps involved in develoning a working circu. ‘colton of interface appliations betwoen various miropro- ‘cassrsicontols and the LTC1090 family of data acquisition systems. The nate Is ddd into sections spect to each interface. The folowing sections are avaiable: Microprocessor! Number vy Microconot NGA ——_LTC1080 8051 7268 LTCI080 eaH00s ange =——_LTC000 62705 anzso——LTC1080 corszo anes T1090 mis7742 anes LTO1000 copsacn wise Liciot e051 mes LTGH09t 68H005 ‘anes! LTO oPe20 a8) LTo1091 IwSI742 anesk = LTCA091 copaczn anes, = LTCI091 0637050 anoem = UTot090——_TS320025 AN26N —LTC091/@@ © TMS320025, aneso——LTC3090 Z80 anesP ——TC1080 064180 anzsa——UTCI081 Hos4180 anzgn —LTC1094 = TS320025 Tas intertace notes demonstiate the ease with whlch the LTC1060tamly canbe itericed to microprcessoricontrl les having ether paral or seral ports. A complete hardware and software deseition of the interfaces included. ANZTA ASimple Method ofDesigningMutplOrderAlPote Bandpass Firs by Cascading 2nd Order Sections Presents two methods of designing high quay switched ‘apactor bandpass fits, Both methoss are intended to vastly Simpify the mathemates involved In iter design by using {abular methods. Te ex assumed no fier design experience Dutalows high quay fiters io be implemented by techniques not presented before inthe iterature. The designs ae imple ented by numerous examples usng devices from LIC'S Suitched-Capactorfiter family: LYC1060, LTC1061, and LATC1064. Butterworth and Chebyshev bandpass fiers are dscussed ATE 13,1990 ABSTRACTS EEE N28 AN29 ‘AN32 N33 AN34 ‘Thermocouple Measurement Considerations for thermacoupe-based temperature measure tment are discussed, Atutoral on temperature sensors summa aes pectormanceotvaraus types, establshingperspectiveon thermocouples. Thermocouples are then focused on Included fue sections covering eoiuncton compensation, ampier Selection, ditererialsolaon teciques, protection, and lin ‘ariztion. Comglate schematics aregven oracuts. Praca: sot-basad Irearzation is also presented withthe necessary sotvare detalles ‘Some Thoughs on OC/DC Converters This note examines a wie range of DC/DC converter appioa- tion. Single laduetor, transformer, and switched-capactor ‘converter designs ae shown, Special topis Ikelow nose, high efficiency, ow quiescent curent, high voltae, and wide-input ‘oa rang converters are covered. Appended sections ex: plain some fundamental properties of diferent types of converters. Switching Reguator Circuit Collection Switching eguitors reat uiversalinterest. Linear Technology has made a major efor to address this topic. A catalog ot Creuits has baen compiled so thata design engineer can swity ‘eterine whlch converter ype i best. This catalog serves as visual Index to be browsed through for aspect or general interest, Linear Ciel for Digital Systems Subttea"Someftabl Analogs for Digta Does” discusses a number of analog circuits sell in predominant igtal Systems, Vop generators for Nash memories receive extensive treatment, Other examples include a curent oop transmit, dropout detectors, power management circus, and docs. High Eticency Linear Reguators Presents circu tecniques permitng high efficiency to be obtanad ith near regulation Particular attentions gientothe ‘problem of maintaining Pighefincy with widely veyng in pats, outputs ad loading, Append sections revw component charatrstes and measurement methods Converting Ligh to Digits: LTCTOBD all-Fash 6-88 AD Converter Digtzes Photodiode Aray ‘Thisapplleaion not describesa Liner Technology “Hat-lash” ‘ND converte, te LICTO8, being connected to a 256 elemant ‘inesean photodiode array. Thistechnology aap sel to han hl (ie low power barcode readers as we ashigh resolstion automated machine inspection appcations ‘o1099 Enables PC-Based Data Acquistion Board to ‘Operate DC-204Hr ‘Reamplet design fora data acquiston card forthe IM PC is ‘ote in ts appicatin nate, Adtionaly, language coe is proviged to alon sampling of dataat speed of mare than 20 ‘Tesped itton strictly basedonthe execution speed ofthe 1 dataacqustion op. A"Turbo"Tcanacquie tat speeds reatertnan 204K, Machines with 80286 and 80386 processors ‘an go faster tan 202. he computer tat was used as atest bud in this appiation was an XT runaing at 4.772 and thereto al system timing and aequlstian te measurements axe asad ona 4.77MHz clock sped N35 ans7 NSB N39 NAD ‘Step-Down Switching Regulators DiseussestheLTIO74,aneasiy apple step down regulator Basic conoepts and circuits are described along with more sophisticated applications, Siappended sections cover T1074 Cireuiry deta. inductor and ascete component selection, Curent measuting techniques, effleny considerations and othr tpi, ‘colton of interface applications between various micropro- cessorsicontrols and the LTC1290 family of data acquisition System, The note Ie died into sections speci to each Imertae, The fing sacions are avaiable: Microprocessor Number NO Mirocontotir ange LTCI290, 051 anaes Tct200 vmosaHc05 ‘age LTorzOLTOTO|0 ——TMS370 geo T0190, ccoPa2oc pugs L129 us7ra2 wage (TCI290, copay mgeo——LTC1290, 2.80 anger TC1200, 64180 These interface notes demansrate the ease with which the TG1290 canbe interfaced tomicrprocessorsicontraleshav- ing ether parallel or serial posts. A complete hardware and stare description of he inerace is included. Fast Charge Cleuis lr Wiad Bateries Sale, fast charging of NiCad batteries is attracve in many applications. This note deals simple, ermaly-tased fast hare ccuty for Niads, Pesormance data is summarized and compare to other charging methods. FillerCAD User's Manual, Version 1.00 This note the manual for FOAD, 2 computer-aided design program for designing fiers wih LTC's switehed-capactor fier fami. FCAD helps users design good titers with amin ‘mum amount of efor. The experienced tite designer can use ‘the program to atiee beter cesuls by providing te abit to ‘lay "what i” wth the valuee and configuration of various tampons. Parasitic Capactance Elects in Step-Up Transarmer Design ‘This note explores the causes ofthe large resonating curent spikes onthe leading ede ofthe snitch current waveform, ‘These anomalies ere exacerbatd in very high vollage designs ‘ake the mystery Oto the Swiened-Capacitor Filter: ‘The System Designer's Fitr Compendium ‘ThisnotepresentsgudeinesforccuisilingL T's switche Capito titers, The cieussion focuses on how to optimize fier perormance by apiniing the printed wring boars, te power supply, and the output buffering of the fier. Many fational topics aed scussed suchas nowt selec he proper fier response forthe application and how to characterize a {ters THD for OSP applications ———_—_ 14 AT WESUBJECT INDEX A GUIDE TO THE INDEX Linear Technology has made a major effort to address a wide variety of citcuit topics. The number of application problems solvable with innovative circuit techniques or New linear integrated circuits continues to grow at a impressive rate. This comprehensive index includes Ap- plication Notes (AN1-ANS5), Design Notes (DN1-DNG8) and Data Sheets circuits (through January 1993), NOTE: Api and Design Notes rin this Volume I Book. UIC LITERATURE SUBJECT INDEX A-D—See Converter-Data ACCELEROMETER—See Signal Conditioning ACOUSTIC THERMOMETER—Soe Signal Conditioning Temperature AMPLIFIER Absolute Value Precision Absolute Value Circuit: LT1001 DS; LT1002 DS Wide Bandwidth Absolute Value Circuit: LT1022 DS; 1112208 Precision Absolute Value Circuit: OPOS OS ‘Additional Feature Circuits DC and AC Zeroing: LF198 DS Inverting Ampltier with High Input Resistance: M108 OS Constant Gain Amplifier Over Temperature: LT1004 DS ‘Ammeter with Six Decade Range: 11008 DS; LT1012 DS Five Decade Kelvn-Varley Divider: LT1008 DS. Input Ampitier For 4-1/2 Digt Voltmeter: T1008 DS; 7101208 (0¢ Stabilized FET Probe: LTC1052 DS Artifical Ground Synthetic Ground: ANSO, Pg. 5 The category and subject index are organized so that application circuits and subject tutorials are easily found. The major categories are broken up into specialized topics to help isolate a particular application, The subject index works as follows, i. ANS, Pg. 8 = Application Note 8, page 8; LTC1044 DS = LTC1044 Data Sheet; ON17, Pg, 1 = Design Note 17, page 1. Notes 1 through 40 and Design Notes 1 through 32 are found in 1990 Applications Handbook. All ther Application Notes ‘Audio Very Low Distortion Butfered Pre-Amplifier: ANS2, Po. 15, LT1010 DS. Balanced Transformerless Microphone Preamp: T1115 DS High Performance Transformer Coupled Microphone Pre-Amp: LT1115 DS. Low Noise DG Accurate X 10 Buffered Line Amplifier: L71115 DS Moving Coil Passive RIAA Phonograph Pre-Amp: T1115 0S RIAA Moving Coll “Pre-Pre" Amplifier: LT1115 DS IAA Phonograph Preamplifier (40dB/604B Gain): U71115 0s Boosted Output Basic Boosted Op Amp (150mA): ANA, Pg. 1 Increasing Output Current (10mA-20mA): ANS, Pg, 18 Increasing Output Current and Voltage (=12V at 20mA): AN, Pg. 18 1.5 Votage Boost put Op Ao (0-0): AN, 0.6 LT1010, Paraleling: AN16, Pg, 17 Fast Power Buffer (10MH2): AN16, Pg. 20 High Current Booster (3A): AN18, Pg. 2 Output Stage (150mA): ANB, Pg. 2 Ultra Fast Feed Forward Current Booster (1000V/us, 4 4MHz, 200mA): AN18, Pg. 3 AT NEAR 15SUBJECT INDEX Low Output Saturation: AN'8, Pg. 4; ANEO, Pg. 2; ur¢1052Ds High Current Rail to Rall Output Stage (100mA): ANTS, Pg. 6 Output Stage (#120V Swing): AN18, Po. 7; LT1055 DS Output Stage (£150V Swing) AN'8, Pg. 8 Unipolar Output, Gain Stage (1000V Swing): ANT8, Pg. 9 +£15V Powered, Bipolar Output, Voltage Gain Stage, (#100V Suing): AN18, Pg, 11 Paralletng for High Curent: AN21, Pg. 12 Fast-200mA: ANAT, Pg, 46; LT1220 0S Fast, 1A Booster Stage: AN47, Pg, 47; LT1220 DS Precision Ampltier Drives 50002 Load to 10: T1002 Ds Pracsion Amplifier Drives 20082 Load to +40V: LT1007 DS; 0P227 DS High Output Current Op Amp: LT1022 DS; ANT6, Po. 15; LTC1052 DS. Instrumentation Amplifier with +150mA Output Curent LT4101 0S; LT1102 DS Increasing Output Current and Votage: LTC1052 DS Butter Fast, Stablized FET Buller (FET Probe): ANS, Pg. 9 Input Buffer forthe LT1088: AN22, Pg, 12 Large Signal Voltage Follower: LT1001 DS Fast £150mA Power Butter: T1010 DS Clamping Techniques Precision Adjustable Dead Zone Generator: ANG, Po 5; LT1001 DS; LT1002 0S Precision Clamp: LM129 0S Composite 1 Stabilized Fast Amplifier (23V/us, 300KHz FPR): ANT, Pg. Fast DC Stabilized FET Amplifier (100V/us, 1MHz FP) N21, Pg.2 DC Stabilized-Summing Point Correction: ANA7, Pg. 33. DC Stabiized-Input Stage Current Correction: ANA7, Pg. 34 DC Stabilized-Otfset Pin Correction: ANA, Pg. 34 DC Stabilzed-Full Differential, Parallel Path: ANA7, Pg. 35, ‘DC Stabilzed-Full Differential, Parallel Path, A= 1000: ‘ANAT, Po. 36 Fast Summing Amplifier; LM108 DS; LTC1052 DS; LH2108 DS Current Mode “Current Mode Feedback” Amplifier (MHz FPB): AN21, Pg. 7; AN22, Po, 12; LT1088 OS “Current Mode Feedback’ (Son of Godzla Amplifier) (2000Vius, 25MHz FPB): ANZ, Pp. 8; AN22, Pg. 18; 71088 DS DAC Butter Simple Pre-Amplifier forthe Comparator: ANY7, Pg. 4 “No Trims” 12-Bit Multpying DAC Output Amplifier: N47, Pg 32; LT1022 DS; LT1122 0S Fast Setting 12-Bit DAC Butfer: LT1220 DS No Vos Adjust CMOS DAC Butfer: LTCTO52 OS Dead Zone Dead Zone Generator: LT1001 DS; LT1002 0S Discussion LT1010 Buffer: ANA, Pg. 7; ANG, Pg. 1 Chopper Stabilized Op Amps: ANS, Pg. 19 ‘Amplifier Compensation: AN10, Pg. 8 LT1010, Performance Summary: AN16, Pg. 7 Frequency Compensation: AN18, Pg, 12 Perspectives on High Speed Design: ANA7, Pg. 7 Perspectives on Speod: AN47, Pg. 7 Typical High Speed Ampltier Problem: AN47, Pg. 7 High Speed Effects in Cable, Connectors and Termination: ANAT, Pg. 15 High Frequency Amplifier Evaluation Board: ANAT, Pg. 127 Operational Amplifier Selection Guide for Optimum Noise Performance: DN3, Pg. 1 Chopper vs Bipolar Op Amps: DN42, Pg. 1 Dero DG009 High Frequency Amplifier: DNSO, Pg. 1 Input Guarding: L108 DS Input Protection: LM108 OS ‘Advantages of Matched Dual Op Amps: LT1002 DS; 0P227 DS; LT1024 DS Gain of 1000 Amplifier with 0.01% DC Accuracy: T1007 DS Achieving Picoampere/Microvolt Performance: LT1008 DS; LT1012 DS; LTC1052 DS Frequency Compensation: LT1008 DS Isolating Capacitive Loads: LT1010 DS High Speed Operation: LT1055 DS Phase Reversal Protection: LT1055 DS 16 LT WERSUBJECT INDEX Isolating Large Capacitive Loads: LT118 DS Oiset Votage Adjustment: 0P27 OS Divider ‘Analog Divider: LT1057 DS Divide by 8: LTC1048 OS Divide by 4:LTC1048 DS Divided by 2: LTC1043 0S Precision Vottage Divide by 2: LTC203 DS Fast Precision igh Speed Op Amp (1000V/ps): ANB, Pg. 7 LTt001 Os Stabilized FET Butter (FET Probe): ANS, Pg. 9 Fast DC Stabilized FET Ampliir (100 Vis, 1M FPB): N21, Po. 2 “Current Mode Feedback” Amplifier (MHz FPB): AN21, Pg, 7: AN22, Pg. 12; LT1088 DS “Current Mode Feedback’ Ampitfir(2000V/us, 25MHz PB): ANI, Pg 8; AN22, Pg. 13: T1088 DS Fast Precision Inverter: LH2108 DS Fast Summing Amplifier: LM108 DS Fas Precision Inverters: LT1008 DS Instrumentation +£5V Precision Instrumentation Amplifier: AN3, Pg. 2: T1006 DS; LTC1051 DS Chopper Stabilized Instrumentation Amplifier: ANS, Pg. 3. LTc1043 Ds Instrumentation Amplifier with 300V Common Mode Range: ANG, Pg. 2; LT1001 DS Ultra Precision Instrumentation Amplifier: ANS, Pg. 6; ANTI, Pg.6 Precision instrumentation Amplifier: AN, Pg. 6 A Single Amplifier, Precision High Voltage Instrumenta tion Amp: DN2S, Pg. 1 Differential input Instrumentation Amplifier: LM108 OS ‘Three Op Amp Instrumentation Amplifier: LT1002 DS; 71024 DS; OP0S DS Two Op Amp Instrumentation Amplifier with CMAR Trim LT1002 DS; LT1024 DS; LTC1049 DS Instrumentation Amplifier with +100V Common Mode Range: LT1012 DS '5V Powered Precision instrumentation Amplifier: LT1013 DS. '5V Single Supply Dual Instrumentation Amplifier LT1013 0S. ‘Triple Op Amp Instrumentation Amplifier with Bias Current Cancellation: LT1013 DS Low Noise, Wide Bandwidth instrumentation Amplifier: L1028 0S High Performance Instrumentation Amplifier: LT1051 DS. {Instrumentation Amplifier with Shield Driver: [T1058 0S; 11124 0S Differential Output: LT1101 DS; T1102 0S Gain = 20, 110 oF 200 instrumentation Amplifier: 171401 DS; LT1102 DS Precision, Micropower, Single Supply Instrumentation Amplifier: LT1101 DS High Speed, Precision, JFET Input Instrumentation Amplifier: LT1102 DS 20MiHz, Ay = 50 Instrumentation Amplifier: LT1221 DS; 71225 0S '5V Powered Ultra Precision Instrumentation Ample: LTc1052 DS Precision, Chopper Stabilized, Single Supply Instrumenta- tion Amplifier: LTC1100 DS Single Supply, Chopper Stabilized Instrumentation Amplifier: LTC1150 DS Integrator Integrator with Programmable Reset Level: LF198 DS Low Drift integrator with Reset: LM108 DS Inverter Utta Precision Voltage tnverter: LTC1043 DS Isolation Precision Isolation Amplifier (250V Iso—0.03% Acc.): ‘ANS, Pg. 8; LTC1052 DS Lock In Lock in Amplifier: ANS, Po. 4; AN43, Pg. 24; LTC104308 Logarithmic Logarithmic Amplifier: LT1008 DS Six Decade Log Amplifier LTC1051 DS Low Noise OC Stabilized, Ultra Low Noise (Vos = Sy, 11nV/ Ha}: AN21, Pg, 10; LT1028 DS; LTC1150 Paralleling for Low Noise: AN21, Pg. 11; LT1028 DS; LTC1051 DS Chopped Bipolar Low Noise Amplifier: ANAS, Pg. 2 Low Noise, Chopper Stablized FET Pai: AN4S, Pg, 8 Uttra Low Noise, Low Drift Ampifier: LTC1052 DS LT WEAR 17SUBJECT INDEX Low Voltage '3V Operation of Linear Technology Op Amps: ONS6, Pg. 1 Low Vos Drift Vos Nuling Loop: LT1220 DS Obtaining Utra Low Vos Drit and Low Noise: LTC1051 DS Uta Low Noise, Low Drift Chopper Amplifier: LTC203 DS Micropower Meter Amplifier: LM10 DS Microphone: LM10 DS Transducer Amplter: LM10 DS Precision, Micropower, Single Supply Instrumentation ‘Amplifier: LT1 101 DS Micropower, Single Supply Op Amp: LT1178 DS ‘Multiplier Aalog Mutiplier with 0.01% Accuracy: ANS, Pg. 14 Muliplier-DC to SOM: ANAT, Pg. 45 Resistor Muttplie: LT1012 DS ‘Analog Muttiplie/Divider: LTC1040 DS Precision Multiply by 3: LTC1043, Mutily by 2: LTC1043 DS Precision Multiply by 4: LTG1043 0S Analog Mutiplier: LTC1099 DS Noise Noise Calculations in Op Amp Circuits: DN1S, Pg, 1 Noise Testing: 0P27 DS Oscillation Problems Frequency Compensation without Tears: ANA7, Pg. 86 Programmable Gain Programmable Gain Amplifier (Single Supply) Lr1078 Ds Reciitier—See Aiso Absolute Value Precision Rectifier: LM101 DS ‘0kHz Precision Rectifier: LT1011 DS Half Wave Rectifier: LT1077 DS AF RF Leveling Loop: ANZ2, Pp. 14; LT1088 DS RF Leveling Loop: AN47, Pg. 64; ANS2, Pg. 13 ‘Simple RF Leveling Loop: ANAT, Po. 64 Sample and Hold Fast Sample-Hold, 2us 0.01%, with Hold Step Compensa- tion: ANA, Pg. 5 ‘Sample and Hold (200ns-0.01%): AN3, Pg. 15, LT1016 DS ‘Sample and Hold (10ns): AN3, Pg. 18 4.5V Powered Sample and Hold: ANTS, Pg. 3 1.5V Fast Sample and Hold (125us, 0.4%): AN15, Pg. 4 Micropower Sample and Hold: AN23, Pg, 10; LT1006 DS B-Bit-100ns Sample and Hold: ANA7, Pg. 57 ‘Quad 12-Bit Sample and Hold: DN38, Pg. 2; LTC201A DS Basic Sample and Hold: LF198 DS Diferential Hold: LF198 OS Fast Acquisition, Low Droop Sample and Hold: LF198 DS (Output Holds at Average of Sample Input: LF198 DS ‘Sample and Difference Circuit: LF198 DS 1000 Sample and Hold: LF198 DS. Sample and Hold: LM108 DS Fast, Precision Sample and Hold: LT1022 DS 5s Sample and Hold with Zero Hold Step: LT119A DS ‘Sample and Hold, 8-Bit 100ns: LT1220 DS (Quad Single SV Supply, Low Hold Step, Sample and Hold LTc1043 Ds Low Power, Low Hold Step Sample and Hold: LTc1049 0s Infinite Hold Time Sample and Hold: LTC1099 DS. Settling Time Setting Time Test Circuit: AN10, Pg. 1 Improved Setting Time Test Circuit: AN1O, Pg. 2; 71055 DS Circuit for Testing Followers: AN1O, Pg. 3 Sampling Switch for Uttra Precision Settling Time Measurement: AN1O, Pg. 4 Measuring Amplifier Setting Time: ANA7, Pg. 82 Track and Hold Fast Track and Hold: AN13, Pg. 16, ‘Track and Hold (SMH2): ANB, Pg. 19, Variable Gain Variable Gain Amplifier: AN3, Pg. 5; LTC1043 DS Video Video Line Driving Amplifier: AN, Pg. 3 \Video Distribution Amplifier: AN4, Pg. 4 18 LT NBSUBJECT INDEX —_——_— ¢ Stabilized Fast Amplifier (32M): ANZ1, Po. 5 2-Channel Multiplexed Video Amplifr: ANA7, Pg. 33; NST, Pg. 1; LT1190 DS Differential Cable Sense Amplifier: ANA7, Pp. 33, LT1198 0S Double Terminated Cable Driver: ANA7, Pg. 33; LT1192 DS; LT1193 DS Ful Differential Line Receiver: AN47, Pg. 38 Low Gost SOMHz Voltage Controlled Amplifier: ONSS, Pot Video MUX Cable Driver (LT1227): DNST, Pg. 1 Ditierential Input Video Loop Through Amplifier (LT1964). NST, Po. 2 Electronically Controlled Gain, Video Loop Through ‘Amplifier (LT1228): DNS7, Po. 2 Video DC Restore (Clamp) Circuit (LT1228): DNB7, Pp. 2 Video Fader (T1228, LT1223): ONS7, Pg.2 Bidirectional Video Bus: DNSS, Pp. 1 Video Cable Driver: LT1220 0S Wideband—See Also Fast Ampitier Feed Forward, O Stabilized Butler: ANA, Pp, 2 LT1010 Wideband Amplifier AN16, Pg. 17 Wideband FET Input Stabilized Butter: AN21, Pg. 3 Gain Trimmable Wideband FET Amplifier: N21, Pg. 4 DC Stablzed Fast Amplifier, Low Bias Current (100Vfus, ‘MHz FPB): AN21, Pg. 6 Stabitized, Wideband Cable Driving Amplifier: ANAS, Po. 4 Fast Differential Comparator Amplifier: AN47, Pg. 39 Transformer Coupled Amplifier: ANA7, Pg. 39 Differential Comparetor Ampitier-Setabe Limiting and Ofte ANA7, Pg 40 Wideband, High Input impedance, Gain = 1000 Ampitier: LT1058 DS AMPLIFIER-CURRENT FEEDBACK AC Coupled ‘AC Coupled inverting: LT1229 DS; L11227 DS ‘AC Coupled Noninverting: L11229 DS; LT1227 DS Boosted Output 1150mA Output Current Video Amp: LT1223 DS Discussion Current Feedback: ANA7, Pg. 124 Current Feedback Amplifier “Dos and Don's": DN46, Pot Instrumentation Difference Amplifier: 11223 DS Video Instrumentation Ampiter: LT1223 DS Integrator Current Feedback Ampitier Integrator: LT1223 0S Single Supply Single Supply AC Coupled Amplifiers: LT1228 DS Video Video Cable Driver: LT1223 DS Cable Driver for Composite Video: LT1229 DS Video Loop-Through Amplifier: LT1229 DS ‘ANALOG SWITCH Driver +25V Analog Switch Driver: LTC1045 DS ‘Multiplexed 2-Channel Switch: LF198 OS ‘Multi-Channel Micropower, Low Charge Injection, Quad Analog Swito: LTC201 0S ANEMOMETER—See Signal Conditioning AUDIO—See Amplfier-Audio BACKLIGHT—See Regulator-Switching BALLISTOCARDIOGRAPH Heart Condition Monitoring: AN43, Pg. 8 BATTERY CHARGER Charger Constant Current Battery Charger: ANS, Po. 8 High Eficiency Dual Rate Battery Charger: ANS, Po. 9 Programmable Battey Charger: ANSI, Pg. 10 50mA Battery Charger and Regulator: LT1020 DS Battery Charger LT1086 DS Battery Charger: LTC1041 DS Wind Powered Battery Charger: LTC1042 DS Discussion Construction of Low Resistance Shunts: AN3T, Pg. 4 AT MEA 19SUBJECT INDEX Lead Acid Load Acid Battery Charge: ANS1, Pg. 7 Temperature Compensated Lead Acid Battery Charger: 1.71038 DS; LT117 DS;LT138 DS ‘witad Thermally Controlled NiCad Batery Charger: ANG, Po. 4; LT1001 DS “Thermally Controled NiCad Battery Charger: ANG7, Po. 2 Switched Mode Thermal NiCad Charger: ANS7, Pg. 3 Switched Mode Thermal NiCad Charger: AN37, Pg. 4 A 4-Call NiCad RegulatoriCharger for Notebook ‘Computers: ANSI, Pg. 11; DNS4, Po. 1 BLACK, HAROLD S. Feedback: ANAS, Pp. 41 BOOSTER—See Amplifier BOTTLE Baby Circuit Difficulty Rating: ANS, Pg. 1 BREADBOARDING TECHNIQUES Discussion Breadboarding Techniques: ANA7, Pg. 26; ANA7, Pg. 98 BRIDGE AMPLIFIER—See Signal Conditioning BUFFER—See Ampitier BYPASSING—See Capacitors caD Filter Contact Factory to Get FilterCAD: ANB, Pg, 1 Switeher Contact Factory to Get SwitcherCAD CAPACITORS Discussion ‘About Bypass Capacitors: AN'3, Pg. 25; ANA7, Po. 25 Hold Capacitor: LF198 0S CARTOON Back Page Jim and Celia's Caribbean Trip: AN25, Pg. 24 Mr, Cool LT1025: AN28, Pg. 20 Kick that Creaky Stuff Out: AN 35, Po. $1 Who You Gonna Call?: ANS5, Pg. 32 ‘Slow Application Note—Fast Amplifiers: AN47, Pg, 132 Backlight Light Up Your Lite: AN49, Pg. 16 Bridge Signal Conditioning the Golden Gate Bridge: ANA3, Pg, 48 CCFL—See Regulator-Switching CHRISTIE, S. H. Bridges Inventor of Wheatstone Bridge: ANAS, Pp. 1 CLOCK CIRCUITS—See Oscillators COMPARATOR ‘Additional Feature Circuits Driving Ground Referred Load: T1011 DS; LT311A DS Driving Load Referenced to Negative Supply: LT1011 DS; UT3t1A 0S Driving Load Referenced to Positive Supply: LT1011 DS; LIB11ADS Noise Immune 60H2 Line Sync: LT1011 DS; LT119A DS Using Clamp Diodes to Improve Frequency Response: T1041 DS; LT311A DS 2-Wire Comparator: LT1018 DS Current Fast Gurtent Comparator (16-Bit): LT1055 DS Fast Curtent Comparator (12-Bit): OP15 DS pac Fast Pre-Amplifier for Comparator: AN17, Po. 5 Discussion High Speed Comparator Problems: AN13, Pg, 4 Input Protection: LT1011 DS Input Signal Range: LT1011 DS Input Siew Rate Limitations: LT1011 DS Preventing Oscilation Problems: LT1011 OS Strobing: LT1011 DS High Speed Design Techniques: LT1016 DS Input Impedance and Bias Current: LT1016 DS Measuring Response Time: LT1016 DS 20 ATERSUBJECT INDEX ee Hysteresis Comparator with Hysteresis: LT1011 DS; LT685 DS Low Power Comparator with 6V: LTC1064-1 DS Single Supply Operation of LTC1064-1: LTC1064-1 DS Gas Linearized Methane Transducer Signal Conditioner: ANT P9.3 Instrumentation Amplitier Precision instrumentation Ampiter: ANAT, Pg. 6 Uttra Precision Instrumentation Amplifier: AN, Pg. 6; LTc1043 DS Precision, Micropower, Single Supply Instrumentation Amplifier: T1101 OS ‘Two Op Amp Instrumentation Amplifier: LTC1049 OS Intertace ‘AID Converter interface: DN29, Pg, 1 Motor Speed Motor Speed Controller, No Tachometer Require! LT1013 0S Oscillator Single Supply Crystal Oscilator 1OMH2-15Miz: LT1116 DS ‘Sample and Hold—See Aiso Single Cell ‘Quad Single 5V Supply, Low Hold Step, Sample and Hold LTe1043 Ds Strain Gouge Strain Gauge Signal Conditioner: ANNI, Pg. 7; Lrci0s4 bs Temperature Sensor Single Supply Precision Linearized Platinum RTO Signal Conaitioner: AN3, Pg 6; LTC1043 OS; LT1006 DS Linearized Platinum RTD Signal Conditioner (0°C-400°C to OV-4V): ANI, Po. t Cold Junction Compensated Thermocouple Signal Conditioner: ANT, Pg. 5 Single 5V Thermocouple Over Temperature Alarm Ure1042 0s Transmitter ‘4mA-2OmA Gurrent Loop Transmitter: AN11, Pg. 9 4mA-20mA Floating Output for Curtent Loop Transmit: ANT, Pg, 10 LT NE 47SUBJECT INDEX 4mA-20mA Digitally Controlled Current Loop Transmitter: ANS, Pg. 6 ve Uta Linear Voltage to Frequency Converter (100kH2- 4.1MH2}: AN, Pg, 7; ANZ3, Pg. 13 Uta Linear, Micropawer V+ (0-SV to O-10kHz): ANAS, Pg. 15 Voltage to Frequency Converter: LTC1040 DS Voltage Regulator Low Dropout SV Reguiator: ANS, Pp. 3; LT1013 DS; LIC1044 DS: Low Voltage Regulator: LM10 DS. STRAIN GAUGE—See Signal Conditioning ‘SWITCHES—See Also Analog Switch—See Also Driver Analog Low Charge Injection Analog Switch: LTC201 DS High Side High Side Switch (1.54): LT1188 DS THERMISTOR—See Signal Conditoning- Temperature ‘THERMOCOUPLE—See Signal Concitioning-Temperature ‘THERMOMETER—See Signal Conditioning-Temperature TRIGGER ‘Adaptive Threshold 0MH2 Trigger with Adaptive Threshold: AN7, Pg. 69 VCO—See Oscillators VOLTMETER RMS Wideband True RMS Voltmeter: AN47, Pg. 62 WEIN BRIDGE OSCILLATOR—See Oscillators WHEATSTONE, CHARLES Bridges Bridge Thiet: AN43, Pg. 1 WILKINSON, D. H. AD First Electronic A-D: AN43, Pg. 42 WILLIAMS, MICHAEL Son Future Circuit Hacker (If He Wants to): ANAS, Pg. 24 WIND SPEED—See Signal Conditioning z00 ‘San Francisco Birthplace of Figure 16, AN23: AN23, Pg, 13 48 LT WERSECTION 1: APPLICATION NOTES ATELT tae INDEX SECTION 1—APPLICATION NOTES anet ane ANAS aN ANS ANG ANAT ana aug nso Ns ans NSS ANA ANSI ANA2-4 ‘Questions and Answers on the SPICE Macromodel Library... Voltage Reference Circuit Clletion .. Bridge Circuits: Marrying Gain and Balance 111074/.71076 Design Manual... . = ‘Measurement and Control Circuit Calle rs and Designs on the Night Shit... Efficiency and Power Characteristics of Switching Regulator Cireuits . High Speed Amplitir Techniques: A Designer's Companion for Wideband Circuit... ANAS-1 ANAE-1 ANAT Using the LTC Op Amp Macromodels: Getting the Most rom SPICE and the LTC Library ANE Iumination Circuitry for Liquid Crystal Displays: Tipping the Light Fantastic ANAS Interfacing to Microprocessor Based SV Systems. ANSO-1 ANS ANS2-1 ANSI-1 ANSI Power Conitioning fr Notebook and Paimtop Systems Linear Technology Magazine Circuit Collection, Volume 1 Micropower High Side MOSFET Drivers Power Conversion from Milliamps to Amps at Ultra-High Etficiency (Up to 95%) ALT WERrt AR Application Note 41 TECHNOLOGY April 1990 Questions and Answers on the SPICE Macromodel Library Walt Jung INTRODUCTION This document is provided to answer some ofthe potential questions raised about the Linear Technology SPICE macromodel library. It assumes that you have a diskette copy of the library already, and want some background andior additional information, Those needing a copy of the current SPICE macromodel diskette may obtain one by calling (800) 637-5545, The macromodel library is available on IBM PC format (high density) diskettes, in either 5.25" r 35" styles. If you should have a question not answered by this text, you may call LTC applications at (408) 432. 1900. For more general SPICE questions, references are provided, GETTING STARTED Question (1): What hardware and software do | need to get the LTC SPICE model package up and running? ‘Answer (1): Obviously, you frst need an IBM PC compat ble computer witha high density dive, either §.25" or 35°, Beyond that, you will need only @ minimal amount of RAM (612k or more), With this SPICE macromodel diskette, we have not just given you a model library, we have also Tur- nished a working demo copy of PSpice™ from MicroSim, Tight on the diskette with our model software. To run this, demo copy of PSpice, there are no minimum CPU speed, display or printer requirements, Unlike the production ver- sion, this special version of PSpice does not requite a co processor to run, $0 you can see the models at work almost immediately, with no configuration or file editing necessary. The demo PSpice version will run up to two models at ‘once. To see it operate, all you need to do is slide the diskette into your computer, [og onto the A: drive, and type in:“DEMOLTC ". The rests all automatic! Question (2) That sounds a bit too easy fsn't there some configuration necessary to run SPICE? Also, is there some “on diskette” help available? ‘Answer (Qt To minimize the configuration necessary for P Spice the graphics display Probe" comes pre-configured fora “text” style of soreen display, one which will display € plot on any monitor. Once you get your feet wet, you will want to eit the Probe configuration fl," PROBE.DEV” to better match your equipment this file is in the SPICE directory Yes, there are two help files on the diskette, One, “README.COM" is in the root directory, and it lists the specific LTC device types modeled. To use it type “README ", then just follow the on screen prompts. The information can also be printed out, if de- sired. The second help utility is “README2.COM”, and it | in the SPICE directory. Ithas information on PSpice and Probe in general, and this demo version in particular. From the SPICE directory, type "README2 " to use it, and follow the prompts. Note that this help fle has the detailed info needed to customize “PROBE,DEV”, with an ASCII editor. We recommend printing out the information inboth ofthese help utilities for future reference ‘Question @ Where can get more information on PSpice and Probe? ‘Answer (3) The two help utlites mentioned will serve you here, or write or call MicroSim (mentioning this demo diskette) at MicroSim Corporation 20Fairbanks, Ivine, CA 92718 (714703022 ———————— ——— LT WEAR AN41-1Application Note 44 Question (4): Will the devices in this LTC macromodel library run on any version of SPICE? Are they copy pro- tected or encrypted? ‘Answer (4: You can use the LTC models with other ver: sions of SPIOE, either on a PC or another computer sys- tem. All ofthe LTC SPICE model files are furnished in an ASCII file format, which are actualy usable on any type of computer; a PC, a workstation andlor mainframes. If you don’t intend final use for them on aPC, they can be trans ferred ftom the PC environment toa dissimilar system via ‘modem, using an error checking protocol (such as Xmodem or Kermit) ‘As was noted, the models are in ASCII form, and are de signed to be Berkeley SPICE 26.6 compatible (generic SPICE), They were infact developed and debugged using PSpice, but other vendors’ PC based SPICE implementa- tions can be used with them, and they will also work on workstations and large mainframes (once transferred). So, while we can recommend PSpice as highly useful, the generic nature of our models allows their use on virtually any 2G.6 compatible host. Since the models are ASCII files, they are easily copied, and we encourage use on diverse systems. Model encryp- tion, in our opinion, is counter-productive to our goals of widespread LTC model use. Infact, it could be said that it is contrary oa “universal” SPICE 26.6 ASCII file format. MODEL COVERAGE Question (6): How many of the LTC linear devices are now included in the SPICE macromodel library, and what de- vice types are covered? ‘Answer (6: Right now, most of the LTC operational ampli fier models are already contained in the lirary. This col- lection of 40-0dd part numbers includes NPN and PNP bipolar and JFET input amplifier types. There is also an in strumentation amplifier, and it is hoped that more ampli- fiers will soon follow. Other linear devices (comparators, ‘AiDs, references, regulators) are not modeled as yet. MODEL SUPPORT ‘Question (6: If your models are in fact ASCII ies, that means they are easily edited and changed, Does this mean that | can “tweak” a model to suit my own specific needs? Answer (6: You sure can edit the models, but you'd better Understand all the implications of it before doing so! Modifying a model by definition makes it something other than what it was when released, Please note that LTC will ‘only support models in ther released form, and at our dis cretion, Does tis then mean that you won't ever be able to make useful model changes? Not realy, if you just use ‘common sense, and keep an original reference copy ofthe model, in “as received” form. Common sense means that you don't change 10 model parameters, then call us up and ask why “ut” model doesn't fly. LTC (or any other IG vendor} won't step info such a Pandora's box! Question (7 What if| really do have a problem with the models? Will be able to get help from LTC? Answer (7k: Problems using SPICE models will generally fall into one of three types: 1) Problems with the user's ‘system which ate hardware andlor software related, 2) Problems of application, that isa circuit application which presents some general modeling difficulty. Or, in some cir- ‘cumstance, 3} A real problem with the model itself. Obvi- ously LTC cannot be responsible for the correct operation cof your computer system and application of your software, 0 we wil not become involved wit case 1), Case ), prob- lems which can be directly attributed to an LTC model will be serviced at the discretion of LC. Case 2)is the most dificult ofall, since it can actually be open-ended, with no practical solution. For example, you may need to simulate a circuit using an LTC model, but ssome other crucial part is not modeled, say something from another vendor. While we can sympathize with this dilemma, we could not logically be expected to help de Yelop such a model. Due to time and manpower realities, we may not even be able to help develop @ new model for ‘one of our own parts (on short notice). More on this and related areas is answered inthe next two questions. AN41-2 ATEApplication Note 44 ee Qu ‘Answer (8): Users should bear in mind that software mod- els are at their very best just approximations of the real thing that is they amount to clever apings of actual ICs. UTC does guarantee (an fully supports) its IC devices, the ones you plugin to do genuine work on your PC boards. By way of contrast, models are software support items, and are supplied on an “as is” basis. With regard to their use and performance, they should never be confused with the performance of the rel item. Think about this as in the context of what gets shipped out your door as product, ‘that is real, and measured performance results on it vali- dates your equipment guarantees. Model results will likely mean little or nothing to your customers, since they are much less tangible to your produc. tion (8): Are these models guaranteed to run? Question (@}: What if a model functions, but it simply doesn't reveal everything | want itto? ‘Answer (9: iis entiely possible that a given model may fall short of specific expectations, especially if they tend towards the unrealistic or the impractical. We don't get paranoid when areal op amp has finite gain as opposed to infinite, we consider the implications in context and pro- ceed from there. It is simply impractical (at least at this, Point in modeling evolution) to make a macromodel emu- late a device's specs with 100% fidelity inal regards, and still remain compact, fast running, and free of conver gence problems. What we have done in developing these models isto take into account all those performancelspec areas we saw as ‘most important, and then pay serious attention to them in the models. Granted, this is a judgement call on our part, but we hope itis @ reasonable one. This does not rule out special cases, where a model may be optimized to satsty a given set of customer requirements, and LTC will re spond to these as they arise, And, we will welcome inputs ‘on future models! PARAMETERS MODELED Question 10}: OK then, what are the specific performance areas and specifications which these models do cover? Answer (10; The LTC op amp macromodels simulate a number of performance areas and specs, 28 noted in Table 1. We have chosen typical parameters from the de- vice datasheet in generating these models, and room tem- perature operation. Table SPECIFICATION MODELED? TWODELING ACCURACY Vo Yes High lglos ws High Gatranowiamn vs Mesum Phasemargin Yes Medium sR Yes Medium Avia) ves High cure Yes High Psa No NA Vou + and -) ves igh ke vs High Fo ves High k ves High & Not Na i Not NA “The ode topology used does nat addres input stage oie serlation Usethe LTC" NOISE” software nsoad which dos model te LTC 09 _ampstorvotage ane curen noise(see question 2, In addition, there are functional areas of performance ‘where modeling attention should be directed for realistic behavior For example, if an op amp is designed as @ sin le-supply device, then the input/output ranges of the model should include the V~ rail (ground), with good ao ‘curacy. If clamping networks are used at the input, then the model should reflet this, and clamp atthe same level Ifthe amplifier is pole-zero compensated, its transient re- sponse will not resemble a classic single pole plus para- siti rollof, and the model should address this. Table 2 summarizes the LTC model characteristics in these func tional regards. Table? ‘GnaRACTERIsTic | WODELED? | ~"WODELING ACCURACY Muitipiepolaero ve | Wedium Single supp 6, we | igh CCommansmodeciames | Yes, Neston Dierentaieanps | ___Yes etiam LT WR AN41-3Application Note 41 fl ey MODEL TOPOLOGY Question (11); Sometimes it appears that the terms “model” and “macromodel” are being used interchange- ably. there a difference, and what defines a macromodel? Answer (11) “Model” is a genera term, and a "macro model” is a specific model form, one which is more com- pact and efficient. To be historically precise, the op amp macromodel was devised by Boyle’ originally, and has ‘been used since then. An op amp macromodel differs from a full “device level” model in that key parts of the circuit are defined by the use of synthetic SPICE elements, that is controlled currentivoltage sources, etc., along with pas sive circuit elements such as Rs and Cs, and a minimum number of (simplified) semiconductors. By reducing the number of semiconductor junctions to a minimum, an op amp macromodel can achieve simulation times 5 to 10 times faster than a device level model, and so easily allow multiple amplifier simulations for large systems. Question (12): This sounds like an area of tradeoff! Certainly @ macromodel using synthesized elements can- not perform lke areal device level model can it? ‘Answer (12 For many aspects of performance, one can: not tell that macromodeling has been used, For any per: formance aspect with simulation speed as a criterion, a macromadel approach will almost always be faster, and with reasonable fidelity, when properly executed. A qualifying note here ... comparatively speaking, we will rule outa SPICE “ideal” op amp model, which can be bull with one or a few controlled sources. We feel this is too far removed from a real IC op amp, as it will be devoid of real bias currents, offset voltages, slew rates, et. The most useful macromodel approach is one which carefully balances the mutual goals of reasonable fidelity to the real part, along witha realistic simulation time, and finally the overall vigor or robustness of the model. The importance of the first two of these points cannot be ‘overemphasized in considering the evolution of op amp macromodeling. As a case in point, itis not a widely useful Note :Boyle, 6. Mecromodeling of integrates rut ‘oha B (paratioal Amplifiers, EEE Joural ot Padesor,0, SodSlate eu, Vol SC, f, December Solomon, JE a thing to improve say, the fidelity of an op amps transient response with a complex model which departs from the simplicity and speed advantages of a more basic model. In. the extreme, one might find a board's worth of "more so- phisticated” op amp models which takes all night to run simulations, or worst yet, won’trun at all! Question (13): What is meant by “won't run at all2” Is that related to the reported convergence problems of SPICE? ‘Answer (13) Yes, there are macromodel types which have been published which have problems with SPICE conver gence for certain types of simulations. In the extreme case, a solution cannot be found and the simulator Just uits, reporting an error. “Tweaking” of the simulator de- faults may be necessary o make it run, and then slowly. “Try a unity-gain follower small signal transient analysis to separate the macromodel wheat-fromchaff, and to see what a‘robust” macromodel implies. To our minds, itis simply not enough that a model yield {good fidelity with the electrical results, it should also do 0 with reasonable speed and not be overly sensitive to system memory, applied signal, biasing, andior supply voltages. So, we have purposely included a transient test for the LT1007 (one of our more complex models) in our ddemotoillustrate this point. We wil be interested to learn ‘of comparative tests, using other models (see Appendix) ‘THE BOYLE MODEL ANDLTC IMPROVEMENTS Question (14: We take it then, that your LTC models are based on the Boyle macromodel. Is it true that this mode! cannot handle differing transistor types, and that it has other serious deficiencies? ‘Answer (14: Yes, the LTC macromodels ar in fact derived from the basic Boyle model. We should hasten at this point to note that this model is apparently little under- stood in terms of real versus perceived limits! In fact, many Boyle derived models (and we include LTC’s here) are elated topologically, but have been enhanced in many different and significant ways. Perhaps a fitting analogy is, that all present day cars using internal combustion en- gines are in a sense related to Henry Ford's Model . This — AN41-4 LT WARApplication Note 44 ee is of course intentionally dramatized to make the follow: ing point: Most of us will have no trouble at all appreciat ing that a basic design concept can be usefully enhanced in many aspects, while still retaining @ fundamental lineage. Yes, the original Boyle model used NPN bipolar input stage transistors, in the context of a 741. But replacing them with PNP types simply changes the connections, not the basic design equations. FET transistors were added to the Boyle model in 1979, in the paper by Krajewska and Holmes, in both JFET and MOSFET form. Anyone imply- ing that a Boyle-based model can't handle variety of tran- sistor types is confused as to history! ‘Question (15): But the Boyle model cannot handle multiple poles and zetos, and is therefore not suited for accurate transient response simulations. Some companies have discarded that approach long ago. How can you guys stil be using, with all those problems? ‘Answer (15): The LTC macromodels were developed with an altitude that transient response fidelity, while important, should not necessarily be achieved atthe expense of many ‘other equally citical performance areas. Accordingly, LTC macromodels use extensions tothe overall Boyle topology for additional poles and zeros, as opposed to discarding it outright. This technique allows additional control over phase response, while stil retaining relative simplicity. The T1007 demo example cited uses this form of compensa- tion, an the results can be seen inthe demo example (see ‘Appendiy). This approach does have the virtue of stil retain ing the overall form of the Boyle topology. While it may be possible to more accurately simulate an OP-27, for example, with upto 10 pole-zaro par networks, a legitimate question arises: Is it worth the substantial overhead of the many additional active stages, for each and every simulation, however trivial? Every element added to a SPICE macro- model extracts some penalty in terms of speed, memory required, or overall model vigor, Carried tothe extreme, sig- nificantly more complex models may even preclude multi ple amplifier simulations, defeating the very purpose of macromodeling. Nole2:Kiajewska,@, “Macromodeing of FETBpolar Operational Moines,FE” Ampitits,"/EEE Journal of SolStte Geuits, Vol 8-14 86, Dacomber 178 Question (16): The last statement seams to be a contradic- tion, as you have added additional networks, diode clamps, and entire circuit sections to model the unique in- ternal features of your op amps. If you question others ad- ding additional stages, how then can you justify it? ‘Answer (16): The answer lies in exactly how one goes about it! We certainly do recognize the potential penalties these added features can represent to users who simply may not care about a particular detall which they may be simulating. So, we have generally implemented them in ‘ways which allow them to be easily disconnected, For example, the diode clamps at the inputs of the LT1078 series can be disconnected if they get in the way, as can the differential clamps forthe LT1007 (and others) Inother ‘words, we haven't locked anyone away from stripping the model bare, 80 to speak, should they so wish. In most in- stances, a” in column one ofa line is all that is needed todeactivate it. Question (17: The Boyle model uses a ground node in- ternally, node zero (node 0). Isn't it true that this creates simulation erors for power supply and load curents? ‘Answer (17): The model we use does have a node 220 In ternally, which happens to be the default common (ground, of node 0 for SPICE circuits in general. The out: put signal current of our models therefore flows through this common node, and tolfrom the common node of the Coverall circuit in which it is used. Usually this is @ common round between source(s) and the loads) In our models (and most others which operate similarly) the actual model output current comes from controlled sources, which are referred to ground (node 0), inside the model. To an extent, this node voltage can be somewhat arbitrary; that i, iis possible for it tobe refered to other points, and the model wil still operate normally. For exam ple, the “node 0” in single-supply op amps such as the T1078 series gets tied to V~ inthe main circuit, when the device is used in a singlesupply mode (since the V~ pin, #4 is tied to ground), All still works OK in this fashion. If the very same model is used with dual supplies, obviously “node 0” gets referred toa level which is intermediate be ‘ween the two supply levels, such as + 15V and ~15V. AT WEAR AN41-5Application Note 44 ee AA belter understanding of how this operates can be realized if it is appreciated that the SPICE controlled sources do indeed have two terminal floating outputs, \hich can be referred to various levels. Thus, the op amp's ‘output (load) current can actually be different from the power supply rail current, forthe case where the internal ‘common node (node 0) i not tied toa supply rail Is all ofthis a real problem? It actually becomes more one ‘of bookkeeping, or adding up al the currents propery. We hopeit is then not a great one, since the total current drain will stil be that in the load, pius the static drain ofthe op amp itself. We have taken the step of making all the mod- els reflect an internal DC power supply current which is that value typical to thelr operation (the real (T1007 draws 2.7mA, therefore lee + Ip totals 2.7mA in the model) ‘SOME GENERAL SPICE QUESTIONS ‘Question (18; All of this seems to be implying that SPICE simulations can be quite burdensome, in terms of getting up and running toa point of realizing useful results. What can be said about this aspect to someone just geting started with modeling? ‘Answer (18): SPICE simulation is unquestionably very in volved, and it is also quite demanding of analog circuit skill along with general computer proficiency. Its just as demanding of the computer hardware as well. While you don't need to be a programmer to use SPICE efficient well developed computer skills definitely do help. More im portant to overall effectiveness however isa strong design ‘engineering background, in particular one in analog cir cult design. This should seem obvious, since SPICE Is an analog simulator, But, itis being stressed here to make the point that someone proficient in analog design wil likely pro duce quality SPICE results much faster than one equally proficient in digital design, with both starting from zero. Why? Because SPICE has its quirks, which must be dealt with to use it most effectively. By and large, there ae of- ten analogs between SPICE software problems and linear circuit problems. Thus, it helps in dealing with these types of problems to be comfortable in “thinking analog,” Ana- log designers also tend to be welldeveloped in terms of patience, and SPICE if nothing else will be a challenge to ‘one's patience! ‘These generalizations aside, SPICE will definitely be most demanding of hardware, as the bigger and faster the computer, the more quickly you get your results. The PSpice demo supplied with this macromodel library is quite exceptional in terms of what it does, but this does not change the fact that the full version counterpart is more demanding on the hardware. In the SPICE world, hardware dollars for RAM, coprocessors, and faster CPUs buy overall speed and complex circuit capability. Question (19): OK, assuming that these general require ments can be met, what other potential bottlenecks lie in the path of my trip towards SPICE bliss? ‘Answer (19: Given adequate resources in terms of man- ower and computer hardwarelsoftware, the next funda- imental obstacle isthe availability and quality of models. One certainly wouldn't want to build up a breadboard cir cult faced with the necessity to make all the op amps up from scratch, but that is where you'd stand for a SPICE simulation without adequate madels. Even assuming you had the time and manpower resources to make your own models, there is the very eal question of their technical sufficiency. Now, this actually brings us full circle, with the IC man- ufacturer such as LTC entering the picture as a supplier of ‘op amp models for their catalog of devices. With this ci cumstance, you, as an IC user, ae in the very best position to do useful simulations, since itis in the IC manufactur ers interest to supply you with models that reasonably re- flect actual device performance, This establishes your ‘confidence in the devices as well as speeding your design towards completion, with a minimum of hassle with models. Of course, this does not make the modeling problem go ‘completely away, it only lessens it appreciably, with regard to LTC as one vendor. You still need models forall patts of your circuit, beyond the op amps. This will very likely continue to be a serious challenge in the months and years ahead, as more and more vendors become ac- tive with modeling support of thelr devices. AN41-6 ATER‘Question (20): The bottom jine seems to be that the SPICE user in today’s design world has their work really cut out for them. What level of confidence can be expected with SPICE op amp simulations, given typical designs and your models? ‘Answer (20: SPICE simulation results can and wil vary in fidelity with regard to areal live op amp, dependent upon the type of circuit in use. Generally speaking, DC and low frequency AC results are good to excellent, and the mod- els do a nice job with bias currents offset voltages, and most input related parameters. By contrast, noise is not modeled well at all with the enhanced Boyle topology we ‘employ, but we do provide a useful option here, in the form ofthe alternative software, Alan Rich's program "NOISE? (available as noted. ‘The high frequency response of LTC wideband op amps such as the LT1007 and OP27 is modeled with multiple Poles and zeros, which yields a reasonable approximation to the real device's transient response (see demo), It is wortharile noting thatthe precise pulse fidelity of a sin- gle given sample of a wideband amplifier isin reality a “moving-arget.” This is because device-to-device produc- tion variations can be of the same degree as the errors in their current modeling! Therefor, there is some question a to just what benefit a more precise high frequency model would provide, ‘The particular performance area of transient response has been and will continue tobe one of challenge in terms of better models (without pitas Its also likely to continue as one of controversy, in terms ofthe best overall solution tothe technical challenge. Note: Rich A. “Noise Calculation nOp Amp Cres," LTCesign| Note #5 September. 188, (rogram aralabeon ike cal 60) 697545, AT WEAR Application Note 44 Output stage performance of the LTC models is good to excellent, with accurate current and voltage limits, and ood simulation of the small signal characteristic, par- ticularly the single supply devices near the als. AlLinall, we feel that this model collection is a quite use- ful addition to the analog designer's bag of tricks. Like the SPICE program itself, the models are no panacea, and they need to be used carefully and wisely. You will very likely encounter many crossroads with SPICE models, and often be tempted to decide between the lab results and a SPICE simulation . . . which one to believe? Our advice here is to not accept either without first carefully ‘checking, but do be inclined to lean towards the lab perfor. mance of the real device, particularly if it passes all the Conventional analog bench tests ... Remember, that is ‘eal by default, while SPICE is a mimic by default! ‘We hope that the LTC mode's serve you well, and welcome your feedback on them, ‘SOME GENERAL SPICE REFERENCES 1.Nagel LW, “Simulation Program with Integrated Pederson, 0.0. Circuit Emphasis (SPICE),” University CA @ Berkeley, ERL-M382, 1973. “SPICE2: A Computer Program to Simu- late Semiconductor Circuits,” University CA @ Berkeley, ERL-M520, 1975. 3.Cohen,. “Program Reference for SPICE2,” Univer. sity CA @ Berkeley, ERLMS92, 1976 2. Nagel, LW. Avallable trom: EECSIERL Industrial Support Office 497 Cory Hall, University CA @ Berkeley Berkeley, CA 94720 AN41-7Application Note 44 APPENDIX The LT1007 Op Amp Macromodel Transient Test Demonstration 0310290 + Evaluation PSpice (LT 3.08) x 08:41:27 LTCLT1007 VOLTAGE FOLLOWER DEMO: OUTPUT = (55) (edited for claitylrevity; comments italicized) MATRIX SOLUTION 6.09 4 MATRIX LOAD 874 READIN 248 ‘SETUP 0.05 DC SWEEP 0.00 0 BIAS POINT 198 32 ‘AC and NOISE 0.00 0 ‘TRANSIENT ANALYSIS 2a 485 ouTuT. 022 TOTAL JOBTIME 2653, ‘Shown above are (edited) portions ofan actual output fie, “DEMO.OUT,” as run from files on a released LTC SPICE ‘macromodel diskette. The test is a small signal, volage follower transient test. The computer used is @ 16 mega- ‘hertz 286 w/067 math coprocessor, and the times shown in the feft column reflect operation from a RAM disc. Actual running times for other situations wil vary. We invite relative comparisons using other models for this same transient test (edit “DEMO.CIR,” to include your compar- ‘son mode). ‘Shown below is the LT1007 test waveform simulated in this transient analysis, as seen on the screen. {TC1T1007 Voltage Follower Demo: Output = Vi55) same | ~ t tf — mel is oe w io “Ppl” and "Probe are trademarks o erin Coot, AN41-8 LI WEBNt | \R Application Note 42 TECHNOLOGY Voltage Reference Circuit Collection Brian Huffman This application note is a guidebook of circuits featuring voltage reference ICs in various configurations. The cir- cuits shown are both basic as wellas complexand employ many popular IC references. Included are 2-terminal and 3Herminal references in series and shunt modes, for June 1 991 positive and negative polarities, in voltage and current boosted versions. Additional circuit information can be located in the references listed in the index. The reference ‘works as follows, ie., ANB, page age 2; LTC1044 DS = LTC1044 data sheet. Application Note 8, DRAWING INDEX fice mE ract___nerenecesounce Peril Re 12 Ou, Mtopwe Reece om 15 ate aw 1 roots 12 Out, Meropne Renz am 9 Bt row 0 trios 12 0upat Meepne Retr wt snp tap Range rave st 124 wt Moyne Cue Bost Rete EOnA) Fae 2 1 trios 25V Out pw Rees awe? n Cronos 25¥/ Ou Meow Ree wih Wik pt Voge are rowed it ‘Terminal Reterence — 25¥ Oa Tenet eee Ten Fowe? 5 Ls 08 2 up Teno om To Foues 5 3808 251 Oat Reece. 8% Tn ge rout 5 ‘rons 0s 2 5¥ta wn Wr age. rues it ‘tioosas Bae Map TIO ates Rees Fours 7 ‘rors Basi Hot T1021 Ses tence Fee 8 7 cries Bose ok TOD Sees Reece raw 20 7 trieros 5 up Rta Tn age Fowes 3 ‘rioesos 5 Out Rete Raw i age. Fowes $ Cries 5120 Out Ted Rete, raures $ tres 08 Bast Sores tee Fove2i 7 ia 0s lar Reference ~ ~ SOV Oda Pre Releece. foe38 ‘0 ues 08 1125/4 ap Pepe tne Towed ‘0 ¥1 27245 Out Set Bute, Mune eee Tewest tt urireos {HOV Gua Rees raves? ‘0 225V dupa Reemet ra ‘0 rte 08 12. On, Preface en LT WEAR AN42-1Application Note 42 DRAWING INDEX (Continued) HGURE TILE AGURE + PAGE AREFERENCE/SOURCE Boosted Reference 1-28 Output, Meropower, Current Boosted Reference (00a) Figure 52 1 ‘Gurren Boost Negative Relerence (LT1019-25,-, 10) Figue 37 8 Lr1019 0s ~10V Output, Curent Boosted Reterence Figue 38 10 Lrv031 os 109 ouput wth Vi Your Shut Resistor for Greater Currant gue 53. 12, Lria31 0s 10V Oetgut wth Eecnal PN or Boosted Output (100mA) Figure 54 12 T1031 0s 10V Boosted Opt with Curent Lint (100). Fiquo 55. 12 Lr1031 0s Sis Raterenc wth PRP Bost Figure 56. 12. tres os ‘utered Reference 254 Output, Low Noise Reterence gue 6 15 Lr1009 0s Precision High Curent Reference (15a) gue 57 12 AN2, page 7 OV Output, Low Noise Reference gure 62 14 Single Supply, -10V Output, Temas Low ois, Low TC Reference que 63 14 5V Output, Curent Boosted Negative Reference with Overload Protectan Fgure 60 13 10V Ouipi, Low Noise Reference Fqure61 14 T1031 05 7V Output, Lom Nose, Low Orn Reference. gure 5 18, \7z1000 0 Butered Standard Col gue 8 13 rior ps Standard Grade Variaba Voltage Reference gue 59 13 \rot0s208 ‘Mcropower Roerence 1.2V Output, MiropowerRelerence trom 1.5VBaltry Figura 44 10. T1004 DS +1260, 248V Output Sel Butfeed, Micropower Reference (100mA). Figue 51 1 urii78 0s 1.24V Output, Miropower, Curent Boosted Reference Figure 52 1 T1004 0s 2.5 Cutt, Meropower Reference gue 47 1" Lr1008 0s 2.5 Output MicropowerRearece with Wide Input Votage Range Figure 48 t ‘ogaive Output Reference ~ ~ Shunt Operation ofa Saris Device (LT101825, 5, 10) que 36. 8 ‘currere Boost Negative Reference (LT101925, 5,10) que 37 8 Lri018 0s Shunt Made Operation of a Series Device (LT1021-7, 10) gure 32 9 raat 05 ~5V Output Reference (LT1021-5) que 33. 9 raat os 0 Output fora Seis Dove gue 34 8 T1031 0s TOV Outpt, Wide Input Range Figure 35. 9 T1031 0s ~10¥ Output, Guren Boosted Reerence Figure 38 10. T1031 0s Power Reference Regulator Circuits ~ Programmable Negative Output High Stabilty Repuator Figure 63 2 cri 08, igh Guten arable Ouput Supply Figue 88 2. T1004 0s ‘Simple igh tbilty Reguator Figue 7 19. T1008 08 High Staity Negative Regulator gue 78. 19. ra33 0s Rogue with Reference gue 79. 20 Nogate Output Reguiator with Relerence que 80 20 Low Temperature Coefcet Regulator. Figure 88 2 Pracision High Curent eterence 15) gues? 2 2, page? 5V Output, Low Dropout Miropower Regulator wi 2SV Releence gure 85 2 ria20 0s Prograrmable igh Stabity Regulator. que 82 21 igh Curent Regulator wth Reference Foue a7 2 11086 0s AN42-2 AT NEARApplication Note 42 DRAWING INDEX (Continued) lOURE TLE ___rounE # PAGE /REFERENCE/SOURCE Power Reference eguatr Circuits (Cominued) ‘5¥ Output, Low Dropout, Miropower Regulator wth 2 SV Reternce and Shutdown Pure 86 23 L120 08 ‘Simple Stacked Reorence Regulator. Figure 84 21 _ Series Reterence Wide Tim Range (25%). que 25 8 Lr1019 0s Narrow Tem Range (202%) gue 26 8 Lrio18 0s 10 Output, Trimmed to 1.240. Figure 29. a Lr1019 0s 5 Output, Trnmed 0 5.1200 Figure 23 8 Lr1019 08, 10V Output, Ful Tim Range (20.7%) Figue 22 ? ria2t os 10V Output, Restos Trim Range for Improves Resolton que 23 7 Lr102t bs 10 Outpt, Trimmed to 10.28 que 27 8 11921 05 Low Noise Statistical Vota Standard Fqure3t 9 5V Output, Fast Setting, rimmed Reference Figure 20. a Lrve27 os 10V ouput, Trimmed Reference Figure 24 8 rast 0s Shunt Reference” Precision Divide by Two Fqwe 15. 6 Lrotots 0s Precision Mutipy by Two Faure 18 6 Lro1oss 08, Lnra-Precision Voge Inverter Figue 17 6 Lieto Ds 25V Reterence (LT14312) Figure 10. 6 Lrvaat os 2.5 Reference (LT1434) Figure 1 6 T1431 os SV Relerence Figure 12 6 Ur4st os Increasing SV Reterence gue 13 6 Lraat os Programabi Reference wth Adusabe Curent Lint Figure 14 6 Lriaat os Bsc Operation ot Shunt Reference Farily Figure 1 5 Lr1004 os Current Source Stabiaed Raarene Fgure2 5 Luws34 083 ow To Curent Stabze Reference Fgure3 5 Temperature Stabiized Reference ~ — —_ Butered Standard Col Replacement Figures 1” 10V Output, Set ised Temperature Sabiaed Reteance Figure 70 17 7399 08, Ltea-rcision Variable Votape Reference. Figure 71 18. AN 2986 10V Ovput, Temperature Sabized Retarence Figure 72 18 Luwss9 0 Temperature Stabized TOV uterad Reference Figure 73. 18 Uro1208 6 95V Output, Tempecatue Stables Reference (Vy, Figure 78 19. 1399 08, {6.95 Output, Temperature Stabilized Reference (Vy Figue 75. 19. 1399 0s, 6 95 Output, Temperature Stabe Reference (Vy Figure 76 19. L998 10V Output, Tanperatre Sabla Retee Fque 66 15 Lr1019 05 Low Wise, Ura Low Ort, Long Term Stabe 7VPostveRelerence Figure 67 16 Lrz10000 Low Noise, tra Low Ort, Long Term Stale Negative Voltage Reterece Figure 68 16 12109005 ‘pend ~ — Precisan Resistr Selection os Aopends a Capactor Selection Popendix 8 27 TreningTechrgue. Aopendin€ 29 *See also 2-Terminal References ee AT WEAR AN42-3Application Note 42 - TUMOR OTe ve VOLTAGE REFERENCE SELECTION GUIDE ne Sra sg at YoUTAGE ext vouuae ) rust cocume | ‘Sraate ve | ‘waa reuperarune ont, | cunnent ance | Peoatce wotis) | ‘heave | oewce | pomrconmy cuanoe_ | consupntr carne |") uuon FEATURE im sao. | Tort ore) Taxezn | 15 Tipe Stas | uioouses2 | atom foyarozmna | 18 Merger Sie | Untacs a >on im) ayaa | 18 Le Tope win Nhu toes sie | crows {059s ayrwans | 15 Coeteenpovera tu Rees zee | uus12 Zev gator | 1s ecpower sie | Wswa.2 Zope) gatozom | 43 oper 5 on] ones “aren Binoank | 15 isaponer toms | Uioncse2s | rem ee But 2004 5 fom | tron ev ot ‘omarorom | 1a va | tromse ‘Soom ma ‘omatozmd |] 08 2am | trinwces ‘Bonn na, tam wa Press oa see | Uineas ev int lagatosooa | ta Cone Prpce, | mess fe ms) fonawiom | 1a oma Purest ao | binss 2tron om) guava | 15 ecpner iis | besos 2pm} Byawaen | 18 Mowporer ae | Ur 85 (ray) toa a STermal ow oot a | ce ‘a\ras 1m wk “Terme ow Dr tows | Goo. (ro ism a ‘Terma aw be som | Useon ‘ores ism tn Tema aw Or 5 soa} troweas es Tank Mk Fron Src a0 Som | Uno pom (oa Tank Mi ron mo ai, | Uuorecs Soom a) Nama ° ‘ey bow Ot Sooo. | Unters opm ae tana a Ye Tt tatoo Sie | Uranoes ‘Bonn na) tana a tow co ntact ay | tiatcse orp ne) Vim 1 {oe et Petes soma | tien doom ina Zim us {one Ta Tore foams | Ue zoom ira) 2m tin {eT Teer soa | tneate Soom na) ome Wk aw Tees tosses | tre ‘opm no) 20m a ew Te Teer soe | thre T35pm(oas Boma we Uw Tae fom | Um om ina fomatotom | o5 cor ero fie | tw ‘gam a qoatotoma | 08 Frets oa ios) Rene Seem ra Sara ry Frese ona soe | Re 2pm oa Ws Peden eee sie | Rowe Sepp a) ion We Peco eoe sox | see 25 20m is sera a =) Uaae “ap ‘oukia tank | —t0T5—) —]—Low ye | Gow 2g Souter | tone) | town ise | Uo ‘Soe in) Sovaterama | 1009) | Gena Pupose Es | tee {tam rs) tonawiem | 12(0m) | Soma Post ce | Utiom Shaper ‘on no tata ort opm og Ter Saiy= = TC) oom a an itv rt soe | tsa ‘om ra) Scomworom | $8 Ua tow oon 1B ae ‘oor (rae Tom or Taw Orie Ee Say Zom__|_ wioewe? 2eyen ea to o2 tau gh Palomar cr 202%] _iae0 ‘on ma) Tank wi Prion sn Som | Lhamecto Spm ra time 0% Yerba Soom | troneoo oom ay os “ey Te a Toanes zoe | Ureooa0 2oopm ae Vea os lo Con Hn eae pose | trois Soom rary as ‘er tow ot Som | times pam ra) Vink O25 Yer na orc som | Gros 2sypm as ita bas {or ato Perma som | tre Sopp a {na we ‘ee aw or com | uel ‘pon tne) oma nn Sema Dot some |e 35pm a Moa tn Parton no, sr ‘soem Moa tn Prison oon sis | aero fsoom a ana me Prin tre ae ee ee eee AN42-4 LT WEARApplication Note 42 avert Figure 1. Basie Operation of Shunt Reterence Family -voesnor cr ‘eire ctetcen ating Fue oe Tare Si ss Pre sree ya D “irene sea Figure 6. 5V Output Reterence, Figure 7. 2.6V Output, Temperature Narrow Trim Range Independent Trim Figure 4. 2.5V Output Reference, Reg, on 10k 682K Web FOquA 6.20 88.20 E20 Figure 2. Current Source Stabilized Reference Figure 5. 5V Output Reference, 45%, 134% Tim Range LES cone Figure 8. 2.490V Output, Trim for thinimum TC AT WNEAR AN42-5Application Note 42 Figure 9. 5.120V Output, Figure 10. 2.5V Reference Figure 11. 2.5V Reference ‘TWimmed Reference —" sons (48) er oe one ao Re i ows oo ows owt aos __ avo Tt TT am srg fis 2 moots TOLERANCE L sSbom a Figure 12, SV Reterence Figure 13. Increasing SV Reference Figure 14. Programmable ‘Adjustable Curret Limit Figure 16. Precision Multiply by Two Figure 17. Utra-Precision Voltage Inverter AN42-6 LT WeApplication Note 42 Figure 18. Basic Hookup for {T1019 Series Relerence no Mure most Vout Figure 19. Basic Hookup for Figure 20. Basic Hookup for T1021 Series Reference 11027 Series Reference Lon recent SS LAPT ONS) Figure 22. 10V Output, Full Trim Range (10.7%) Figure 23. 10V Outpt, Restricted Trim Range for Improved Resolution eS PERFORMANCE a Lrrost¢ Lr19310 71021 PERFORMANCE vewce Uriaies Lrioat8s Lri02187 Lrve2i0-7 Lrte2i¢-10 Lr10218-10 rote Pen Lrio9a25 L092 L101945 L015 Lri0198-10 Device TEIN gmc Your (TVPIMAK) ov ssn 35 tov #10m7 a5 10V 220niv 1026 Tein pone Vo | vem) BVe2 Sa 920 5V 50m 28 TV50nWv 25 7vas0mv 30 tv 25m 520 | swvsso0v % MANGE — Tem pare (TVPIMAN);C = COM, M. 315 (C), 510 (M) 25V 5m 5720(0), 825 (M) | sv326mv 95 (0), 510M) | svstomy 5:20 (0), 825 (Mm) Lrv0110_| 10v 2200 (71027 PERFORMANCE pewce Your Or0ar | vsinv 110278 Sye25m taz7e Sy225nV Ura [sv 2m Lrio27e 525m 5120 (0). 825 ( crvemax) 35 (0), 510), TEIN amc 2 12 23 48 V—— STN AN42-7Application Note 42 Figure 24. 10V Output, Trimmed Figure 27. 10V Output, Figure 28. SV Output, ‘rimmed Yo 10.24V ‘rimmed io 5.1200 rorroasy +e REDUCTION CAP AND TRA POTENTONETER TONAL Figure 26, Narrow Trim Range (0.2%) Figure 29, 10V Output, ‘Trimmed to 10.2400 Figure 30. 6V Output, Fast Setting, Trimmed Reference AN42-8 LST WEARApplication Note 42 J me Figure 31. Low Noise Statistical Voltage Standard - hy oh Figure 32. Shunt Mode Operation of a Figure 23.-5v Output Reterence Figure 34 -10¥ Output ora Series Devin (1024-1. 10) (utes) Series Devie sn 7 [+ i Figure 35. 10V Output, Wide Figure 36. Shunt Operation of a Series Figure 37. Current Boost Negative Input Range Device (LT1019-2.5, 5, -10) Relerence (LT1019-2.5, 5, -10) AT WN AN42-9Application Note 42 a ere BYR) te Men Figure 40. -5V Output Reference ‘Figure 41. +2.5V Output Reference 00 iw ASHE Sy Figure 42. 210V Output Reference > Figure 43, +1.25V Output, Logic Figure 44. 1.2V Outpu, Micropower Figure 45. 1.2V Output, Micropower Programmable Reference Reference from 1.5V Battery Reterence trom V Battery AN42-10 AT WEARApplication Note 42 Lo swvevecaw Figure 46 1.2V Output, Micropower Figure 47.2.5V Output, Figure 4. 2.5V Output, Micrpower Releence with Wide Input Voltage Range MicropowerReterence Roference wih Wide Input Vottage Range v en #. Ky Kies Figure 49. 2.5V Output with Wide Input Range Figure 5. +1.2V,47V Outpt, Pre-Repulate Reference Sara gf SE Boon moore ce +2.45V Output, Sel-Buferee, Figure 82. 1.24V Ougu, Micropower, Current Boosted ce Reference (100mA) AN42-11Application Note 42 im Seam = ; Figure $3. 10V Output with Viy-Vour Figure $4. 1 Output with External PNP Figure $5. 10V Boosted Output with ‘Shunt Resistor for Greater Current for Boosted Output (100mA) Current Limit (100m) Device 2 a iris — uta iTio19s. Leas ae 4 1m BY Zam: te — -pesir0Rs Taw 8 iro 10 Tov oma MBER CURIENT z= trioat-t0 Figure 86. Series Reference with PNP Boost Figure 67. Precision High Current Reference (1.54) AN42-12 LT WeeApplication Note 42 rc we Me oka soo Figure $8. Butlered Standard Ce = wt bey F fe =~ on 1 + Flies “ue San en Figure 59, Standard Grade Variable Voltage Relerence =| x {pass arms myo Moo yr cag “8 esha eno Figure 60.SV Output, Curent Boosted Negative Reference with Overiad Protection AT WER AN42-13Application Note 42 Figure 61. 10V Output, Low Noise Reference 1 Figure 62.—10V Output, Low Noise Reteren eo Figure 63, Single Supply, ~10V Qutput, Trimmed Low Noise, Low TC Reference AN42-14 LT WEARApplication Note 42 * wer suc AMAL Figure 64. 2.5V Output, Low Noise Reterence Figure 65. 7V Output, Low Noise, Low Drit Reference Figure 66. 10V Output, Temperature Stabilized Reterence AT WEAR AN42-15Application Note 42 paves coupes, TE F020 ‘za he REE VEE ay CHEE a a Oem aT A 2 CONTR LES THAN 29 OF OUIPUT ET OGRA Si Re Figure 67. Low Noise, Ultra Low Dit, Long Term Stable 7V Positive Reference or a D2 OMTRAVTE ESS THN 24 OF OIPU ORT VER ASO RENCE Figure 68. Low Noise, Ultra Low Dri, Long Term Stable Negative Voltage Reference AN42-16 AT EARApplication Note 42 (65am oureut ca Figure 69. Buttered Standard Cell Replacement Figure 70, 10V Output, Set-Biasod Temperature Stabilized Reference AT Wee AN42-17Application Note 42 Figure 71. Unra-Precision Variable Voltage Reference Figure 72. 10 Outpul, Temperature Stabilized Relerence Figure 73. Temperature Stabilized 10V Buttered Reterence AN42-18 LT WEARApplication Note 42 78k de i "I od oss 1S cow sory a 5 ex Seg so 5 we | 7 | Fawe 74.6 25 duu, Tpersture Fue 75.6451 Ou, Temperate Figur 76 6.86 Ott, Temperate Size Retrone Stine Reon Stbize Reon Figure 78. High Stability Negative Regulator LT WEAR AN42-19Application Note 42 oat ‘hn e413, ace | rears — di Le torent UTH086 —| TA Low Oresot T a = iiss [ae Toad Figure 79, Regulator with Rel Sg ca Var =-7¥ 898 Laon = ak Figure 80, Negative Output Regulator with Reference AN42-20 LT eneApplication Note 42 ao Teer Tes is aad crs Loot | tas | tz | aaa uate —p— vor ri aso | 2s | a7 ay fa cotscrow | tzeses | ars | as T ures s s | 60 = crv034 CTO 625 625. =) 747 uriontutioaa | 625 | gas | ras waze 69 co | ais rom sros | asso | ram | arn scien canoes rion since | taeseeo | bres | gare ee, = roots inses | t25v69 | 818 | 9385 74 EFFECTIVE REFERENCE VOLTAGE ri00a «329 25469 9400 10880 a owen xO ses | tomo | traso trices unas | se69 | sts00 | taas0 Pate coves | t3am0 | ts0s0 Figure 61. Simple Stacked Reference/Regulator rs t T again 16008, Drift 005,VFC- | ‘Requires Floating Supply. No 025iV°6, Gain Accuaey0000% | Direct atiometr Output. Possible, Gan Dit gpmi*C win | Floating Supply Orisa Gain Appropriate Resistors Ps Floating Term. Require Feedback ‘Supply Ero, Simp Gain Tim, Resistors to Set Gan, Ou Ta, Dit ODEO 025,VC, Gain AccuracyO001% | Zener SuplyisaGainandOtset Possible, Gani ipmiPCWth | Tem Ener Generator Requires AzpropiateesisorsPusFcating | Feedback Resistorsto Set Gan Suppy Err, Spe Gain im Noise nse Posi. No Direct Ratiometic Output Low impedence Bapes Require Substanta Curent rom Shun Feguatr ot Great Which Simulates. Usualy Poo: Chace INPreciion Raquted Figure 4, Some Signal Conditioning Methods for Bridges AT NEAR AN43-3Application Note 43 "CONFIGURATION 1025:0°6, Gai Accracy0001% Possible, Gain it ppmC with ‘Approsiat Resistors, Simple Gain Tin, Rationetc Output, Noise ‘sara Possbe t ‘Requires Precision Analog Lev |_ setts ih toton noir aquresFotoeck | | sors ‘OMAR 2068-14068, Dai 05,¥°C-025,00, Gain ‘Accuracy 007% Pssibi, ala Dai ppmiec with Appropriate equves Tecking Supplies Assumes high Dages of Bridge Syma dchiee Best CHAR. | | Rous Forte ests (025), GeinAccuraty 001% Possible, Gain Dit ppm, Si? | Simple Gain Tin, Diet Ratio | etre Output, Noise 1oVs Hz * Possible, Fess, SimpleGain Trin, Direct | SetGain Fatometric Outpt Noise ovHE Possible = ‘OMAR 16048, Drift .05,W°C- “Practical Real ] “woAnpifiers Pus Vaiaus Dcrete Components Negative Suppl Nesestry | Figure 4. Some Signal Conditioning Methods for Bridges (Continued) work. The amplifiers in this example, CMOS chopper sta- bilzed units, essentially eliminate offset dri with time and temperature. Trade offs compared to an instrumentation amplifier approach include complexity and the require- ment for a negative supply. Figure 7 is similar, except that low noise bipolar amplifiers are used. This cicutt trades slightly higher DC offset dit for lower noise and is a good candidate for stable resolution of small, slowly varying measurands. Figure 8 employs chopper stablized AT 10 reduce Figure 7's already small ofset errr. At measures the DC error ai A2's inputs and biases A's offset pins to force offset fo a few microvots. The offset pin biasing at ‘2s arranged so At will always be able to find the servo point. The 0.01,F capacitor rolls off At at low frequency, with A2 handling high frequency signals. Returning A2’s feedback string to the bridges midpoint eliminates Ad's offset contribution If this was not done Aé would require a similar offset correction loop. Although complex, this ap- proach achieves less than 0.054V/°C drift, 1nVVHz noise and CMRR exceeding 16048, AN43-4 LT NABApplication Note 43 esse panaouceR SRR Figure. A Practical Instrumentation Amplifier Based Bridge Circuit sever Figure 6. Servo Controlling Bridge Drive Eliminates Common Mode Voltage ‘Single Supply Common Mode Suppression Circuits ‘The common mode suppression circuits shown require a ‘negative power supply. Often, such circuits must function in systems where only a positive railis available, Figure 9 shows a way to do this. A2 biases the LTC1044 postive- to-negative converter. The LTC1044’s output pulls the bridge's output negative, causing A1's input to balance at OV. This local loop permits a single-ended amplifier (A2) {to extract the bridge's output signal. The 100k-0.33uF RC filters noise and A2's gain is set to provide the desired ‘output scale factor. Because bridge drive is derived from the LT1034 reference, A's output isnot affected by sup- ply shits. The LT1034's output is available for ratio opera- tion. Athough this cicuit works nicely from a single SV rail the transducer sees only 2.4V of drive. This reduced AT WEAR AN43-5Application Note 43 Figure 8. Low Noise, Chopper Stabilized Bridge Amplifier with Common Mode Suppression AN43-6 LT WNApplication Note 43 Figure 10. High Resolution Version of Figure 9. Bipolar Voltage Converter Gives Greater Bridge Driv, Increasing Output Signal. drive results in lower transducer outputs for a given mea- surand valve, effectively magritying ampli ofset crit terms. The limit on available bridge drive is set by the CMOS LTC1044's output impedance, Figure 10's circuit employs @ bipolar positive-to-negative converter which has much lower output impedance. The biasing used per- mits 8V to appear actoss the bridge, requiring the 100mA Capabiity LT1054 to sink about 24mA. This increased drive results in a more favorable transducer gain slope, increasing signal-to-noise rato, ee — AT WB AN43-7Application Note 43 ‘Switched Capacitor Based Instrumentation Amplifiers ‘Switched capacitor methods are another way to signal condition bridge outputs. Figure 11 uses a tying capacitor, configuration in a very high precision scale application. This design, intended for weighing human subjects, will resolve 0.01 pound at 300.00 pounds full scale. The sirain gauge based transducer platform is excited at 10V by the LT1021 reference, At and A2, The LTC1043 ‘switched capacitor bulding block combines with A3, form- ing a differential input chopper stabilzed amplifier. The LTC1043 alternately connects the 1F fying capacitor be- tween the strain gauge bridge output and A3's input. A second uF unit stores the LTC1043 output, maintaining AA3's input at DC. The LTC1043's low charge injection maintains differential to single ended transfer accuracy of ‘about 1ppm at DC and low frequency. The commutation rate, set by the 0.0144F capacitor, is about 400H2. A3 takes scaled gain, providing 8.0000V for 300.00 pounds tull scale output. cH The extremely high resolution ofthis scale requires fter ing to produce useful results. Very sight body movement acting on the platform can cause significant noise in A3's ‘output. Ths is dramatically apparent in Figure 12s trac- ings. The total force on the platform is equal to gravity puling on the body (the "weight plus any additional ac- celerations within or acting upon the body. Figure 12 (trace 8) clearly shows that each time the heart pumps, the acceleration due to the blood (mass) moving in the ar- teries shows up as “weight.” To prove this, the subject gets ofthe scale and runs in place for 15 seconds, When the subject returns tothe platform the heart should work harder, Trace A confirms this nicely. The exercise causes the heart to work harder, forcing a greater acceleration: per-stroke ot 2 Carly acne wil eognae is a5 ater Bastocactgaph| (tom te Giekcnalen’—to row hr et nd tara". A sgfeart was expended ater olay characte hea cartons Vis acderaon decion rads Thee ef wee wraucessil when ompres apret tela ! EKG posed cla. Soo referees deauson Figure 11. High Precision Scale for Human Subjects AN43-8 AT WERApplication Note 43 A naspRUL see i i a ossar se Figure 12. High Precision Scale’s Heartbeat Output. Trace B Shows Subject at Rest; Trace A After Exercise. Discontinuous Components in Waveforms Leading Edges Are Due to XY Recorder Slew Limitations, ‘Another source of noise is due to body motion, As the body moves around, its mass doesn't change but the in- ‘stantaneous accelerations are picked up by the platform and read as “weight” shits. All this seems to make a 0.01 pound measurement meaningless. However, fering the noise out gives a time averaged value. A simple RC low pass wil work, but requires excessively long setting times to fiter noise fur ddamentals in the 1H2 region. Another approach is needed. ‘Ad, AS and associated components form a filler which ‘witches it's time constant from short to long when the output has nearly arrived at the final value. With no weight onthe platform A3's output is zero. Ad's output is also zero, ASB's outoutis indeterminate and ABA's output is low, The MOSFET optocouplers LED comes on, puting the REC fier into short time constant mode, When some- cone gets on the scale A3's output rises rapidly. ASA goes high, but ASB trips low, maintaining the RC filter in its short time constant mode. The 2uF capacitor charges rapidly, and AA quicky settles to final value + body motion and heartoeat noise, ASB's negative input sees 1% atten- uation from A3; i's positive input does nol. This causes ‘ASB to switch high when Ad's output artves within 1% of final value. The optocoupler goes off and the filter ‘witches into long time constant made, eliminating noise in Ad's output. The 39k resistor prevents overshoot, en- suring monotonic AA outputs. When the subject steps off the scale A3 quickly retumns to zero, ASA goes immedi ately low, turning on the optocoupler. This quickly dis- charges the 2uF capacitor, returning AA's output rapidly to zero, The bias string at ASAS input maintain the scale in {ast ime constant mode for weights below 0.50 pounds. This permits rapid response when small objects (or per sons) are placed on the platform. To trim ths circuit adjust the zero potentiometer for OV out with no weight on the platform, Next, set the gain adjustment for 3.0000V out for a 300.00 pound platform weight. Repeat this proce: dure until both points are fixed Optically Coupled Switched Capacitor Instrumentation Amplifier Figure 13 also uses optical techniques for performance enhancement. This switched capacitor based instumen- tation amplifier is applicable to transducer signal condi- tioning where high common made voltages exist. The Circuit has the low ofset and drt ofthe LTC1150 but also incorporates a novel switched-capacitor “front end” to achieve some specications not available in a conven tional instrumentation ampli. Common made rejection ratio at DC for the front end ex- ceeds 16008. The amplifier will operate over a +200V ‘common mode range and gain accuracy and stabilty are limited only by extemal resistors. At, a chopper stabilzed Unit, sets offset drift at 0,05yW/°C. The high common ‘mode voltage capabilty of the design allows it to with- stand transient and fault conditions often encountered in industrial environments -——_- eer ATR AN43-9Application Note 43 <4 * ipl . et c TS L, T 1 De ont a Figute 13. Floating Input Bridge Instumentation Amplifier with 200V Common Mode Range The circuit's inputs are fed to LED-crven optically-cou- pled MOSFET switches, St and S2. Two simiar switches, §3 and $4, are in series with S1 and $2. CMOS logic functions, clocked from As internal oscillator, generate rnor-overtapping clock outputs which drive the switch’s, LEDs. When the "acquire pulse is high, St and S2 are ‘on and C2 acquires the diferental votage atthe bridge's cutput. During this interval, $3 and $4 are off. When the aoquite pulse falls, $1 and $2 begin to go of. After a de lay to allow S1 and S2to fully open, the “read pulse” goes, high, turning on $3 and S4, Now C1 appears as a ‘ground-refered voltage source which is read by AT. C2 allows At's input to retain C's value when the citcuit tums to the acquire mode. At provides the circuits out- put Its gain is set in normal fashion by feedback resistors. The 0.33uF feedback capacitor sets rollof. The diferen- tiakto-single-ended transition performed by the switches ‘and capacitors means that At never sees the inputs common made signal. The breakdown specication of the optically-driven MOSFET switch allows the circuit to with- stand and operate at common mode levels of +200V. In addition, the optical dive to the MOSFETS eliminates the charge injection problems common to FET switched ca- pacctive networks, Platinum RTD Resistance Bridge Circuits Platinum RTDs are frequently used in bridge configura- tions for temperature measurement. Figure 14's circuit is highly accurate and features a ground referred RTD. The ground connection is highly desirable for noise rejection. The bridges RTD legis driven by a current source while the opposing bridge branch is voltage biased. The current tive allows the voltage across the RTD to vary directly with its temperature induced resistance shit. The difer- tence between this potential and that of the opposing bridge leg forms the bridges output sess AN43-10 AT WEARApplication Note 43 Figure 14, Linearized Platinum RTD Bridge. Feedback to Bridge from AS Linearizes the Circ. ‘1A and instrumentation amplifier A2 form a voltage con troled current source, AYA, biased by the T1009 refer ence, drives current through the 88.702 resistor and the RTD. A2, sensing diferentialy across the 88.702 resistor, closes a loop back fo ATA. The 2k-0.1,uF combination sets amplifier rolloff, and the configuration is stable. Because A1As loop forces a fixed voltage across the 88.70 resistor, the current through Rp is constant. At's, ‘operating point i primarily fixed by the 2.5V LT1009 volt: age reference The RTDs constant curent forces the voltage across it to vary with its resistance, which has a nearly linear positive temperature coefficient. The non-ineariy could cause several degrees of error over the circuit's 0°C-400°C op- erating range. The bridges output is fed to instrumenta- tion amplifier A3, which provides citferental gain while simultaneously Supplying non-linearity correction. The correction is implemented by feeding a portion of A3's output back fo A's input via the 10k-250k divider. This causes the current supplied to Rp to slighty shit with its ‘operating point, compensating sensor non-linearily to within £0.05°C. AB, providing additional scaled gain, fur- rishes the circuit output, To calibrate tis circuit, substtute a precision decade box (e.g. General Radio 1432k) for Rp. Set the box to the °C value (100.0002) and adjust the ose trim for a 0.00V output, Next, set the decade box for a 140°C output (154.2602) and adjust the gain tim for a 3.500V output reading, Finally, set the box to 249.00 (400.00°C) and trim the linearity adjustment fora 10.000V output. Repeat this sequence unt al three points are fixed. Total error over the entire range will be within 40.05°C. The resis: tance values given are for a nominal 100.0082 (0°C) sen- sor, Sensors deviating from this nominal value can be sed by factoring inthe deviation from 100.000. This de- Viation, which is manufacturer specified for each individ ual sensor, is an offset term due to winding tolerances during fabrication of the RTD. The gain slope ofthe plat inum is primarily fixed by the purty of the material and has a very small error term, -eeoeooo AT NB AN43-11Application Note 43 i ec Figure 15 is functionally identical to Figure 14, except that A2 and A3 are replaced with an LTC1043 switched ca pacitor building block. The LTC1043 performs the differ. ential-to-single ended transitions in the current source and bridge output ampli. Value shifts in the current source and output stage reflect the LTC1043's lack of gain. The primary trade-off between the two circults is, Component count versus cost Digitally Corrected Platinum Resistance Bridge ‘The previous examples rely on analog techniques to achieve a precise, linear output from the platinum RTD bridge, Figure 16 uses cigital corrections to obtain similar results, A processor is used to correct residual RTD non- linearities. The bridges inherent non-linear output is also accommodated by the processor. The LT1027 drives the bridge with 5V. The bridge ditfer ential output is extracted by instrumentation ampifier A, A's output, via gain scaling stage A2, is fed to the LTC1290 12bit A-D. The LTC1290's raw output codes re- flect the bridges non-linear output vs temperature, The processor corrects the A-D output and presents lin earized, calrated data oul. RTD and resistor tolerances mandate zero and ful scale trims, but no linearity correc tion is necessary. A2's analog outputs avaliable for feed- back control applications. The complete software code for the 68HC0S processor, developed by Guy M. Hoover, ap- pears in Figure 17 een FRO Figure 15. Switched Capacitor Based Version of Figure 14 AN43-12 LT EARApplication Note 43 Thermistor Bridge Figure 18, another temperature measuring bridge, uses a thermistor as a sensor. The LT1034 furnishes bridge exci- lation. The 3.2k and 625002 resistors are supplied with the thermistor sensor, The networks overall response is linearly related to the thermistor’s sensed temperature. The network forms one leg of a bridge with resistors fur- nishing the opposing leg. A trim inthis opposing leg sets bridge output to zero at O°C. Instrumentation amplifier At takes gain with A2 providing additional trimmed gain to {urmish a caibrated output. Calibration is accomplished in similar fashion to the platinum ATO circuits, withthe tn early trim deleted Low Power Bridge Circuits Low power operation of bridge circuits is becoming in- creasingly common. Many bridge based transducers are low impedance devices, complicating low power design The most obvious way to minimize bridge power con- tT CREAN RESETOR sumption isto restrict drive to the bridge. Figure 19A is identical to Figure 5, except thatthe bridge excitation has been reduced to 1.2V. This cuts bridge current from nearly 3OmA to about 3.5mA. The remaining circuit ele- ments consume negligible power compared to this amount, The trade-of isthe sacrifice in bridge output sig- nal, The reduced dfive causes commensurately lowered bridge outputs, making the noise and dri floor a greater percentage ofthe signal. More specttcally, a 0.01% read- ing of a 10V powered 3502 strain gauge bridge requires AV of stable resolution. At 1.2V drive, this number shrinks 1 a scary 360nV, Figure 198 is similar, although bridge current is reduced below 700,14. This is accomplished by using a semicon dluctor based bridge transduoer. These devices have signi icantly higher input resistance, minimizing power cissioation. Semiconductor based pressure transducers have major cost advantages over bonded strain gauge types, although accuracy and stability are reduced. Appendix A, “Strain Gauge Bridges,” dscusses trade-ofs and theory of both technologies. eno pmcesson Figure 16. Digitally Linearized Platinum RTD Signal Conditioner AT NEB AN43-13Application Note 43 PLATIMUM RTO LINEARIZATION PROGRAM (0.0 To 400.0 DEGREES €> 3/14/90 Fo 60,296,527, 753,976, 1195, 1410, 1421, 1829, 2032 Foe 2255, 2630,2625,2815,3000,3186,3365,3563,3718 3890 ore 1030 Foe 3486,3935, 3585, 3685,3735, Fou 41534232 ,4202, 4382, 6432, 4531, 4581, 6681 4 Foe 0,200,400,600,808, 1000, 1200, 1600, 1600, 1800 Fos 2600,2200,2400,2600,2800,3000,5200,3400,3400,3800 one 3108 ore 0100 {Ok #827 CONFIGURATION DATA FoR PoRT ¢ 00R Use READGO CALL READ9O SUBROUTINE (HSE I¥ S61 L5BS TH 862) Sra $55 STORE Lees IN $55 \ STA 4540 STORE Meus TH 834 rane ase susrect : Figure 17. Software Code for HC0S Processor Based ATD Linearization K 18 FORKED ey SUBTRACTING PROPER SEGHENT EHO POINT FRON A/D OUTPUT ee AN43-14 LT HERApplication Note 43 sr $50 store mses IW $54 / TERPERATURE Im DEGREES C* 1018 IN 861 AND 862 LDA #850 CONFIGURATION DATA FoR SPCR \ toa $50 LoKo orm wor 1470 THE ACC / STA. 800 Loup 01m tuto sot pata nec. stant reANSreR. | rst $08 test starr of srr 1 SPL sacKyo Lor to pRevigus InstaucrioN tf wor DONE | ton toe (oxo contents oF sei oATA REG. GHT9 Aco | STA a0 StART NEXT CYCLE i STA $6) STORE HSBS 14 861 Laren ist soa Test status oF spur | bara SFL sacK#2 Loop To PREvioUS InsraucTrON If NOT DONE | Bsr 0,302 set sir o Font ¢ ces cors wrot> 1 toa soe Lomo contents oF sP1 oATA aEG iwTO Ace i ete cueaR carer \ Figure 17. Software Code for 68HCOS Processor Based RTD Linearization Continued) AN43-15Application Note 43 + susract suBrAACTS #5¢ AND 455 FROM $61 AND $62, RESULTS 16 E61 AND 62 Aves Loa $42 sono ises: Sta $62 store sum S16 HSGS OF RESULT ARE PLACED IW $61 AND B62 cin $69 CLEAR CONTENTS OF $49 \ RESET TeNPoRARY con 368 CLEAR COMTENTS OF $60 Figure 17. Sotware Code for 8HC0S Processor Based ATD Linearization (Continued) TTTCTC_E~—_—_—ee=—'—'— AN43-16 LT WE369 Application Note 43 MULTIPLY CONTENTS OF 855 BY CONTENTS OF S61 MULTIPLY CONTENTS OF 856 AY conteNTS oF 861 LT NEAR Figure 17. Software Code for 8HC05 Processor! 18. Linear Outpt Thermistor Bridge. Thermistor Network Provides Linear Bridge Output AN43-17Application Note 43 OPURESEOR ron ® Figure 18. Power Reduction by Reducing Bridge Drive. Circuits A Low Power Version of Figure. AN43-18 LT WERApplication Note 43 ———— Strobed Power Bridge Drive Figure 20, derived directly from Figure 10, isa simple way to reduce power without sacrificing bridge signal output level. The technique is applicable where continuous out- putis not a requirement. This circuit is designed to st in the quiescent state for long periods with relatively brie onetimes. Atypical application would be remote weight in- formation in storage tanks where weekly readings are sut- ficient. Quiescent current is about 150.8 with on-state current typically 50mA. Bridge power is conserved by sim: ply turing it of With Q1’s base unbiased, all circuitry is off except the 71084 plusto-minus voltage converter, which draws a 4150j:A quiescent current. When Qi's base is pulled low, its collector supplies power to At and A2. A1's output goes high, tuning on the LT1054, The LT1054's output (pin 5) heads toward -5V and Q2 comes on, permiting bridge current to flow, To balance its inputs, At servo con- trols the LT1054 to force the bridge's midpoint to OV. The bridge ends up with about 8V across it, requiring the 100mA capability LT1054 to sink about 24mA, The 0.02uF capacitor stabilizes the loop. The A1-LT1054 loops negative output sets the bridge's common mode voltage to zero, allowing A2 to take a simple single ended measurement. The “output trim” scales the circuit for 3mV/V type strain bridge transducers, and the 100k- 0.1, combination provides noise filtering ‘Sampled Output Bridge Signal Conditioner Figure 21, an obvious extension of Figure 20, automates the strobing into a clocked sequence. Circuit on-time is restricted to 250,18, at a clock rate of about 2Hz. This keeps average power consumption down to about 200... Oscillator ATA produces a 250us clack pulse every ‘500ms (race A, Figure 22). A fitered version ofthis pulse is fed to Q1, whose emiter (trace B) provides slew limited bridge chive. ATA's output also triggers a delayed pulse produced by the 746221 one-shot output (trace C). The timing is arranged so the pulse occurs wel alter the A1B- -A2 bridge ampiier output (trace D) seties. A monitoring AD converter, tiggered by this pulse, can acquire A1B'S output The slew limited bridge drive prevents the strain gauge bridge from seeing a fast rise pulse, which could cause long term transducer degradation, To calibrate this circuit trim zero and gain for appropiate outputs. Figure 20, Strobed Power Strain Gauge Bridge Signal Conditioner AT WER AN43-19Application Note 43 “yw rumaessron Figure2. Sampled Output Bridge Sigal Conditioner Uses Pulsed Excitation to Save Power Figure 22, Figue 21's Waveforms. Trace C's Delayed Pulse Ensures A~-D Converter Sees Setted Output Wavelorm Trace D. AN43-20 LT WEARApplication Note 43 Continuous Output Sampled Bridge Signal Conditioner Figure 23 extends the sampling approach to include a Continuous output. This is accomplished by adding a ssample-hold stage atthe circuit output. inthis circuit, 2 is off when the “sample command! is low. Under these conditions only A2 and St receive power, and current drain is inside 608. When the sample command is pulsed high, 02's collector (race A, Figure 24) goes high, f—1 providing power to all other circuit elements. The 10:2- ‘uF RC at the LT1021 prevents the strain bridge from seeing a fast rise pulse, which could cause long term transducer degradation. The LT1021-5 reference output (trace B)crives the strain bridge, and instrumentation am- plier A1 output responds (trace C). Simultaneously, S's ‘witch control input (race D) ramps toward Q2’s collector. Figure 4. Waveforms for Figure 24's Sampled Strain Gauge Signal Conditioner AT HEAR AN43-21Application Note 43 ee ‘At about one-half Q2s collector voltage {in this case just before mid-screen) $1 turns on, and AT'S output is stored in C1. When the sample command drops low, Q2's collec: tor falls, the bridge and its associated circuitry shut down and S1 goes of. C1's stored value appears at gain scaled AZ output. The RC delay at S1's control input ensures glitch free operation by preventing C1 from updating unt ‘At has settled. During the ims sampling phase, supoly current approaches 20mA but a 10Hz sampling rate cuts effective drain below 250uA. Slower sampling rates wil further reduce drain, but C1’s droop rate (about ‘mv/100ms) sets an accuracy constraint. The 10H2 rate provides adequate bandwidth for most transducers. For 3mV/V slope factor transducers the gain tim shown al: tows calibration. it should be rescaled for other types. This circuits effective current drain is about250uA, and ‘2's output is accurate enough for 12-bit systems. Its important to remember that ths circuit is a sampled system, Although the output is continuous, information is being collected at a 10H2 rate. As such, the Nyquist mit applies, and must be kept in mind when interpreting resulls High Resolution Continuous Output Sampled Bridge Signal Conditioner Figure 25 is a special case of sampled bridge drive. It is intended for applications requiring extremely high resolu- tion outputs from a bridge transducer. This circuit puts 1O0V across a 10V, 36002 strain gauge bridge for short petiods of time. The high pulsed voltage ckive increases bridge output proportionally, without forcing excessive dis sioation. In fact, although this circuit is not intended for power reduction, average bridge power is far below the ‘normal 29mA obtained with 10Vigg excitation Combining the 10x higher bridge gain (200mV ful scale vs the normal 30m) with a chopper stablized amplifier in the sample-hold output stage isthe key to the high reso- lution obtainable with tis circuit When oscillator A1A’s output is high QB is turned on and AA2's negative input is pulled above ground. A2's output goes negative, turning on Q1. Qt's collector goes low, robbing Q3's base drive and cutting i of. Simultaneously, ‘3 enforces i's loop by biasing Q2 into conduction, softy tuming on Q4. Under these conditions the voltage across the bridge is essentially zero. When AA oscilates low {trace A, Figure 26) RC fiter driven Q6 responds by cut- ting off slowy. Now, A2’s negative input sees curent only through the 3.6K resistor. The input begins to head nega tive, causing A2's output to rise. Qt comes out of satura: tion, and Q3's emitter (rave B) rises. Italy this action is rapid (fast rise slewing is just visible at the start of 3's, ascent), but feedoack to A2’s negative input closes @ con- ‘tol loop, with the 1000pF capacitor restritng rise time. “The 72k resistor sets AZ's gain at 20 with respect to the T1004 25V reference, and Q3's emitter servo controls to 50V. Simultaneously, A3 responds to the bridges biasing by ‘moving is output negatively. 2 tends towards cut-of,in- creasing Q4's conduction. A3 biases i's loop to maintain the bridge mid-point at zero. To do ths, it must produce a complimentary output to A2’s loop, which trace C shows to be the case. Note that A3's loop roll is considerably faster than A2'sensuring that it will faithfully track A2's ‘oop action. Simiatly, AB's lop is slaved to A2's loop out: put, and produces no other outputs. Under these conditions the bridge sees 100V drive across itfor the ims duration ofthe clock pulse, A1AS clock output also triggers the 74221 one-shot. The one-shot delivers a delayed pulse (trace ) to 05. 05 ‘comes on, charging the 1,zF capactor to the bridges out put voltage. With A3 forcing the bridges ie side mid-point to zero, OS, the iF capacitor and Ad see a single-ended, low voltage signal. High transient common mode voltages are avoided by the control loops complimentary controlled rise times. A4 takes gain and provides the circuit output The 74C22t's pulse width ends during the bridges on: time, preserving sampled data integity. When the ATA os- cilator goes high the control loops remove bridge drive, returning the circuit to quiescence. AA's output is main- tained at DC by the 1, capacitor. A1A's 1Hz clock rate is adequate to prevent deleterious droop of the 114F capaci tor, but slow enough to limit bridge power dissipation. The ——<—<—$—<$<_<— $$ AN43-22 AT HEApplication Note 43 He engineer ™ i IT T Figure25. High Resolution Pulsed Excitation Bridge Signal Coneitioner. Complementary SOV Drive Increases Bridge Output Signal. controlled rise and fall times across the bridge prevent possible long term transducer degradation by eliminating high AVIAT induced efects When using tis circuit iis important to remember that it is a sampled system. Although the output is continuous, information is being collected at a tHe rate. AS such, the Nyquist limit appies, and must be kept in mind when in- WORD terpreting results Figure 26. Figure 25's Wavetorms. Drive Shaping Results in Controlled, Complementary Bridge Drive Waveforms. Bridge Power ls Low Despite 100V Excitation. LT We AN43-23Application Note 43 —————— AC Driven Bridge/Synchronous Demodulator Figure 27, an extension of pulse excited bridges, uses synchronous demadulaton to obtain very high noise re- jection capabilty. An AC cartier excites the bridge and synchronizes the gain stage demodulator. In this applica- tio, the signal source isa thermistor bridge which detects extremely small temperature shifts in a biochemical mi- crocalorimetry reaction chamber. ‘The 500H2 care is applied at T1's input (trace A, Figure 28). T1’s floating output drives the thermistor bridge, hich presents a single-ended output to AT. A1 operates at an AC gain of 1000. A 60Hz broadband noise source is also deliberately injected into At’s input (race B). The cartier’ zero crossings are detected by C1. Ct’s output clocks the LTC1043 (trace C). A1's output (trace D) shows the desired 500H2 signal buried within the 60Hz noise source. The LTC1043's zero-cross-synchronized ‘switching at A2's postive input (race E) causes A2's gain to alternate between plus and minus one. As a result, “yl jection. ure 27. “Lock-In” Bridge Amplifier Synchronous Detection Achieves Extremely Natrow Band Gain Providing Very High Ne A's output is synchronously demodulated by A2. A2's ‘output (trace F) consists of demodulated carrier signal and non-coherent components. The desired carrier ampli tude and polarity information is discernible in A2’s output and is extracted by filter-averaging at A3. To trim this cir- cuit, adjust the phase potentiometer so that C1 switches when the carrier crosses through zero. Figure 28. Details of Lockin Amplifier Operation, Narrowband ‘Synchronous Detection Permits Extraction of Coherent Signals (Over 12048 Down. AN43-24 ATEApplication Note 43 — [AC Driven Bridge for Level Transduction Level transducers which measure angle from ideal level are employed in road construction, machine tools, inertial navigation systems and other applications requiring a gravity reference. One of the most elegantly simple level transducers is a small tube neary filed with a parially ‘conductive liquid. Figure 294 shows such a device, Ifthe tube is level with respect to gravity, the bubble resides in the tube's center and the electrode resistances to com ‘mon ate identical. As the tube shits away from level, the resistances increase and decrease proportionally. By con- troling the tube's shape at manufacture itis possiole to ‘obtain a linear output signal when the transducer is incor- porated in a bridge circu Figure 2A. Bubble Based Level Transducer Transducers of this type must be excited with an AC waveform to avoid damage to the partially conductive iq- uid inside the tube. Signal conditioning involves generat- ing this excitation as well as extracting angle information and polarity determination (e.g., which side of ‘evel the tube ison]. Figure 29B shows a cicuit which does this, directly producing a calibrated frequency output corre sponding to level. A sign bt, also supplied atthe output, gives polarity information. ‘The level transducer is configured with a pair of 2k02 re- sistors to form a bridge. The required AC bridge excitation is developed at C1A, which is configured as a muli-vibra- tor. C1A biases Q1, which switches the LT1009's 2.5V po- tential through the 100uF capacitor to provide the AC bridge drive, The bridge differential output AC signal is converted to a current by AT, operating as a Howland cur- rent pump. This current, whose polarity reverses as bridge drive polarity switches, is rectitied by the diode bridge. Thus, the 0.03uF capacitor receives unipolar charge. Instrumentation amplifier A2 measures the volt- age across the capacitor and presents its single-ended cutput to C1B. When the voltage across the 0.03uF ca pacitor becomes high enough, C1B's output goes high, turning on the LTC201A switch. This discharges the ca pacitor. When C1B's AC positive feedback ceases, C1B's ‘output goes low and the switch goes off. The 0.034F unit again receives constant current charging and the entire ‘cle repeats. The frequency of this oscillation is deter- mined by the magnitude of the constant current delivered to the braige-capacitor configuration. This current’s mag nitude is set by the transducer bridge's offset, which is level related, Figure 30 shows circuit waveforms. Trace A is the AC bridge drive, while trace B is At’s output. Observe that when the bridge drive changes polity, A1's output flips sign rapidly to maintain a constant current into the bridge- ‘capacitor configuration, A2's output (trace C)is a unipolar, ground-reterred ramp. Trace D is C18's output pulse and the circuit's output. The diodes at C1B's positive input provide temperature compensation forthe sensor's posi- tive tempco, allowing C18's trip voltage to ratiometrcaly track bridge output over temperature. ‘AS, operating open loop, determines polarity by compar. ing the recttied and fitered bridge output signals with respect to ground. To calibrate this circuit, place the level transducer at a known 40 arc-minute angle and adjust the 5K trimmer at 1B for a 400Hz output. Circuit accuracy is limited by the transducer to about 2.5%. AT WER AN43-25Application Note 43 Figure 208. Level Transducer Digit Uses AC Bridge Technique Time Domain Bridge Figure 31 is another AC based bridge, but works inthe time domain. Tis citcult is particularly applicable to ca~ pacitance measurement, Operation is straightforward. With St closed the comparators output is righ. When St opens, capacitor Cx charges. When Ca’s potential crosses the voltage established by the bridge's let side resistors, von zmsty the comparator ps low. The elapsed time between the switch opening and the comparator going low is propor tionate to Cx’s value. This circuit is insensitive to supply AN43-26 LT WEAR Figure 30. Level Transducer ridge Cireuits WevelomsApplication Note 43 Figure 31, Time Domain Bridge and repetion rate variations and can provide good accu: ragy it ime constants are kept much larger than compara tor and switch delays. For example, the LT1011's delay is, about 200ns and the LTC201A contributes 450ns. To en- sure 1% accuracy the bridges right side time constant should not drop below 65ys. Extremely iow values of ca actance may be influenced by switch charge injection. In ‘such cases switching should be implemented by alterna ing the bridge drive between ground and +5. Bridge Oscillator — Square Wave Output (Only an inattentive outlook could resis folding Figure 31's, bridge back upon itself to make an oscillator. Figure 32 does this, forming a bridge oscilator. This circuit wl also be recognized as the classic op amp mult-vibrator. In this version the 10k-20k bridge leg provides switching point hysteresis with Cx charged via the remaining 10k resistor. When Cx reaches the switching point the amplifies out- put changes state, abruptly reversing the sign of is posi- tive input voltage. Cx’s charging direction also reverses, Figure 2. “Bridge Osclator" (Good Old Op Amp Multivcaor wth AFancy Name) and oscillations continue. Al frequencies that are low compared to amplier delays output frequency is almost entirely dependent on the bridge components. Amplifier input errors tend to ratiometrically cancel, and supply shifts are similarly rejected. The duty cycle is influenced by output saturation and supply asymmetrys. Quartz Stabilized Bridge Oscillator Figure 33, generically similar to Figure 32, replaces one of the bridge arms wih a resonant element. With the crys tal removed the circuit is a familiar non-inverting gain of ‘wo with a grounded input. Inserting the crystal closes a positive feedback path atthe crystals resonant frequency. The amplifier output (race A, Figure 34) swings in an at temp! to maintain input balance. Excessive circuit gain prevents linear operation, and oscilations commence as the ampitier repeatedly overshoots in i's attempts to null the bridge. The crystal’ high Q is evident in the filtered ‘wavetorm (trace B) al the amplifiers positive input News. HORE Ae Figure 34. Bridge Based Crystal Oscllator's Waveforms, Excessive Gain Causes Output Saturation Limiting AT HER AN43-27Application Note 43 Sine Wave Output Quartz Stabilized Bridge Oscillator Figure 95 takes the previous circuit into the linear region to produce a sine wave output. It does this by continu ously controling the gain to maintain linear operation This arrangement uses a classic technique frst described by Meacham in 1938 (see References) In any oscilator it is necessary to control the gain as well as the phase shitt at the frequency of interest. If gain is too low, oscilation will not occur. Conversely, too much gain produces saturation limiting, as in Figure 33. Here, {gain control comes from the positive temperature coeti- Cient ofthe lamp. When power is applied, the lamp is at a low resistance value, gain is high and oscilation ampl- tude builds. As amplitude builds, the lamp current in- creases, heating occurs and its resistance goes up. This, ‘causes a reduction in ampifier gain andthe circuit finds a stable operating point. The 15pF capacitor suppresses spurious oscilation. Figure 7. Common Mode Suppression for Quartz Oscillator Lowers Distortion Operating wavetorms appear in Figure 36. The amplifiers output (trace A, Figure 36) is a sine wave, with about 1.5% distortion race B). The relatively high distortion content is almost entirely due to the common mode swing seen by the amplifier. Op amp common made rejection suffers at high frequency, producing output distortion. Figure 37 eliminates the common mode swing by using a second amplier to force the bridge's midpoint to virtual ground’ It does this by measuring the midpoint value, Comparing it to ground and controling the formerly grounded end of the bridge to maintain is inputs at zero. Because the bridge drive is complementary the oscilator amplifier now sees no common mode swing, dramatically reducing cistorion, Figure 38 shows less than 0.005% distortion (race B in the output (trace A) waveform. Hae 3: Sa ye ads wl cognas hs a 2 AG vee fe OC com or mode pression xine nodicdback nF 8 Figure 36. Lamp Based Amplitude Stabilization Produces Sine Wave Output Figure 8. Distortion Measurements for Figure 37. ‘Common Mode Suppression Permits 0.005% Distortion. AN43-28 LT WEARApplication Note 43 Wien Bridge Based Oscillators, Crystals are not the only resonant elements that can be stablzed in a gain contralled bridge. Figure 39 is a Wien bridge (see References) based oscillator. The configura tion shown was orginally developed for telephony app cations. The circuit is a modern adaptation of one described by a Stanford University student, Wiliam R. Hewiet in his 1939 masters thesis (see Appendix C. “The Wien Bridge and Mr. Hewlet’ The Wien network provides chase shit governed by the equation listed, and the lamp regulates amplitude in ac- cordance with Figure 36's description. Figure 40 is a vari able frequency version of the basic circuit. Output frequency range spans 20Hz to 20kHz in three decade ranges, wit 0.25dB amplitude flatness. Noi «tay er a awit rd anda Pada made arom borat Peep cel. They bul som er dsl nt Fo ven KB *b nae nye Figure 40, Mult-Range Wien Bridge Based Oscilator. Multiple Lamps Provide Lowered Distortion at Low Frequencies. ALT WEAR AN43-29Application Note 43 The smooth, limiting nature of the lamps operation, in combination with its simplicity, gives good results. Trace A, Figure 41, shows circuit output at 10kHz, Harmonic distor- tion, shown in trace B, is below 0.003%, The trace shows that most ofthe distortion is due fo second harmonic cor- tent and some crossover disturbance is noticeable. The low resistance values in the Wien network and the 3.8nVvHz noise specification of the LT1037 eliminate am- plifier noise as an error term. ‘aoa BsroRTCN Figure 41, Figure t's Distortion Characteristic at 10kHz ‘At ow frequencies, the thermal ime constant ofthe small normal mode lamp begins to introduce distortion levels above 0.01%. This is due to “hunting” as the osclator’s, frequency approaches the lamp thermal time constant. This effect can be eliminated, tthe expense of reduced cutput amplitude and longer amplitude setting time, by switching to the low frequency, low distortion mode. The four large lamps give a longer thermal time constant and distortion is reduced. Figure 42 plats distortion versus frequency forthe circuit Figure 43s version replaces the lamp with an electronic, amplitude stabilization loop. The LT1055 compares the oscillators positive output peaks with a DC reference. The diode in series with the LT1004 reference provides tem: perature compensation for the rectifier diode. The op amp biases Q1, controling its channe! resistance. This influ- ‘ences lop gain, which is reflected in oscilator output am- plitude. Loop closure around the LT1085 occurs, stabilizing oscillator amplitude. The 15yiF capacitor stabi- lizes the loop, wit the 22k resistor setting its gain, (= rane) Boos Figure 42. Figure 40's Distortion vs Frequency \4 mos Figure 49. Replacing the Lamp with an Electronic Equivalent AN43-30 LT WARApplication Note 43 Distotion performance fr this circuit is quite disappoint ing. Figure 44 shows 0.15% 2f distortion (trace B) in the ‘output (trace A), a huge increase over the lamp based ap- proach. This distortion does not correlate with the recti- fier peaking residue present at Q1's gate (trace C). Where isthe villain in this scheme? ome, ome 0 Figure 4, Figure 43 Produces Excessie| (Channel Resistance Modulation The culprit tums out to be Qi. In a FET, gate voltage the oretically sets channel resistance. Infact, channel voltage also sightly moduiates channel resistance. In this circuit Q's channel sees large swings at the fundamental. This, swing combines wit the channel voiage-resistance mod- Ulation effect, producing distortion, fotion Due to t's The cute for this difculy is local feedback around Qt Properly scaled, this feedback nicely cancels out the para Pit pet ih site, Figure 45 shows the cicuit redrawn with the inclu sion of Q1's local loop. The 20k trimmer allows adjustment to optimize distortion performance. Figure 46 shows re sults. Distorfon (trace 8) drops to 0.0018% and is com. posed of 21, some gain loop rectification artifacts and noise. For reference the circuits output (ace A) and the T1085 output (trace C) are shown. Figure 47 eliminates the trim, provides increased voltage and current output, and sightly reduces distortion. Qt is replaced with an optically driven CdS photocell. This de- vice fas no parasitic resistance modulation effecs. The T1055 has been replaced with a ground sensing op amp Note: wha elo sould te expected when rg io epace a single bulb wha turn ol lecraiccomgenets? | an hear Fgue 39 227 Tap ating ones STON Figure 48, Figure 45s 0.0018% Distortion Characteristic + aoe Figure 45. Local Feedback Around Qt Cures Channel Resistance Modulation, Reducing Distortion t0.0018% AT WEAR AN43-31Application Note 43 OF FL | tt como woae Figure 47. Replacing Qt with an Optically Driven CaS ‘unning in single supply mode. This permits true integra- tor operation and eliminates any possibilty of reverse bi- asing the (downsized) feedback capacitor. Additional feedback components aid step response.® Distortion per- formance improves sightly to 0.015%. The last Wien bridge based circuit borrows Figure 37's common mode suppression technique (whichis simply an AAC version of Figure 6's DC common mode suppression l00p) to reduce distortion to vanishingly smal levels. The T1022 amplifier appears in Figure 48. This ampitier forces the midpoint of the bridge to virtual ground by servo biasing the formerly grounded bridge legs. As in Figure 37, common mode swing is eliminated, reducing Note 6: A much beter chee fe alow Isic ceed be Packard HPO lest spon gan conta nop operating ard src manual sipped we Howe jen tse Photocel Eliminates Resistance Modulation Trim distortion. The circuit's output (trace A, Figure 49) con- tains less than 0.0003% (39pm) distortion (trace B), with 1 visible correlation to gain loop ripple residue (trace C) This level of distortion is below the uncertainty floor of most distortion analyzes, requiring specialized equipment for meaningful measurement. (See Appendix D, guest written by Bruce Hofer of Audio Precision, Inc, for a dis cussion on distortion measurement considerations.) Diode Bridge Based 2.5MHz Precision Rectifier/AC. Voltmeter A final circuit shows a way to achieve low AC error switching with diode bridge techniques. Diode bridges provide faster, cleaner signal switching than any other technique. AN43-32 AT WARApplication Note 43 a et BS pes sepoutr Figure 48, Adding Common Mode Suppression Lowers Distortion to0.0003% enr= nao Figure 49. Figure 48's ppm Distortions Below the Noise Floor ‘of Most Analyzers Most precision rectifier circuits rely on operational ampli fiers to correct for diode drops. Although this scheme works wel, Bandwidth lmitaions usualy restct these cir cuits to operation below 100kHz, Figure 50 shows the T1016 comparator in an open-loop, synchronous rectifier ‘configuration which has high accuracy out to 2.5MHz. An input 1MHz sine wave (race A, Figure 5t) is zero cross detected by C1. Both of C1's outputs drive identical level shifters with fast (delay = 2ns-3ns), +5V outputs. These outputs bias a Schottky diode switching bridge (traces 8 and C are the switched corners ofthe bridge). The input signal is fed to the left midsection ofthe bridge. Because Ci ives the bridge synchronously with the input signal, a half-wave rectified sine appears at the AC output trace D). The RMS value appears at the DC output. The Schottky bridge gives fast switching without charge pump- through, Ths is evident in trace E, which is an expanded version of trace D. The waveform is clean withthe excep- tion of very small disturbances where bridge switching oo cours. To calibrate this circuit, apply a 1MH2-2MHz 1Vp-p sine wave and adjust the delay compensation so bridge LT WR AN43-33Application Note 43 Figure 50. Fas, Bridge Switched Synchronous Rectifir-Based AC-DC Converter Figure 1. Fast AC-DC Converter Operating at 1MHz. lean Switching s De to Bridge Symmetry and Compensations for Delay and Switching Skew. switching occurs when the sine crosses zet0. Ths adjust ment corrects for the small delays through the LT1016 and the level shifters. Next, agjust the skew compensa- tion potentiometers for minimum aberrations in the AC output signal. These trims sigtly shit the phase of the rising output edge oftheir respective level shifter. This al lows skew in the complementary bridge drive signals to be kept within tns-2ns, minimizing output disturbances, when switching occurs. A 100m sine input will produce a clean output with a DC output accuracy of better than 0.25% Note: This application note was derived from a ‘manuscript originally prepared for publication in EDN ‘magazine AN43-34 AT WARApplication Note 43 References 1. Sheingold, D.H,, "Transducer Interfacing Handbook,” ‘Analog Devices Inc, 1980 2. Arthur, K., “Transducer Measurements,” Tektronix Ine., Concept Series, 1971 3, Parry, CH. "Diseases of the Heart.” Vol, 2, London, Underwoods, p. 111, 1825 4. Gordon, JW, "On Certain Motor Movements Human Body Produced by the Circulatio ‘Anatomy Physiology, 11:553-559, 1877 5, Start, |. and Noordegraft. A, “Balistocardiography in Cardiovascular Research,’ Lippincott, 1967 6. Weissler, AM, ‘Non-Invasive Cardiology.” Grune and Stratton, 1974 7. Meade, ML, ‘Lock-in Amplifiers and Appications,” London: P, Peregrinus, id 8. Wien, Max, "Measung der induction constanten mit dern Optischen Telephon,” Ann. der Phys., Vol. 44, 1891, p. 7047. 8. Meacham, L.A., “The Bridge Stabiized Osclator,” Bell System Technical Journal, Vol. 17, p. 574, Oct 1938 10. Hewlett, William R., "A New Type Resistance- Capacity Oscillator,” M.S. Thesis, Stanford University, Palo Alto, California 1939 ‘11. Hewlett, Wiliam R., US. Patent No, 2,768,872, Jan. 6, 1942 12, 14, 18, 16. 17. 20, at Bauer, Brunton, “Design Notes on the Resistance: Capacity Oscilator Circuit,” Parts | and ll, Hewlet- Packard Journal, Nov., Dec., 1949. Hewlett- Packard Company Wiliams, Jim, “Thermal Techniques in Measurement ‘and Control Circuit,” Linear Technology Corporation Application Note 5, Linear Technology Corporation, Milpitas, California 1984 Mattheys, R.L., ‘Crystal Oscillator Circuits," Wiley, New York, 1983 Hewlett-Packard, "Schottky Diodes for High- Volume, Low Cost Applications,” Application Note 942, Hewlett-Packard Company, 1973 Tektronix, Inc., “Type 1S1 Sampling Plug-In Operating and Service Manual,” Tektronix, Inc. 1965 Mulvey, J., “Sampling Oscilloscope Circuits,” Tektronix, Inc, Concept Series, 1970 Hil, W. and Horowitz, P., “The Art of Electronics,” Cambridge University Press, Cambridge, England 1989 Bowers, B., “Sir Charles Wheatstone,” Science Museum, London, England 1975 Nahin, Paul J., “ Oliver Heaviside: Sage in Solitude,” IEEE Press, 1988 Wilkinson, D.H., "A Stable Ninety-Nine Channel Pulse Amplitude Analyser for Slow Counting,” Proceedings ofthe Cambridge Philosophical Society, Cambridge England, 46,508. 1950 AT WNR AN43-35Application Note 43 APPENDIX A ‘STRAIN GAUGE BRIDGES In 1856 Lord Kelvin discovered that applying strain to a wire shied is resistance, This effect is repeatable, and is the basis for electrical output strain measurement. Early devices were simply wires suspended between two insu lated points (Figure At). The force to be measured me- chanically biased the wire, changing its resistance Modern devices utiiz foil based designs. The conductive mater is deposited on an insulated carrier (Figure A2). Physically they take many forms, allowing for a variety of applications. The gages! are usually configured in a bridge and mounted on a beam (Figure A3), forming a transducer, Note 1: Te carat speling gauge, bul roonged pana assaults have asassindthe"U" Heres, "gge assumes a cm olegiirary Figure At. A Very Basic Strain Gage Figure A3. A Conceptual Strain Gage Transducer. Bending Force on the Beam Causes Resistance Shits. A useful transducer must be trimmed for zero and gain, and compensated for temperature sensitty. Figure A4 shows a typical arrangement, Zero is set with a parallel trim, with similar treatment used to set gain. The gain trims include modulus gages to compensate beam mate rial temperature sensitivity. Arranging these tims and completing the mechanical integration involves a fair amount of attr, and is usualy best lt o specialists? Note 2: Those fnaing thelr sense of engineering prowess unaleraby effndd ae eter ta "SR San Gage Handbook" avaliable fom BLM ectronics, Carton, Massachuses Have un +E Figure A2. AConceptua strain Gage. Maximum Device Senstty i with Y-xis Flexing nto the Page. Practical Devices Utilize Denser Patterns with Optimized Distribution ‘of Conductive Material. Figure AA, Simplified Strain Gage Transducer Schematic AN43-36 ATWApplication Note 43 Semiconductor based strain gage transducers utilize resis- tive shift in semiconducting materials. These devices, built in monolithic IC form, are considerably less expensive than manually assembled fol based strain gage transduc- ers. They have over ten times the sensitivity of fil based devices, but are more sensitive to temperature and other effects. AS such, they are best suited to somewhat less demanding applications than foil based gages. Their monoithic construction and small size ofer price and con- venience advantages in many applications. Electrical form is similar to fol based designs (e.g, a bridge contigura- tion), although impedance levels are about ten times higher. The following guest written section details their characters. SEMICONDUCTOR BASED STRAIN GAGES Daniel A. Artusi Randy K. Frank Motorola Semiconductor Products Sector Discrete and Special Technologies Group Strain gage technology, while based on a phenomena which dates back to the nineteenth century, has been of major importance inthe areas of sttess analysis, structural testing and transduce fabrication for more than 40 years. First reports on semiconductor piezoresistive technology dates back to the observation by C.S. Smith? in the early 1950' of large piezoresistive coefficients in Siicon and Germanium There are several advantages to implementing strain {gages using semiconductor technology. The immediate ‘one isthe very high gage factors of approximately two or- ders of magnitude higher than metallic gages. These higher gage factors allow improved signal to noise ratios for the measurement of small dynamic stresses and sim- pits the signal conditioning circuitry. ‘Another advantage isthe precise contro of the piezoresis- tive coefficients including magnitude, sign, and the possi- bility of transverse and shear responses. Additional advantages are low cost, small size, and compatiblty with te 3 Srih'OS,Parowssnce Efe m Geman and Scan” Pyseal Reve, Volne 94, November, 654 Pages 4248, ‘semiconductor processing technology which allows for in- tegration of addtional circuit elements (¢. operational am pliers) on the same chip. The fist phase of integration for siicon pressure sensors occurred when the strain gage and the diaphragm were combined into one monoitic stucture. This was accomplished using the piezoresstive effect in semiconductors. A strain gage can be diffused or ior-implanted into a thin siicon diaphragm which has been chemically etched into a slicon substrate Piezoresistivity In order to understand the implementation in silicon of strain gages, itis necessary to review the piezoresistive etfectin silicon, ‘The analytic description ofthe piezoresstve effec in cu- bic silicon can be reduced to two equations which demonstrat te fst order effects AEy=Po ly(eynXs + 712%) fi AEp=Po lamaaXs, 2] Where AE, and AE, are electric field flux density, Po is the unstressed buk resistivity of slicon, I are the excita tion current density, x's are piezoresistive coetfcients and 1's ate stress tensors due to the applied force. The effect described by equation {1] is that utiized in a pressure transducer of the Wheatstone bridge type. Regardless of whether the designer chooses N-type or P- ‘ype layers forthe difused sensing element, the piezore- sistive coefficients 1, and m2 of equation [1] will be ‘oppose in sig. This implies that through careful placement, and orienta tion wih respect to the crystallographic axis, 2s well as a sufficiently large aspect ratio forthe resistors themselves, itis possible to fabricate resistors on the same diaphragm which both increase and decrease respectively from their ‘nominal values with the application of stress. The effect described by equation [2] is typically neglected as a parasite in the design of a Wheatstone bridge de- vice. A closer look at its form, however, reveals that the incremental electrical field flux density, AEp, due to the applied stress, Xg, is monotonically increasing for increas- ing Xe LT WEAR AN43-37Application Note 43 In fact, equation [2] predicts an extremely linear output since it depends on only one piezoresistive coefficient and one applied stress. Futhermore, the incremental lec tric field can be measured by a single stress sensitive ele- ment. This forms the theoretical basis for the design of the transverse voltage or shear stress piezoresistive strain gage. Shear Stress Strain Gage Figure A5 shows the construction of a device which opti- mizes the piezoresistive effect of equation (2), The di- phragm arisotopialy etched from a silicon substrate The piezoresistive element is a single, four terminal strain gage that is located at the midpoint of the edge of the ‘square diaphragm at an angle of 45 degrees as shown in Figure AS. The orientation of 45 degrees and location at the center of the edge of the diaphragm maximizes the sensitivity to shear sttess, Xg, and the shear stress being sensed by the transducer by maximizing the piezoresi tive coetcient, may Excitation current is passed longitudinally through the re sistor (ins + and 3) and the pressure that stresses the di phragm is applied at a right angle to the current flow. Note 4 JE Gragg US Pat 437,128 Figure AS, Basic Sensor Element — Top View The stress establishes a transverse electric field in the re- sistor that is sensed as an output voltage at pins 2 and 4, which are the taps located atthe midpoint of the resistor. The single element shear stress strain gage can be viewed as the mechanical analog of a Hall effect device. Figure A6 shows a cross section of a pressure transducer implemented in siicon and using the technique described. A ciferential pressure sensor chip is accomplished by ‘opening the back side of the water. Temperature Compensation and Calibration The transverse voltage shear stress piezoresistve pres- sure transduver has been shown to present certain ad- vantages over the Wheatstone bridge configuration. Spectcaly, improved linearity, and a more consistent re- producible ofset (since itis defined by a single phototho- graphic step), as well as the added advantage of integrating stresses over a smaller percentage of the flex- ural element. Very predictably, the transducer exhibits a negative tem perature coefficient of span with a nominal value of 0.19%/°C, as well as a temperature coefficient of offset that can bein the range of #154iV°C or slightly larger be fore compensation. TC of span is due tothe decrease of the piezoresistive coefficients with temperature due to in- creased thermal scattering inthe latce structure y suxgoerone /// Figure AS. Cross Section of Pressure Transducer AN43-38 ATERApplication Note 43 ee First les consider the relationship of output voltage, AVo, with excitation voltage, Vey, as predicted by equation 2). AVo=wil (44Xe) Vex 8 It is apparent thatthe output votage varies directly with excitation, by a factor wilirzaXe), or conversely thatthe output i ratiometric tothe exctaion, Vey. A typical output characteristic for an uncompensated transducer with a constant Vex applied is shown in Figure ‘A7. Hence, itis apparent that by increasing the supply voltage at the same rate that the full scale span is de- creasing, the undesired temperature dependence of span may be eliminated. This is accomplished by means of a very low TCR resistor placed in series with the transducer excitation legs which, by design, have a TCR of 0.24%4/°C (Figure A8). If the value of the zero-TCR span resistor is appropriately chosen, it wil decrease the "net" TCR of the combination to the ideal +0.19%/"C required to exactly ‘compensate the negative TC of SPAN. This technique is known as "sell-compensation,” and can be utlized in the described manner or with a constant current exciton and a parallel TC span compensation resistor. The passive circuit utlized to achieve calibration and tem. perature compensation is shown in Figure A8. Since the Single element design uses only one resistor for both the input and the output, a se-compensation scheme can be Figure 7. Output Span fr Uncompensated Transducer employed. This technique utiizes the temperature coef cient ofthe input resistance (TCR) to generate a tempera: ture dependent voltage. The TCR ofthe strain gage has been specifically designed to be greater in absolut value than the temperature coeficient of the span, so placing additonal passive resistive elements in series with the strain gage modifies the effective TCR and allows temper- ature compensation based onthe input resistance value at room temperature. A constant voltage source is all that is riecessary external othe deve to ensure accurate oper ation over a wide temperature range. The selt-compensation technique eliminates the requite- iment for thermistors which are used in most externally compensated Wheatstone bridge pressure sensors. In addition to the cost and nonlinearity characteristics of thermistors, their negative temperature coefficient precludes their integration on silcon. Thin fim resistors, ‘on the other hand, are easily deposited on the strain gage substrate using techniques similar to those required for the metalization of wire bond pads used to make connec tion to extemal leads. The laser trimming technique is, similar to that used in the manufacturing of high accuracy, monolithic, 16-bit analog-to-cijtal and digital-to-analog data converters, except that inthe case of a pressure transducer, the silicon diaphragm is exercised over the pressure range during the trimming procedure. Figure AB. On-Chip Temperature Compensation and Calibration AT WER AN43-39Application Note 43 Four separate functions are accomplished by the laser trimming operation: 1) Zeto calibration 2) Zero temperature compensation 3) Full scale span temperature compensation 4) Full scale span calibration The sequence in which the trimming operation is per- formed is important to avoid interaction of components and the addition of several iterations tothe trimming pro- cess. The main factor that allows high volume manufac: turing techniques, however, is the abilty to achieve temperature compensation in the single element sensor without the necessity to change the temperature during the trim operation. Measurements of the sensor parame: ters are made prior tothe laser trim operation, Computer calculations determine which resistors must be trimmed and the amount of trimming required. Resistor Rog, and Rog act as part of a voltage divider used to calibrate the offset. The output voltage is set to zero with zero pressure applied by trimming either offset resistor Rogrs oF Rog To temperature compensate the offset, thermistors RT- Coge; and RTCozr, a series of diffused silicon resistors with positive temperature coefficient and diferent values, are added as required tothe circuit by cutting aluminum shorting links Ful scale span temperature compensation is accomplished by ufizing self temperature compensation — the addition ofa single, series resistor to the input circuit when a con- stant voltage supply is used. The resistor is adjusted to compensate for changes in span with temperature by ad: justing the magnitude of the excitation voltage applied to the active element. In order to minimize common made er- rors, the ‘resistor is actually spit between the supply and ‘ground side ofthe input so that RS1=RS2. The span is ad justed to meet the specification by trimming resistor Py which is in paral wit the input resistance ofthe active el tement. The paralel resistor acualy interacts with the se- ‘ies sef compensation network to provde a series-parall temperature compensation which enhances the perfor ‘mance over the temperature range. Performance of Compensated Sensors The specification for Key parameters of a 30PSI on-chip temperature compensated pressure sensor is shown in Figure AQ. The excellent linearity isa result of the small active area of the single element strain gage — essen: tially a point condition. The temperature compensation which is achieved over 0°C to 85°C can be compared to ‘commonly available alternatives. amaueren [ww] wax) Prenwerancetniwy ff = || Fuseeespminn) | aes | @ | ats | RecPrssreofeetinmy | = | 4008 | +10 | Senger om Uneary 6 FS) | son | +02 (iewruruncerrerromocrome | Fulscouspan(F9) | ~~~ | 908] +10 Osetin y05_|_ 40 Figure A9, Specifications fora Typical Pressure Transducer AN43-40 ATEApplication Note 43 LL ‘APPENDIX B. BRIDGE READOUT — THEN AND NOW ‘The contemporary monoithic components used to read bridge signals are the beneficiaries of almost 150 years of dedicated work in bridge readout mechanisms. Some early schemes made fiendishly ingenious use of available technology to achieve remarkable performance. Figure 1 shows a light beam galvanometer. This device easily resolved currents in the nanoampere range. The un- ‘known current passed through a col, producing a mag- netic field. The col is mounted within a static magnetic field. The two field's interactions mechanically biased a ‘small miror, which was centrally mounted on a tautly sus- pended wire. The mirror may be thought of as the elas cally constrained shatt of a DC motor. The amplitude and sign of the coil current produced corresponding torque — like mirror movements. A collimated light source was bounced off the miror, and its reflection collected on a surface equipped with calibrated markings. The instu- rents high inherent sensitivity, combined with the gain in the optical angle, provided excellent result. The tangent galvanometer (Figure 82) achieved similar rnanoampere resolution. The actual meter movernent was, ‘a compass, centrally mounted within a circular coll Coll Figure B1. The Light Beam Galvanometerls Essentially A Sensitive Meter Movement. t Takes Gain inthe Optical Angle of A Mirror Reflected, Colimated Light Source (Courtesy The JM. Wiliams Collection). current is measured by noting compass deflection from the earths magnetic north. Current fow is proportional to the tangent of the measured deflection angle. These and similar devices were refered to as “null detec- tors.” This nomenclature was well chosen, and reflected the fact that bridges were almost always read at nul. This, was so because the only technology avaliable to accu: rately digitize electrical measurements was passive. “Bridge balances," including variable resistors, resistance decade bores and Kelvin-Varley dividers, were corner- stones of absolute measurements. No source of stable, calibrated gain was available; although the null detectors, provided high sensitvity. As such, bridge measurement depended on highly accurate balancing technology and sensitive null detectors. Lee DeForest's triode (1908) began the era of eletronia gain, Harold S. Black attempted to patent negative feed- back in 1928, but the U.S. Patent Office, in their govern- mental wisdom, treated him as a crackpot. Black published in the 1920's, and the notion of feedback stabi lized gain was immediately utlized by more enlightened Figure 2. A Tangent Galrenometer Measures Small Curent by Indicating the Interaction Between Applied Curent and the Eath’s Magnetic Field, Absolute Current Vale Is Proportional to the Tangent ofthe Compass Deflection Angle (Courtesy The JM. ‘Wiliams Collection) AT HER AN43-41Application Note 43 ———————_ types. The technology of the day did not permit develop ment of feedback based amplifiers which could challenge conventional bridge techniques. While Hewiett could use feedback to build a dandy sinewave oscillator, it simply was not good enough to replace Kelvn-Varley dividers and null detectors. Doing so required amplifiers with very high open loop gains and low zero dit. The second re- quirement was notably dificul and elusive. E.A. Goldberg invented the chopper stabilized amplifier in 1948, finaly making stable zero performance practical Electronic analog computers quickly folowed, and historic George A. Phlbrick Researches produced the fist com- mercially available general purpose op amps in the 19508. Null detectors were the frst bridge components to feel the impact of ali this. A number of notable chopper stabilized bridge nul detectors were produced during the 1950's and 1960's. All of these were essentially chopper based operational amplifiers configured as complete instru- ments. Notable among these was the Julie Research Laboratories sub-microvolt sensitivity ND-103, which fea- ‘tured a 93Hz mechanical chopper (to avoid any interac- tion with 6H2 noise components). The Hewlett-Packard HP-425 had similar sensitivity, and used a small syn- chronous clock motor, photocells and incandescent Note:The Hew Packard Carper rig tubs har had eg ard sues Note 2: Theta uy leer ara sit carver mas dvioedby DL Wika in 1945 (on alrenou) Te st nog Sgt comers avaible a8 dana pro were probably hese proaucady Patra Bacon in the ite 19603, tamps' in an elegantly simple photo-chopping scheme. Latter versions of this instrument (the HP-<19A) were completely solid-state, atough retaining a neon lamp- photocell chopping arrangement. Battery operation per- mitted floating the instrument across the bridge Concurrent to all this was the development of rackmounting based devices called “instrumentation amplifiers." These devices, designed to be applied at the system level, featured settable gain and bandwidth, differential inputs, and good zero point stability. Some were chopper stabilized while others utilized transistorized diferental connections. Sold by a numiber ‘of concerns, they were quite popular for transducer signal conditioning. These devices were the forerunners of modern IC instrumentation amplifiers. Their ability to supply low errors at zero and stable gain made accurate off-null bridge measurement possible. The development of analog-dgital converters during the 1960's? provided the last ingredient necessary for practical, cigtized output, of-ull bridge measurement. It had required over 100 years of technological progress to replace the null detectors and bridge balances. This is something to think about when soldering in IC. instrumentation amps and A-D converters. What Lord Kelvin would have given for a single min DIP! AN43-42Application Note 43 —_———_— APPENDIX C. ‘THE WIEN BRIDGE AND MR. HEWLETT The Wien bridge is easily the most popular basis for constructing sinewave oscilators. Circuits constructed around the Wien network offer wide dynamic range, ease of tuning, amplitude stability, low distortion and simplicity Wien described his network (Figure C1) in 1891 Unfortunately, he had no source of electronic gain avail able, and couldnt have made it oscilate even ifhe wanted to. Wien developed the network for AC bridge measure- ment, and went off and used it for that. Forty-eight years later William R. Hewlett combined Wiens network with controlled electronic gain in his mas: ters thesis. The results were the now familiar “Wien bridge oscillator” architecture and the Hewlett-Packard Company. Hewlett’ circuit (Figure C2) utlized the rela- tively new tools of feedback theory (see References) to support stable oscillation. Two loops were required. A Figure Ct. Wiens Network positive feedback loop from the ampliier’s output (6F6 plate) back to its postive input (67 frst grid) via the Wien bridge provided osciaton. Oscillation amplitude was sta- bilized by a second, negative, feedback loop. This loop ‘was closed from the output (again, the 6F6 plate) back to the amplifiers negative input (he 67 cathode). The now famous lamp supplied a sight postive temperature coeft- cient to maintain gain atthe proper value. For relerence in interpreting the vacuum tube! configuration, a modern version (text Figure 28) of Howiet's circuit appears as an inser Contemporary oscilators usually replace the lamps action with electronic equivalents to control loop setting time (see text) te For thts den yoars, vaso ube are ermioncaly acted FETs, descended Loo Dafoe ©z Figure C2. A Copy of Hewlett Thesis “Figure” Showing His Orginal Circut. Modem Version Shown or Reference (Hewlett Figure Courtesy Stanford University Archives), AT NER AN43-43Application Note 43 APPENDIX D UNDERSTANDING DISTORTION MEASUREMENTS Bruce E. Hofer Audio Precision, Inc. Introduction ‘Analog signal distortion is unavoidable inthe real word. It can be defined as any effect or process that causes the signal to deviate from ideal. Because “distortion” means signfcanty diferent things to diffrent people let us dis- tinguish between two general categories based upon tre- ‘quency domain effec. ‘A ingar distortion changes the ampitude and phase rela tionship between the existing spectral components of a signal without adding new ones. Frequency and phase re sponse errors are the most common examples. Both can cause significant alteration ofthe time domain waveform. ‘A nonlinear distortion adds frequency components to the signal that were never there, nor should be to begin with Nonlinear distortion alters both the time and frequency cdomain representations ofa signal. Noise can be consid ered a form of nonlinear distortion in some applications. Nonlinear distortion is generally considered to be more setius than linear distortion because it is impossible to determine if a specific frequency component in the output signal was present inthe input. Ths brief discussion will focus on the measurement and meaning of nonlinear dis- tortion only.The word ‘distortion’ shal hereinafter be used accordingly. Measures of Distortion (One ofthe best and oldest methods of quantifying distor tion isto excite a citcut or system with a retatvely pure sinewave and analyze the output forthe presence of sig- rnal components at frequencies other than the input sinewave. The sinewave is an ideal test signal for mea- suring nonlinear distotion because itis virally immune to linear forms of distortions. With the exoeption of a per- fecty tuned notch fier, the output of any linear distortion process wil sil be a sinewave! “Neth” harmonic distortion is defined as the amplitude of ‘any output signal at exactly N times the sinewave funda- ‘mental frequency tthe input sinewave is 400Hz any seo- ‘ond harmonic distortion will show up at 800Hz, third harmonic at 1200Hz, etc. Spectrum analyzers, wave ana- \yzers, and FFT analyzers are the typical instruments used to measure harmonic distortion. These instruments funo- tion by acting as highly selective voltmeters measuring the signal amplitude over a very narrow bandwicth centered at ‘a spectc requency. THD’ or Total Harmonie Distortion is defined as the RMS summation ofthe ampitudes of all possible harmonics, a though itis often simpified to include only the second ‘through the fith (or somewhat higher) harmonics. The as sumption that higher order harmonic content is insignif cant in the computation of THD can be quit invalid. The sinewave distortion of many function generators is usually dominated by high order harmonic products with only rel atively small amounts of products below the fifth har- monic, The crossover cistorion characteristic of class AB and 8 amplifiers can often exhibit significantly high har- monio content above the fifth order. Afar better deinion of THD is to include all harmonies up to some prescribed frequency limit. Usually the spe- cific application will suggest a relevant upper harmonic frequency limit, In audio circuits a justifiable upper fre quency limit might be 20kH2-25kH2 because few people can perceive signals above that range. In practice it has proven desirable to use a somewhat higher limit (typically 80kHz) because nonlinear distortion products above 20kH2 can provoke intermodulation problems in subse- quent aucio stages. In the word of FM and TV broadcast measurements itis common practice to usa a 30kHz, bandwith limit even though the signals are inherently lim ited to 15kH. AN43-44 ATERApplication Note 43 —_—_——— “THO+N’ or Total Harmonic Distortion plus Noise is de- fined as the RMS summation of al signal components, x- cluding the fundamental, over some prescribed bandwidth Distortion analyzers perform this measurement by remov- ing the fundamental sinewave with a natch fiter and mea- suring the leftover signal. Unfortunately some popular analyzers have excessive measurement bandwidth (@1MH2) with no provision for limiting, For the vast major ity of applications a measurement bandwidth of >500KH2, serves litle purpose other than to increase noise contribu tion and sensitty to AM radio stations. Today's better dis- tortion analyzers ofter a selection of measurement bandwidths typically including 20kHz-22kHz, 30kHz, S80kHz, and wideband (300kHz-500KH2). [A first glance it might appear that THD+N measurements are inferior to THD only measurements because of the sensitity to wideband noise. Even wit thet noise contr- bution today's cistorton analyzers offer the lowest resid- ual distortion, hence the most accuracy in making ultra-low distortion measurements. The typical residual contribution of spectrum analyzers is usually limited by their intemal mixer stages to about 0.003% (-90¢8). FFT analyzers do not fare much better due to A-D converter nonlinearities. The very best 16-bit converters available today do not guarantee residual distortion below about 0.002% although future developments promise to improve ths situation. Distortion analyzers offer the lowest resid- ual performance with at least one manufacturer claiming 0.0001% typical). “IMD" or InterModulation Distortion is yet another tech- nigue for quantifying noninearty,Itis @ much more spe- cialzed form of testing requiring a mul-tone test_signal IMD tests can be more sensitive than THD or THDsN tests because the specific test frequencies, ratios, and analyzer measurement technique can be chosen to opti- mize response to only certain forms of nonlinearity Unfortunately this is also one of the biggest cisadvan- tages of IMD testing because there are so many tess that have been suggested: SMPTE, CCIF, TIM, DIM, MTM, to name afew. Distortion Measurement Accuracy Nonlinear distortion is nota traceable characteristic in the sense that an unbroken chain of comparisons can be made to a truly distortion-less standard, Such a standard does rot exist! Real world distortion measurements will always include the non-zero contributions from both the sinewave source and the analyzer, Itis a truly challenging task to accurately measure distor tion below about 0.01% (-80d8). indeed, distortion mea surement errors can become quite large near residual levels. Harmonic contributions from the original sinewave and the analyzer can add algebraically, vectorialy, or even cancel depending upon their relative phase. There ‘are no general assumptions that can be made regarding how two residual contributions wil add or subtract. In the following equation let ‘M" be the measured value of the Nth harmonic, let" be the magnitude of the distortion contributed by the analyzer, and let “D" be the true distor- tion magnitude of some signal. The measured distortion wil be influenced by he residual analyzer contribution M*sin(2nNtte)=D" sin(2nNf}+X" sin(2nNt+@)} (04x) 1-0" 4 (D2+xe)"® if @=180° (0X) it@=180° Depending upon the relative phase between the distortion components (@) a true distortion factor (D) of 0.0040% could be read as anything between 0.0025% to 0.0055% if the analyzer’ internal distortion contribution (X) was 0.005%. Conversely a 0.0040% reading could have re sulted from a true distortion factor of anything from 0.028% to 0.0056% with the same 0.015% analyzer contibution Itis very important to understand this conoept when mak- ing distortion readings near the specified residual levels of the test equipment. A lower reading may nat always sigiy lower distortion. A low reading could be the result ofa fort itous cancelation of two larger contbutions. tis also ilogi- cal to conclude that the true value of cistron is always, less than the reading because the non-zero residual conti- butions of the analyzer and sinewave. The service manual LT WR AN43-45Application Note 43 ee of one test equipment manufacturer incredibly states that a 0.004094 reading verifies thei residual distortion guarantee (0f0.0020% for both oscilator and analyzer! All of the distortion measurement techniques give 0,5dB-1.0d8 (5%-10%) reading accuracies at higher reading levels. Some distortion analyzers additionally provide average versus true RMS detection. Average de tection is a carryover from the past and should be avoided because it will give erroneously low readings ‘when multiple harmonics are present. The Ultimate Meaning of THD and THD+N Measurements Both THD and THD+N are measures of signal impurity Distortion analyzers measure THD+N, not THD Spectrum, wave, and FFT analyzers measure individual harmonic distortion from which THD can be calculated, but not THDSN. is one better than the other? For most applications THD+N is the more meaningful measurement because it quantifies total signal impurty. Particularly as we enter the age of A-D and D-A based systems (for example, digital audio) the engineer is in- creasingly confronted with effets and imperfections that introduce non-harmonic components to a signal. Wideband noise itself can be viewed as an imperfection to be minimized. Itis tuly myopic to exclude other poten- tially serious and undesirable signal components in the determination of signal qualty just because they do not hhappen to be a harmonic of the test signal Why should a 60Hz component be acceptable inthe calculation of 20Hz THD but be excluded when testing with a 1kHz fundamental? (On the other hand THD measurements are istnctly bet ter than THD+N measurements if the application is to ‘quantify a simple transfer function nonlinearity. Noise, tum, and other interference products are not introduced by these simple forms of nonlinearity and should not influ ‘ence the measurement. Examples include the distortion due to component voltage coetticient effects and non- ‘ohmic contact behavior. Given that ail real signals contain some distortion, how much THD or THD4N is acceptable? Only the designer ccan make that determination. —————— ‘APPENDIX E ‘SOME PRACTICAL CONSIDERATIONS FOR BRIDGE INTERFACES. itis often desirable to route bridge outputs over consider able cable lengths. Cable driving should always be ap- proached with caution. Even shielded cables are ‘susceptible fo noise pick-up, and input protection is often in order. Figure E1 shows some options. Simple RC fiters often suffice for fitering. The upper limit on resistor value is set by ampiter bias current. FET input ampitiers alow large values, useful for minimizing capacitance size and input protection, Leakage eliminates electrolytic capaci tors as candidates, and the largest practical non-elec- trolyfc devices are about iF Otten, a single capacitor {dashed lines) is al that is required. Diode ciamps prevent high voltage spikes or faults (common in industrial env- ronments) from damaging the amplifier. Figure E2 sum- marizes some clamp alternatives. Sof 4 Figure 1, RC iter Altematves AN43-46 ATEApplication Note 43 [~ ~ LEAKAGE | Forwano | g25'c CLAMP TYPE: o (ASV REVERSE) =06V =10°% nv | =H =o | ‘= |] | oe L Figure £2. Various Device Offer Different Clamp Characteristics Figure E3 shows a high order switched capacitor based fiter, Te LTC1062 has no DC ertor, and offers much bet- ter rol-off characteristics than the simple RC types. LTC ‘Application Note 20, ‘Application Considerations for an Instrumentation Lowpass Fite,” presents details. Figure E4 shows a pre-ampliier used ahead of the re- motely located instrumentation ampitier. The pre-amp raises cable signal evel while lowering drive impedance. The asymmetrical bridge loading should be evaluated when using this circuit. Usually the ampitiers input resis- tor can be made large enough to minimize its effect. lo “hie” GI Figure E3, Switched Capacitor Techniques Permit aDC Accurate Sth Order Lowpass Filter Figure E4. Pre-Amplifier Provides Gain and Low Impedance Drive to Cable AT WAR AN43-47Application Note 43 a AN43-48 AneTECHNOLOGY 11074/LT1076 Design Manual Carl Nelson INTRODUCTION ‘The use of switching regulators increased dramatically in the 1980's and this trend remains strong going into the 90s, The reasons for this are simple; heat and efficiency. Today's systems are shrinking continuously, while simul- taneously offering greater electronic “horsepower.” This ‘combination would result in unacceptably high internal temperatures if low efficiency linear supplies were used. Heat sinks do not solve the problem in general because most systems are closed, with low thermal transfer from “inside” to “outside.” Battery powered ystems needhigh efficiency supplies for long battery Ife. Topological considerations also require switching technology. Fr instance, a battery cannot gen- erate an output higher than itself with near supplies. The availabilty f low cost rechargeable batteries has created a spectacular rise in the number of battery powered systems, and consequently @ matching rise in the use of switching regulators, The LT1074 and LT1076 switching regulators are de- signed specifically for ease of use. They are close to the ultimate “three terminal box” concept which simply re- quires an input, output and ground connection to deliver powerto the oad. Unfortunately, switching regulators are rot horseshoes, and “close” stil leaves room for egre- gious errors.n the final execution. This Application Note is intended to eliminate the most common errors that cus- tomers make with switching regulators as well as offering some insightinto the inner workings of switching designs. ‘There is also an entirely new treatment of inductor design based on the mathematical models of core loss and peak current. This allows the customer to quickly see the allowable limits for inductor value and make an inteligent decision based on the need for cost, size eto. The prace- dure differs greatly from previous design techniques and Application Note 44 September 1991 many experienced designers at first think it can’t work. ‘They quickly become silent after standard laborious trial and-error techniques yield identical results. There is an old adage in woodworking — "Measure twice, cutonce.” Thisadvice holds for switching regulators, also. Read ANA through quickly to familiarize yourself with the contents. Then reread the pertinent sections carefully to avoid “cutting” the design two, three, or fourtimes, Some switching regulator errors, such as excessive ripple cur- rent in capacitors, are time bombs best fixed before they are expensive field failures. Since this paper was originally written, Linear Technology has produced a CAD program for switching regulators called SwitcherCAD. This program uses the ideas pre- sented inthis application note, but adds an extra level of accuracy by factoring in more second order effects. Italso takes the drudgery out ofthe iterative design procedure allowing rapic “what i” exploration. | highly recommend using SwitcherCAD after absorbing the basic concepts presented here. Itouts design time considerably, presents detailed information on operating conditions, and has many safeguards to prevent unreliable designs. One cau- tion, however; SwitcherCAD has an initial run sequence, called Novice Mode, which generates a very conservative design from database components. The results of this initial design may not correlate with AN44 procedures because of assumptions used in SwitcherCAD and be- cause of the limited number of components in the data- base. Changing to Expert Mode allows all components to be changed at wil SwitcherCAD does not calculate components for loop stabil. Linear Technology will be creating several sepa- rate programs for this purpose during 1993. Contact our Application department for details. AT NEAR AN44-1Application Note 44 TABLE OF CONTENTS rRooucTiON ANdd-1 NEGATIVE BOOST CONVERTER Output Diode ‘ABSOLUTE MAXIMUM RATINGS... A443 Output Caption PACKAGE/ORDER INFORMATION AN4A-3 Output Ripple. Input Capacitor ELECTRIGAL CHARACTERISTICS. ANas3 INDUCTOR SELECTION BLOCK DIAGRAM ---AN44-5 Minimum Inductance to Achieve a Reauied Output Power. Se AN44-6 Minimum Inductance Required to Achieve TYPICAL PERFORMANCE CHARAGTERISTICS.....AN44-7 a Desired Core Loss PIN DESCRIPTIONS -AN4-10 MIGROPOWER SHUTOOWN Vivi ‘ANA4-i0 Start-Up Time Delay Ground Fin ANAAAO Feedback Pin fanaio-PIN CURRENT LIMIT Shutdown Pin ANG-11SOFTSTART Status Pin. : ANE 3 limi ANd-ig OUTPUT FILTERS. Error Ampliier : ANS-15 — jNPUT FILTERS DEFINITION OF TERMS. AN44-16 — QsciLLOSCOPE TECHNIQUES. POSITIVE STEP-DOWN (BUCK) CONVERTER......AN4-17 found Loops. Inductor ‘ANsd-19 Miscompensated Scope Probe Output Catch Diode ‘ANad-19 Ground “Clip” Pickup. T1074 Power Dissipation ‘ANs4-20 Wires Are Not Sorts Input Capacitor (Buck Converter) ‘ANA4-20 E491 SUPPRESSION. Output Capacitor ANGA-24 Eficiency ‘AN44-22 TROUBLESHOOTING HINTS Output Divider AN4-22 Low Efficiency Output Overshoo ... AN44-22 Alternating Switch Timing... Cvershoot Fixes that Don't Work AN44-23 Input Supply Won't Come Up Switching F Is Low in Current Limit TAPPED-INDUCTOR BUCK CONVERTER nu ANM23 — (CBIQUG UR! nena Snubber ANY-25 Ic Runs Hot Output Ripple Vottage AN44-26 High Output Ripple or Noise Spikes Input Capacitor AN-26 Poor Load or Line Regulation POSITIVE TO NEGATIVE CONVERTER wasn _S0KH2-SMHz Oscilations, Especially at Input Capacitor AN44-28, Light Load Output Capacitor ANA 29, Efficiency. AN44-30 AN4A-31 AN44-32 ‘AN44-32 AN44-33, ANA-33 AN44-33, ANA 34 AN4-35, AN44-38 AN4S-38 ANAS-39 ANAS-39 ANG4-40 AN44-42 ANSG-43 AN44-43 ANa4-44 AN4-44 AN4-44 AN44-45 wo AN44-46 ANG 46 ANA-46 ANA 46 AN44-46 ANG 46 ANSE-A7 AN44-47 aN4-47 ANAS-47 AN44-2 LT eeApplication Note 44 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION Input Voltage oxen UT1074/ LTH 7. 45V 7 oer aat | | LTSO74HV/7BHV eav 3 —— Switch Voltage with Respect to Input Votage oi " um1074cT 110741 76. ; 6aV is LT1074HVCT LT1074HV/76HV 75M siBbioz LT1076cT Switch Voge wit Respect to Ground Pin (yy Negative) ‘esas ne,onnen swmwoneo | LT1076HVCT L11074/76 (Note 6) 35V Hows ane. cnoes LTLO74HVITBHY (Note 6)... a5 | Feedback Pin Voltage -2V, +10V : ‘Shutdown Pin Vottage (Not to Exceed Vin). av) ee Pea Status Pin Voltage... sn OV > " LTi07ack (Current Must Be Limited to SmA When Status Pin cseisow | LTHO74HVOK Switches “On”) b LT1076MK {uy Pin Voltage (Forced) SV | on LT1076HVMK Maximum Operating Ambient Temperature Range LT076ck | LTHO7ACI76C, LT1O74HVCI7BHVE 0°C to 70°C, LT1076HVCK LTO74M/76M, LTIO7AHVWWTBHYM .~55°C 10 125°C | 1 —_| Maximum Operating Junction Temperature Range LT1074C/76C, LTIO74HVC/76HVC........0°C to 125°C oe Lmovacy | LT1O74M/76M, LT1074HVM/76HVM..-55°C to 150°C Td | Maximum Storage Temperature .....65°C 10 180°C rs Lead Temperature (Soldering, 10 sec.) 300°C 1 1 ve ato OO ELECTRICAL CHARACTERISTICS ;,- eae eanaTTONS - wa [ows Str Va eT Ti esta SO 185 ¥ ihyere u ¥ anore mo) ooY Sane \ ee ° 2 v : 3 ‘ 7am A um |e Tie i oA i ” Was V4) eH a Ghaincoht is . m™ Vourshivibne Susy ans) |S o_o ” AT ieee AN44-3Application Note 44 ELECTRICAL CHARACTERISTICS 5,- 25°C, vi.=25v, unless otherwise noted. ananeren [__enorons am wat — ws ie oe ioral 7 7 : i he toe 3 ta ‘ Seach Gar ia oe) Cro wee a rr A ees a sucmaows) : A TE Oe cr A Aes) a ; Ruse) 8 4 ian on a) % Sc Femoy @ we ysase g iw te oe § s te : Vast eh eh Ss Sin Foamy in eon 81s on weveea zat Erector 3000 rere Svea Sees wos vA Seeontsanes sattiataan _ mf a Fatih Paes re a= Vas . a A etre oa Yer [ins eat ee ¥ ake vo Tp ton = 35 a5 = Miter Vn, cat . a HE : _ Teg Teper se ad ae _ Fe a a apon 1607 . some aa {ot at0% uC ~ = 18 v ~~ Garten ie Rao oie nso Pare rr Veen 250 San Treo as} uy Cor «0 _ Niyiorbren Sawn Pre el a Susi Tyas AS Sutstovine Ta 8 rat Sei 2 Satan a IE 2 18 ul Ressines sun Os re z i fran ts chore _ | ‘The @danotes the speseations which apply oe the ful operating temperature rage Note: To calculate maximum sit “on vote at currents between Taw an nigh eondtons,aincr interpolation may De used Note 2: A foeback pin otage (Va) of 25 forces the We pint ts ow clamp eel andthe sch duty cycle to zero. This approxmatsthe ero Toad condton whee duty cycle approaches eo, Nate Total votage tram Va pinto ground pin must be 2 8V ater startup tor proper region. Note 4 Switch eaveny i iteraly scaled down when he feedback pin Valtage is ss than 13 fo avid extremely stor suit o1 mes. During lasting, Vig ate to give a rinamum uch on time f Tus Note: yy = SUM (7074), yy = = «T1076 Es 55 Nite 6: Switch 10 ng voltage imtaton must alo be observed Note 7: Vaux =40V forthe LT107476 ana 60V forthe LT1OTAHUIPEHY, Nate 8: Does not incite suite kaye AN44-4 AT HBApplication Note 44 BLOCK DIAGRAM urur gure s5>— ie = = etn ea SHIFT i cotta aml Mowe =~ c: atin : “ A e eases i {MLA on aca CLT GREATER THUS RABLE OMY ONT AT NER ANA4-5Application Note 44 BLOCK DIAGRAM DESCRIPTION ‘A switch oycle in the LT1074 is initiated by the oscilator setting the R/S latch. The pulse that sets the latch also locks out the switch via gate G1. The effective width ofthis pulse is approximately 700ns, which sets the maximum switch duty cycle to approximately 93% at 100kHz switch ing frequency. The switch is turned off by comparator C1, which resets the latch. C1 hasa sawtooth waveformasone input and the output of an analog multiplier as the other input. The multiplier output is the product of an internal reference voltage, andthe outputofthe erroramplifir, At, divided by the regulator input voltage. In standard buck regulators, this means that the output voltage of At required to keep a constant regulated output is indepen dent of regulator input voltage, This greatly improves line transient response, and makes loop gain independent of input voltage. The error amplifier is a transconductance type with 2 Gy at null of approximately 5000umho, Slew current going positive is 140uA, while negative slew current is about 1.1mA. This asymmetry helps prevent ‘overshoot on startup. Overall loop frequency compensa- tion is accomplished with a series RC network from Vg to ground. Switch current is continuously monitored by C2, which resets the R/S latch to turn the switch off if an overcurrent condition occurs. The time required for detection and switch turn-off is approximately 600ns. So minimum switch “on” time in current limit is 600ns. Under dead shorted output conditions, switch duty cycle may have to beaslowas 2% to maintain contol of output current. This would require switch on time of 200ns at 100kHz switch ing frequency, so frequency is reduced at very low output voltages by feeding the FB signal into the oscillator and creating a linear frequency downshift when the FB signal drops below 1.3V. Currenttrip evelis set bythe voltage on ‘the ly pin which is driven by an internal 320xA current source. When this pin i eft open, it self-clamps at about 4.5V and sets current imitat6.5A for the LT1074 and2.6A for the LT1076. In the 7-pin package an external resistor can be connected trom the I y¢pin to ground to seta lower current limit. A capacitor in parallel with this resistor wil soft start the current limit. slight offset in C2 guarantees ‘thatwhen the lnapin is pulled to within 200mV of ground, C2output wil stay high and force switch duty cycle tozero. The "Shutdown" pin is used to force switch duty cycle to zeroby pulling they pin ow, ort completely shut down the regulator. Threshold for the former is approximately 2.35V, and for complete shutdown, approximately 0.3V. Total supply current in shutdown is about 150A. A 10.4 pull-up current forces the shutdown pin high when left ‘open. Acapacitor can be used to generate delayed startup. A resistor divider will program “undervoltage lockout” i the divider voltage is set at 2.35V when the input is at the desired trip point. ‘The switch usedin the LT1074isa Darlington NPN (single NPN for LT1076) driven by a saturated PNP. Special patented circuitry is used to drive the PNP on and off very quickly even from the saturation state. This particular switch arrangement has no “isolation tubs” connected to ‘the switch output, which can therefore swing to 40V below ground, AN44-6 AT eRApp! ication Note 44 TYPICAL PERFORMANCE CHARACTERISTICS VePinCharaceristies Ve Pin Characteristics Feedback Pin Characterisies ae 2 Po 0 15 et 100, Yew ADJUSTED FOR 10 ») I SARE : smo] —— sit ze gos ml eee set Ze Ee 5 - T i 1 5-3} som ama: es Bett wo} fT “9 = 0! “- os aa 20 2 “ao rr) ores ese es oT reese TEER vow vous vous Shutdown Pin Characteristics Shutdown Pin Characteristics « ° eae * ni T 5} seen nowsour ! ee sungon » t “0 1 3°) cron sy os zn io iain | 5-n| | Bay » | + al menses | |] ~ ‘ica cram st ol Lis “4 i a ee) O05 WO As 025 88 a a aerate sere ONE voumem voce Staus Pin Characterisies Status Pin Characteristics Supply Curent «| {4 [ i imei of 4 S sais rao va See t - = [sane Ee z) seven swromte Ky 2 er Ev “a : / 5 *[sanccoomen auf Ss - = os an lA = ods 02 a3 Gs Os G8 G7 te vouase out wae eur vara AT iene AN44-7Application Note 44 TYPICAL PERFORMANCE CHARACTERISTICS AeterenceVotape ve a ‘Supply Current (Shutdown) . Temperature ‘Switch “On” Voltage | aL “ yee 250 al t as _ sare i= iz 7 4H Ra ate fs Fal ee BS Bom aS 5 aa +1} ‘tus | | : 4 ol a rt ol a | ob Lt | Pee ee ee sewvrweny mre semo.onwer Aefrenc Shit wih ipo wihing eoatoy vs vote et ae eae e* _™ ~ sos a i ewe} e2 won| gt jy de ira Ha 0 Few | ES i a ried 24 100 cy { gol it z 7 T noo i. is | im 9 AD a 10 TH TD 10 200 PEAK TO-PMKRPREATEB PG) Feedback Pin Frequency Shit | Ew | 3 a gu Iai : 2 0| of ff : ee ae} 2 "cos 10 18 20 25 a0 FEDaNoK PN VOLTAGE pe) mw wo Ta 10 SONTON TEMPERATE) Curect Limit ve Temperature 1 7 pupa oe ‘ 2 ue ao 4 [etree oro 8 “gas 0 SO 1S 10) 15 1 {TON eUPERATRE AN44-8 LT NEBTYPICAL PERFORMANCE CHARACTERISTICS Operating Input Supply Current* Feedback Pin Frequency Shit 0 Application Note 44 Shutdown Threshold “ {> puck comvenren 035 . 2 o 020 1+ 6 2 0 & ors | ‘ Bol she 2 owl + : ( CH so 250-2 HS «100 125 150 UNETION TEMPERATURE Ve Voltage vs Input Voltage TTT TT ax coments ontmuaysuooe | W207 uy fusow IMPIT OUTAGE ve voce ° J oa www wo ia Te 0 REDEREX PI CURRENT sq WeVtage we Outpt Vliage ovrncus mode | ws we ws Ow uTPUT WOLTER) ACTIN TEMPERATURE (0) Status Delay and Minimum Timeout TT) 55 Sag Lo THE] 2 Notes a l ACTION TEMPERATURE sraTWSWIL WoT GO LOWE OUTPUTS (TBE WOW FOR LESS THAN DAY aE AT WHER AN44-9Application Note 44 PIN DESCRIPTIONS Vu PIN The Vjy pin is both the supply voltage for internal control circuitry and one end of the high current switch. It is important, especialy @t low input voltages, that this pin be bypassed with alow ESR, and low inductance capacitor to prevent transient steps or spikes from causing erratic operation. At full switch current of 5A, the switching transients at the regulator input can get very large as showin in Figure 1. Place the input capacitor very close to the regulatorand connect it with wide traces to avoid extra inductance. Use radial lead capacitors. Figure 1. Input Capacitor Ripple Lp= Total inductance in input bypass connections and capacitor. “Spike” height (giet} is approximately 2V per inch of lead lent, Step =0.25V for ESR = 0,050 and Igy = 5A 0.25V. Ramp = 125m for C = 200uF, Tow = 5us, and Igy = 5A is 125mV, Input current on the Vy Pin in shutdown mode isthe sum of actual supply current (=140uA, with a maximum of 300A) and switch leakage current. Consult factory for special testing if shutdown mode input currentis critica GROUND PIN It might seem unusual to describe a ground pin, butin the case of regulators, the ground pin must be connected properly to ensure good load regulation. The internal reference voltage is referenced to the ground pin; so any errorin ground pin voltage will be multiplied atthe output, _(6Vou0) our) AVour 251 To ensure good load regulation, the ground pin must be connected directly to the proper output node, so that no high currents flow inthis path. The output divider resistor should also be connected to this low current connection line as shown in Figure 2, secamer Figure 2. Proper Ground Pin Connection FEEDBACK PIN ‘The feedback pinis the inverting input ofan error amplifier which controls the regulator output by adjusting duty cycle. The non-inverting input is internally connected to a trimmed 2.21V reference. Input bias current is typically 0.5uA when the error amplifiers balanced (Iqyr=0). The error amplifier has asymmetrical Gy for large input sig- nals to reduce startup overshoot. This makes the amplifier more sensitive to large ripple voltages atthe feedback pin. 400mVp-p ripple atthe feedback pin will create a 14mV offsetin the amplifier, equivalent to a0.7% output voltage shift. To avoid output errors, output ripple (p-p) should be less than 4% of DC output voltage at the point where the ‘output divider is connected ‘See the “Error Amplifier” section for more details Frequency Shitting at the Feedback Pin ‘The error ampilier feedback pin (FB) used to downshift the oscillator frequency when the regulator output voltage is low. This is done to guarantee that output short circuit AN44-10 LT eRApplication Note 44 _—_— PIN DESCRIPTIONS current is well controlled even when switch duty cycle must be extremely low. Theoretical switch “on” time fora buck converter in continuous mode is; toy = Sour +0 Viner Vp = Catch diode forward voltage ( = 0.5V) {= Switching frequency Att = 100kHz, toy must drop to 0.2us when Viy= 25V and the output is shorted (Voyr = OV). In current limit, the LT1074 can reduce toy to a minimum value of ~ 0.6, much too ong to control current correctly for Vour=0.To correct this problem, switching frequency i lowered from 400kHz to 20kHz as the FB pin drops from 1.3V to O.5V. This is accomplished by the circuitry shown in Figure 3 1 is off when the output is regulating (Vig = 2.21V). As the output is pulled down by an overload, Vrg will eventually reach 1.3V, turning on Q1. As the output continues to drop, Qt current increases proportionately and lowers the frequency of the oscillator. Frequency shifting starts when the output is = 60% of normal value, and is down to its minimum value of = 20kH2 when the output is = 20% of normal value. The rate at which frequency is shifted is determined by both the internal 3k resistor R3 and the external divider resistors. For this reason, R2 should not be increased to more than 4kQ, if the LT1074 will be subjected to the simultaneous condi- tions of high input voltage and output shor circu. SHUTDOWN PIN The shutdown pin is used for undervoltage lockout, micropower shutdown, soft start, delayed start, or as a {general purpose onvotf control ofthe regulator output. It controls switching action by pulling the I jyapin low, which forces the switch to a continuous “off” state. Full ‘micropower shutdowns initiated when the shutdown pin drops below 0.3V. ‘The V/I characteristics of the shutdown pin are shown in Figure 4. For voltages between 2.5V and =Vjy, a current of 10,A flows out of the shutdown pin. This current increases to =25yA as the shutdown pin moves through the 2.35V threshold. The current increases further to ~ ‘30uA at the 0.3V threshold, then drops to =15yA as the shutdown voltage falls below 0.3V. The 10uA current source is included to pull the shutdown pin to its high or default state when lett open. Italso provides a convenient pullup for delayed start applications with a capacitor on ‘the shutdown pin, When activated, the typical collector current of Q1 in Figure5, is=2mA. Asoft start capacitor on the |, pin will delay regulator shutdown in response to C1, by =(5V)(Cix/2mA. Soft start after full micropower shut- down is ensured by coupling C2 to Q1 Beou.aToR Figure 3. Frequency Shitting AT Wnene AN44-11Application Note 44 PIN DESCRIPTIONS “eSHuToSmn ou) Figure 4, Shutdown Pin Characteristics Undervoltage Lockout Undervoltage lockout point is set by Rt and R2 in Figure 6. To avoid errors due to the 10uA shutdown pin current, 2 is usually set at 5k, and R1 is found trom: (Vre — Vex) Vou \Vyp= Desired undervoltage lockout voltage, gy = Threshold for lockout on the shutdown pin = 2.45V. It quiescent supply currentis critical, R2 may be increased up to 15kQ, but the denominator In the formula for R2 should replace Vsu with Vey ~ (10,A)(R2). Hysteresis in undervoltage lockout may be accomplished by connecting a resistor (R3) from the Ii pin to the shutdown pin as shown in Figure 7. D1 prevents the shutdown divider from altering current limit. RI=R2. AN44-12 cutoan Figure 6. Shutdown Cieulry Figure 6. Undervottage Lockout Sa Figure 7. Adding Hysteresis. ATRPIN DESCRIPTIONS TR3is added, the lower trip point (Vy descending) will be the same. The upper trip point (Vrp) will be; (,,R1, RY Rt Vore = Vou [1+ 55 -B) av (8) If R1 and R2 are chosen, R3 is given by (Yon -0.8V) (1) Rt Vore ~Yo (14 73) Example: An undervoltage lockout is required such that the output will not start until Viy = 20V, but will continue to operate until Viy drops to 1V. Let R2 = 2.32k. _ (18v -2.35v) t= (2.82) = 12.54 pa 235-08) (12.5) _ 5 oy 20~2.98(14 125 (0 2.32. STATUS PIN (AVAILABLE ONLY ON LT1176 PARTS) The status pinis the output ofa voltage monitor “looking” at the feedback pin. Its low fora feedback voltage which is more than 5% above or below nominal. “Nominal” in this case means the internal reference voltage, so that the :£5% window tracks the reference voltage. A time delay of = 1041s prevents short spikes from tripping the status lov. Onceit does go low, asecond timerforcesitto stay low for ‘a minimum of = 30s. Application Note 44 The status pin is modeled in Figure 8 with a 130, pullup to.a4.5V clamp level. The sinking driveis a saturated NPN with =1000 resistance and a maximum sink current of approximately SmA. An external pullup resistor can be added to increase output swing up to a maximum of 20V. When the status pin is used to indicate “output OK,” it becomes important to test for conditions which might Create unwanted status states. These include output over- shoot, large signal transient conditions, and excessive output ripple. “False” tripping ofthe status pin can usually be controlled by a pulse stretcher network as shown in Figure 8. A single capacitor (Ct) will suffice to delay an output “OK" (status high) signal to avoid false “true” signals during start-up, etc. Delay time for status high wil beapproximately (2.3x 104) (C1), or23ms/uF. Status low delay will be much shorter, = 600js/HF. sus Figure 8. Adding Time Delays to Status Output AN44-13Application Note 44 PIN DESCRIPTIONS Itfalse tripping of status “Iow’ could be a problem, Rt can be added. Delay of status high remains the same it Rt < 10kQ. Status low delay is extended by Rt to approxi- mately R1 + C2 seconds. Select C2 for high delay and R1 for low delay. Example: Delay status high for 10ms, and status low for ‘ms. 10ms 2 = — ——_ = 0.47, F (Us 02 = ache uF (Use O.47uF ) ims 3ms Ri== = 64kKQ 2 O47uI In this example 01 is not needed because 1 is small enough to not limit the charging of C2. If very fast “low” tripping combined with long “high” delaysis desired, use the D2, R2, R3, C3 configuration. C3 is chosen first to set “low” delay tLow 3 0 Ris then selected for “high” delay t 3 = {HIGH B= t3 For tow = 100us and tuigh = 10ms, C3 = 0.05uF and R3 = 200k0. Tum PIN The ya pinisused to reduce currentlimit below the preset value of 6.5A. The equivalent circuit fo this pin is shown in Figure 9 When I jyisleftopen, the voltage at Q1 base clamps at SV ‘through 02. Internal current limit is determined by the current through Q1. If an external resistor is connected between luyy and ground, the voltage at Q1 base can be reduced for lower current limit. The resistor will have a voltage across it equal to (320uA) (R), limited to ~ 5V ‘when clamped by D2, Resistance required for a given current limit is, Punt = lum (2k) + 1402 (L71074) Runa = lum (5.5k2) + 10 (LT1076) AAs an example, a 3A current limit would require 3A (2k) + ‘1k = 7aC2for the LT1074. The accuracy of these formulas is£25% for 2A Iyy<5A(LT1074)and0.7A< I y<1.8A (L71076), 50 liyy should be set at least 25% above the ‘peak switch current required. Tour, cur Figure 8. hun Pin Circuit Foldback current limiting can be easily implemented by adding a resistor from the output to the I pias shown, in Figure 10. This allows full desired current limit (with or ‘without Ri) when the output is regulating, but reduces ‘current imit under short circuit conditions. Atypical value for Regis 5k, but this may be adjusted up or down to set the amount of foldback. 02 prevents the output voltage from forcing current back into the I pin. To calculate a Figure 10. Foldback Current Limit AN44-14 LTRPIN DESCRIPTIONS value for Rep, first calculate Rua, then Rep; Isc — 0.44") (R, Ryp = 8244 VEAL) (inka) 0.5" (Ry 1k) ~ gg *Change 0.44 to 0.16, and 0.5 to 0.18 for LT1076. Example: lum = 4A, Igo = 1.5A, Rim = (4)(2k) + 1k = 9k _ (15-044) (HO) _ 5 4 FB 0.5(9k—tk) -15 ERROR AMPLIFIER The error amplifier in Figure 11 is a single stage design with added inverters to allow the output to swing above and below the common mode input voltage, One side of the ampliferis tied toa trimmed internal reference voltage of 2.21V. The other input is brought out as the FB (feed back) pin. This amplifier has a Gy (voltage “in” to current “out’) transter function of =5000.mho. Voltage gain is determined by multiplying Gy times the total equivalent ‘output loading, consisting of the output resistance of Q4 ‘and Q6 in parallel with the series RC external frequency compensation network. At OC, the external RC is ignored, and with a parallel output impedance for Q4 and Q6 of -400kQ, voltage gains = 2000. At frequencies abovea few hertz voltage gain is determined by the external compen- sation, Re and Ce, Ay = a HG at mictequences Gn# Rg at highfrequencies = i Phase shift from the FB pin to the Vo pin is 90° at mid- frequencies where the external Ccis controling gain, then drops back to 0° (actually 180° since FB is an inverting input) when the reactance of Cc is small compared to Ro. The low frequency “pole” where the reactance of Co is equal to the output impedance of Q4 and 06 (Fo), is 1 fro = >= == fo = 400K02 Teepe 0 ~ 400 Application Note 44 Although fpoce varies as much as 3:1 due to rg variations, mid-frequency gain is dependent only on Gy, which is specified much tighter on the data sheet. The higher {requency “zero" is determined solely by Re and Cp. = DeeRe* Cp The error amplfierhas asymmetrica/peak output current. (03nd Q4 current mirrors are nity gain, but the Q6 mirror has again of 1.8 at output null and a gain of 8 when the FB pin is high (Q1 current = 0). This results in a maximum positive output current of 140.Aanda maximum negative (sink) output current of = 1.1mA. The asymmetry is deliberate — it results in much less regulator output overshoot during rapid startup or following the release of ‘an output overload. Amplifier offset is kept low by area scaling Q1 and Q2 at 1.8:1 treo = Amplifier swing is limited by the internal 5.8V supply for Positive outputs and by D1 and D2 when the output goes low. Low clamp voltage is approximately one diode drop (=0.7V-2mviec) Note that both the FB pin and the Vg pin have other internal connections. Refer to the frequency shifting and sychronizing discussions. ona Figure 11. Eror Amplifier LT Wee AN44-15Application Note 44 DEFINITION OF TERMS Vjw: DC input voltage. Vin’: DG input voltage minus switch voltage loss. Vin’ is 1.5 Vto 2.3V ess than Vin, depending on switch current. Vout: DC output voltage. Vour' 0C output voltage plus catch diode forward voltage. Vour is typically 0.4V to 0.6V more than Vout. f: Switching frequency. iy: Maximum specified switch current I = §.5A for the (11074 and 2A for the LT1076. Igy: Switch current during switch on time. The current typically jumps toa starting value, then ramps higher. Igw is the average value during this period unless otherwise stated. Itis notaveraged over the whole switching period, which includes switch off time four: DC output current. um: DC output current limit. Ipp: Catch diode forward current. Ths is the peak current for discontinuous operation and the average value of the current pulseduring switch off time for continuous mode. Ina: Catch diode forward current averaged over one com- plete switching cycle. Ing is used to calculate diode heating. ‘Al: Peakcto-peak ripple current inthe inductor, also equal to peak current in the discontinuous mode. Al is used to calculate output ripple voltage and inductor core losses. Vp-p: Peak-to-peak output voltage ripple. This does not include “spikes” created by fast rising currents and ca- pacitor parasitic inductance. {sw This isnot really an actual rise or falltime. Instead, it represents the effective overlap time of voltage and cur- rent the switch. tgw is used to calculate switch power aissipation Inductance, usually measured with low AC flux densi and zero OG current. Note that large AC flux density can increase L by up to 30%, and large DC currents can decrease L dramatically (core saturation), Be: Peak AC flux density inthe inductor core, equal to ‘one-half peak-to-peak AC flux density. Peak value is used because nearly all core loss curves are plotted with peak flux density N: Tapped-inductor or transformer turns ratio. Note the exact definition of N for each application HH: Effective permeability of core material used in the inductor. is typically 25-150. Ferrite material is much higher, buts usually gapped to reduce the effective value to this range Ve: Effective core material volume (cm). Let Ete ‘Ag: Effective core cross sectional area (om). ‘Ay: Effective core or bobbin winding area ‘core magnetic path length (cm). [Lg Average length of one turn on winding, Pcy: Power dissipation caused by winding resistance. It does not include skin effect. Pe: Power loss in the magnetic core. Pr depends only on ‘pple current nthe inductor not DC current. E: Overall regulator efficiency. It is simply output power divided by input power. AN44-16 LT WEARApplication Note 44 —_— POSITIVE STEP-DOWN (BUCK) CONVERTER The circuit in Figure 12s used to convert a larger positive input voltage to a lower positive output. Typical wave~ forms are shown in Figure 13, with Viy=20V, Vour=5V, LL = 50jH, for both continuous mode (inductor current never drops to zero) with Ioyr = 3A and discontinuous mode, where inductor current drops to zero during a portion of the switching cycle (Igy = 0.17A). Continuous ‘mode maximizes output power but requires larger induc- tors. Maximumoutputcurrentin true discontinuous mode is only one-half of switch current rating. Note that when load current is reduced in a continuous mode design, eventually the circuit will enter discontinuous mode. The T1074 operates equally wel in either mode and there is ro significant change in performance when load current reduction causes a shift to discontinuous made. eno ase 178 Figure 12. ase Poste Buck Comer Duty cycle of a buck converter in continuous mode is pg = Your “Yi _ Your oT © Vin=Vow Vin \Vy= Forward voltage of catch diode Vy = Voltage loss across “on” switch Note that duty cycledoes not vary with load current except to the extent that Vj and Vsw change slighty ‘A buck converter will change from continuous to éiscon- tinuous mode (and duty cycle will begin to drop) ataload current equal to (Your) (Mni~ Your’) louwenm) = "35 Yqge Fol (02) With the possible exception of load transient response, there is no reason to increase L to ensure continuous mode operation at light load. Using the values from Figure 12, with Viy=25V, V;=0.5V, Vsw = 2V DC= = 5 oat (03) (5.5)(23-5.5) Nouriontt) = 0.42 (68 3(29)(108) (5010-5) The “ringing” which occurs at some point in the switch “off” cyclin discontinuous mode is simply the resonance created by the catch diode capacitance plus switch capaci- tance in parallel with the inductor. Ths ringing does no harm and any attempt to dampen it simply wastes etfi- ciency, Ringing frequency is given by; 1 ‘anes ———— (04) 2n,\Le(Csw + Covove ) Cow = 809F Coione = 200pF - 10009F No off state ringing occurs in continuous mode because the diode is always conducting during switch off time and effectively shorts the resonance. A detailed look atthe leading edge of the switch waveform may reveal a second “ringing” tendency, usually at fre- quencies around 20MHz-SOMHz. This is the result of the inductance in the loop which includes the input capacitor, the LT1074 leads, and the diode leads, combined with the capacitance of the catch diode. A total lead length of 4 inches will create =0.1yH. This coupled with 500pF of diode capacitance will create a damped 25MHZ oscillation superimposed on the fast rising switch voltage waveform. ‘Again, no harm is created by this ringing and no attempt should be made to dampen it other than minimizing lead length. Certain board layouts combined with very short interconnects and high diode capacitance may create a tuned circuit which resonates with the switch output to AT HER AN44-17Application Note 44 Continuous (lour= 3) Discontinuous (lqut = 0.168) [ ‘ay VOLTAGE roa) (iooaoe verre) ie os rt He syne FEA wpm TST A Fe aa + ‘wai J: H guerre Figure 13. Buck Converter Waveforms with Vy=20V, L = S0uH cause a low amplitude oscillation at the switch output during “on” time. This can be eliminated with a ferrite bead slipped over either diode lead during board assembly. Itis interesting to note that standard silicon fast recovery diodes create almost no ringing because of their lower capacitance and because they are effectively damped by their slower turn-off characteristics. This slower turn-off and the larger forward voltage represent additional power toss, so Schottky diodes are normally recommended. ‘Maximum output curtent ofa buck converter i given by; Continuous Mode (05) Vout (Vin= Vout) 2 Vinel hy = Maximum switeh current (5.58 for LT1074) Vin= DC input voltage (maximum) Vour = Output voltage witching frequency our (wax) =! ~ AN44-18 ATSFor the example shown, with L = 50uH, and Vjy = 25V, 5 (25-8) if =§.5-——_““"_ —=51A (06) aro SS” TF) 256010") » Note that increasing inductor size to 100uH would only increase maximum output current by 4%, but decreasing it to 20H would drop maximum current to 4.5A. Low inductance can be used for lower output currents, but core loss will increase. Inductor ‘The inductor used in a buck converter acts as both an energy storage element and a smoothing filter. There is a basic tradeoff between good fering versus size and cost. Typical inductor values used with the LT1074 range from 5uH to 200uH, with the small values used for lower power, ‘minimum size applications and the larger values used to maximize output power ot minimize output ripole voltage. The inductor must be rated for currents atleast equal to ‘output current and there ae restrictions on ripple current (expressed as volt « microsecond product at various fre- quencies) toavoid core heating. For details on selectingan inductor and calculating losses, see the “Inductor Selec- tion” section Output Catch Diode D1 is used to generate a current path for L1 current when the LT1074 switch turns off. The current through D1 in Continuous mode is equal to output current with a duty cycle of (Vin - Vour)/Vin. For low input voltages, D1 may operateat duty cycles of 50% or less, butone must be very careful of utilizing this fact to minimize diode heat sinking, First, an unexpected high input voltage will cause duty cycle to increase. More important however, is a shorted Output condition. When Voyr=0, diode duty cycleis~1 for any input voltage. Also, in current limit, diode current is hot load current, but is determined by LT1074 switch current limit. ff continuous output shorts must be tolerated, D1 must be adequately rated and heat sunk. 7 and 11-pin versions ofthe LT1074 allow currentlimit to be reduced to limit diode dissipation. 5-pin versions can be accurately current limited using the technique shown in Figure 20. Application Note 44 Under normal conditions, D1 dissipation is given by; Por= our (nou, (7 in jis the forward voltage of D1 at Ioyr current. Schottky diode forward voltage is typically 0.6V at the diode’s full Fated current, soitis normal design practice to usea diode ratedat 1.5 to 2timas output currentto maintain efficiency and allow margin for shortcircuit conditions. This derating allows Vj to drop to approximately 0.5V Example: Vinonax) =25V, lour= 3A, Vour = 8V, assume Vy=05V, Full Load (08) (3)(25-5)(0.5V) Ey Pos Shorted Output Po: =(~6A)(0C = 1)(0.6v)=3.6W The high diode dissipation under shorted output condi- tions may necessitate current limit adjustmentif adequate hheat sinking cannot be provided. Diode switching losses have been neglected because the reverse recovery time is assumed to be short enough to ignore, If a standard silicon diode is used, switching Josses cannot be ignored. They can be approximated by; Phre=(Vin) (fer) our) (09) ‘ter = Diode reverse recovery time Example: Same circuit with ty = 100ns Pte =(28)(105] (10-7) (3) = 0.75 (19) Diodes with abrupt turn-off characteristics will transfer most of this power to the LT1074 switch. Soft recovery diodes will dissipate much of the power within the diode itset. AT WEAR AN44-19Application Note 44 11074 Power Dissipation The LT1074 draws about 7.5mA quiescent current, inde- pendent of input voltage or load. It draws an additional ‘5mA during switch “on” time. The switch itsetf dissipates ‘power approximately proportional to load current. This power is due to pure conduction losses (switch “on” voltage times switch current) and dynamic. switching losses due to finite switch current rise and falltimes. Total T1074 power dissipation can by calculated from P=Viul7MA+5MADC+Zlouretgwet]+ — (tt) 2) DC | Hour (1.8V)" + 0.12 (Igy (ant Vour +0.5V De =Duty Cycle = ty Oem tay = Effective overlap time of switch voltage and current = 50ns + (3ns/A) (lout) (T1074) = 60ns + (10ns/A} (lou) (LT1076) Example: Vu = 25V, Vout = 5Y, gw = 50ns+( 3ns/A)(3A) = 59ns 5 (13) ef 5TA(018) +] og 119) sone : +01 |(2)2)(60n9 (109) | [3019)+ 010] =O21W + O89W +124W =234W ‘Supply Dynamic Sch Curent Sutching Conduction tose Loss Lass “L11076 = 1V, 030 ‘Input Capacitor (Buck Converter) ‘A oral input bypass capacitor is normally required for buck converters because the input current is a square wave with fastriseand fal times. This capacitors chosen by ripple current rating—the capacitor must be large enough to avoid overheating created by its ESR and the AC RMS value of converter input current. For continuous ‘mode; eal boas =lour YOU Vout \ (nF Worst case is at Vin = 2Vour. (14) Powerlossinthe inputcapacitoris notinsignificantin high efficiency applications, itis simply RMS capacitor current squared times ESR. Fes =(lnerus) (ESR) 15) Example: Viy = 20V-30V, Iour = 3A, Vout = SV. Worst aseisatVjy =2* Voyr=10V, souse the closest Vy value of 20V; 520-5) hems -24 =) \ (20y ‘The input capacitor must be rated ata working voltage of 30V minimum and 1.34 ripple current. Ripple current ratings vary with maximum ambient temperature, so check data sheets carefully. 1.34 RMS (16) Itisimportantto locate the input capacitor very closetothe LT1074 and to use short leads (racial) when the DC input voltage is less than 12V. Spikes as high as 2V/inch of lead length will appear at the regulator input. i these spikes drop below ~7V, the regulator will exhibit anomalous behavior. See “Viy Pin’ in the Pin Descriptions section. ‘You may be wondering why no mention has been made of capacitor value. That's because it doesn’t really matter. Larger electrolytic capacitors are purely resistive (or in- ductive) at frequencies above 10kH2, so their bypassing impedance is resistive, and ESR is the controlling factor. For input capacitors used with the LT1074, a unit which meets ripple current ratings will provide adequate “by- passing” regardless of its capacitance value. Units with higher voltage rating will have lower capacitance for the same ripple current rating, but as a general rule, the volume required to meet a given ripple current/ESR is fixed overa wide range of capacitance/voltage rating. Ifthe ‘capacitor chosen for this application has 0.192 ESR, it will have a power loss of 1.3A)* (0.192) = 0.17. AN44-20 LINER0 —_ Application Note 44 — Output Capacitor Inabuck converter, output ripple voltages determined by both the inductor value and the output capacitor, Continuous Mode (€58)oun(1 7 er) yy) (7) Vp-p= Discontinuous Mode 2lour)(Vour) (Vin- Your) TefeVy ‘Note that only the ESR of the output capacitor is used inthe formula. Itis assumed that the capacitor is purely resistive at frequencies above 10kHz. If an inductor value has been ‘chosen, the formula can be rearranged to solve for ESR to aid in selecting a capacitor. Continuous Mode (18) (ve-s)(L)¢) Your) Vw J ESR (MAX) = Vour (- Discontinuous Mode ESR (MAX) = Vp-p. V2lgur (our) Min= Your) Worst case output ripple isat highest input voltage. Ripple is independent of load for continuous mode and propor- tional to the square root of load current for discontinuous mode. Continuous mode with Viyuax) = 25V, Vour = sr=3A, L1 =50qH, t= 100kH2. Required maximum peak-to-peak output ripple is 25m\. (19) ‘A10V capacitor with this ESR would have to be several thousand microfarads, and therefore faily large. Tradeoffs which could be made include; A Paralleling several capacitors it component height is more critical than board area B. Increasing inductance. This can be done at no increase insizeita more expensive core (molypermalioy, etc.) is used . Adding an output filter. This is often the best solution because the additional components are fairly low cost, and their additional space is minimized by being able to “size down" the main Land C. See the “Output Filter" section Although ripple current is not usually @ problem with buck converter output capacitors because the current is pre- filtered by the inductor, a quick check should be done beforeatinal capacitors chosen—especially ifthe capaci- tor has been “downsized” to take advantage of an addi- tional output filter. RMS ripple current into the output capacitor is Continuous Mode (20) oo 029(va1-“a) lants = _ us = a From the previous example: 5) 0.28 © 1% laws = =0,23ARMS (21) four) This ripple current is low enough to not bea problem, but that could change if the inductor was reduced by two or three to one and the output capacitor was minimized by adding an output filter. The calculations for discontinuous mode RMS ripple ‘current were considered too complicated for this discus sion, but a conservative value would be 1.5 to 2 times ‘output current. AN44-21——_— Application Note 44 To minimize output ripple, the output terminals of the regulator should be connected directly to the capacitor leads so that the diode (D1) and inductor currents do not circulate in output leads. Efficiency Allthe losses except those created by the inductor and the output filter are covered in this buck regulator section. The example used was a 5V, 3A output with 25V input. Calcu- lated losses were: switch, 1.24W; diode, 1.2; switching times, 0.89W; supply current, 0.21W; and input capacitor, 0.47W, Output capacitor losses were negligible . The sum. of all these losses is 3.7 1W. Inductor loss is covered in a special section of this Application Note. Assume for this application that inductor copper lossis 0.3Wand coreloss is 0.15W, Total regulator loss is 4.16W. Efficiency is __lour * Vout (GA)(5v) Tour *Vour +5, (BA)(BV) +476 8% (22) When considering improvements or tradeotfs of particu- lar loss terms, keep in mind that a change in any one term will be attenuated by efficiency squared. For instance, it switch loss were reduced by 0.3W, this is 2% of the 15W ‘output power, but only @ 2(0.8)? = 1.28% improvement in efficiency. Output Divider Rt and R2 set DC output voltage. R2 is normally set at 2.21kQ2 (a standard 1% value) to match the LT1074 reference voltage of 2.21V, giving a divider current of ‘mA. R1 is then calculated from _2(Vout Vaer IE R2 = 2,21k0 Bt = (Vou ~ Veet) KO R2 may be scaled in either direction to suit other needs, but an upper limit of 4k&2 is suggested to ensure that the frequency shifting action created by the FB pin votage is ‘maintained under shorted output conditions. RI net) (23) Output Overshoot Switching regulators often exhibit startup overshoot be- cause the 2-pole LC network requires a fairly low unity ‘gain frequency for the feedback loop. The LT1074 has asymmetrical error amplifier slew rate to help reduce ‘overshoot, but it can stil be a problem with certain combinations of L1C1 and C2R3. Overshoot should be checked onall designs by allowing the output to slew from zer0 in a no-load condition with maximum input vottage. This can be done by stepping the input or by pulling the Ve, pin low through a diode connected to a OV-10V square wave, Worst case overshoot can occur on recovery from an ‘output short because the Ve pin must slew from its high clamp state down to=1.3V. This conditionis best checked with the brute force method of shorting and releasing the output sMexcessive output overshoot is found, the procedure for reducing it to a tolerable level sto first try increasing the compensation resistor. The error amplifier output must slew negative rapidly to control overshoot andits slew rate is limited by the compensation capacitor. The compensa- tion resistor, however, allows the amplifier output to “step” downward very rapidly before slewing limitations begin. The size ofthis step is =(1.1mA)(Ro). If Rc can be increased to 3kQ, the Vo pin can respond very quickly to control output overshoot. ifloop stability cannot be maintained with Ro=3kO2, there are several other solutions. Increasing the size of the ‘output capacitor will reduce short-circult-recovery over- shoot by limiting output rise time. Reducing current limit vill also help for the same reason. Reducing the compen- sation capacitor below 0.05pF helps because the Vc pin can then slew an appreciable amount during the allowable overshoot time. ‘The “final solution’ to output overshoot isto clamp the Vo pin so that it does not have to slew as far to shut off the ‘output. The Ve pin voltage in normal operation is known fairly precisely because it is made independent of every- thing except output voltage by the internal multiplier, AN44-22 AT ERNour Ve Voltage = 26 + Be (2a) (= Vee of internal transistor = 0.65V - 2mVI°C Toallow for transient conditions and circuit tolerances, a slightly different expression is used to calculate clamp level for the Vo pin Your , Vinans) Vejen) =20+—5 + o2v (25) For a 5V output with Viyagax) = 30V, 5,30 Vojocawe) =2(0.65)+ 55+ 55+0.2=2.35V (26) There are several ways to clamp the Vo pin as shown in Figure 14. The simplest way isto just add a clamp Zener (03), The problemis finding alow voltage Zener which does Notleak badly below the knee, Maximum Zener leakage over ‘temperature should be 40uA @ Vo =26 + Vour/ 20V. One solution isto use an LM385-2.5V micropower reference diode where the calculated clamp level does not exceed 25V. Figure 14. Clamping the Ve Pin A second clamp scheme is to use a voltage divider and diode (D4). Vx must be some quasi-regulated source which does not collapse with regulator output voltage. A third technique can be used for outputs up to 20V. It ‘clamps the V¢ pin to the feedback pin with two diodes, D1 and2. These are small signal nongold doped-diodeswith a forward voltage that matches 9. The reason for this is start-up. Vis essentially clamped to ground through the Output divider when Voyy = 0. It must be allowed to rise Application Note 44 sufficiently to ensure start-up. The feedback pin wil sit at about0.5V with Voyr=0, because ofthe combined current ‘rom the feedback pin and Vp pin. The Vo voltage willbe 26 +0.5V + (0.14mA) (Rc). With Rg= 1k, Ve= 1.94, This is plenty to ensure start-up. Overshoot Fixes that Don't Work | know that these things don't work because I tried them. The first is soft start, created by allowing the output current or the Vo voltage to ramp up slowly. The first problems that slowly rising outputallows more time for the Vepin to ramp up well beyond its nominal contral point sottatit has to slew farther down tostop overshoot Ifthe Ve in itsefis ramped slowly, this can control input start- Up overshoot, but it becomes very difficult to guarantee reset the soft start forall conditions ofinputsequencing. Inany case, these techniques do not address the problem of overshoot following overload of the output, because they do not get “reset” by the output ‘Another common practice isto parallel the upper resistor inthe output divider witha capacitor. This again works fine under limited conditions, but it is easily defeated by overload conditions which pul the output slighty below its regulated point long enough for the Ve pin to hit the positive limit (=6V). The added capacitor remains charged and the Ve pin must slew almost 5V to contra overshoot When the overload is released. The resulting overshoot is impressive—and often deadly ‘TAPPED-INDUCTOR BUCK CONVERTER ‘Output current of a buck converter is normally limited to ‘maximum switch current, but this restriction can be altered by tapping the inductor as shown in Figure 15. The ratio of “input” turns to “output” turns is “Nas shown in the schematic. The effec ofthe tap is to lengthen switch “on’ time and therefore draw more power from the input without raising switch current. During switch “on” time, current delivered to the output through LI Is equal to switch current—5.5A maximum for the LT1074. When the switch turns off, inductor current flows only in the output section of L1, labeled "t," through D1 to the ‘output. Energy conservation inthe inductor requires that current increase by the ratio (N+ 1):1. If N = 3, then ‘maximum current delivered to the output during switch off LT NEAR AN44-23Application Note 44 gfe vod “ruse enanceRNG HEHE Figure 15. Tapped-Inductor Buck Converter time Is (3 + 1)(5.5A) = 224, Average load current is in- creased to the weighted average of the 5A and 22A cur- rents, Maximum output current is given by: Sour max) = (27) ot lgy Vo +N) || MW) | las Lvs) | L= Total Inductance Thelast term, (N+ 1)/(1 +N*Voyr/Viy) isthe basie switch current multiplier term, At high input voltages it ap- proachesN +1, andtheoretical output current approaches 1A for N= 3. Forlowerinput voltages the multiplier term approaches unity and no benefit s gained by tapping the inductor. Therefore, when calculating maximum load cur- rent capability, always use the worst case low input voltage. The 0.95 multiplier is throw-in to account for second order effects of leakage inductance, et. OV, N= 3, L =100HH, Vout = SV, 100kHz, Lat Igy = Maximum for LT1074 =5.5A, Vout’ =5V +0.55V=5.55V, Vi =20V-2V = 18V Nour nax) = (28) (18-5.55)(1+3) Vsu ~4\(195)(..18 3(5.55) sory(om(o+ 5) 88 (o(o[eras)ilM ae | =0.95,5.5~0.4] 2.08] = 10.084 Duty cycle of the tapped-inductor converter is equal to; 0.95/5.5— (29) ‘Average and peak diode currents are our (Min'= Your’) lye) (30) (Use Maximum Vy) Nour (NVour' + Vin) loypean) = ~ (Use Minimum) AN44-24 AT NeeAverage switch current during switch on time is tour Your +n) ta = eR @» (Use Minimum Vj) Diode peak reverse voltage is Min Vour. TEN (Use Maximum Viy) (32) Vpi(PeaK. ‘Switch reverse voltage is Vow =Vin+ Vo + Vspine (33) (Use Maximum Vy) Vz= Reverse breakdown of D2 (30V) Vepue = Nartow (<100ns) spike created by rapid switch tumottand the stray wiring inductance of €3,02, 03, andthe 1074 Vy and switch pins. This voltage spike is aprox- mately lgy/2 vot per inch of total lead length Using parameters from the maximum output current example, with Vinay) = 30V, lgyr = 8A DC @ Vjy=20V= — 64% (34) S558 (8) (28-5.55) _ 'oave) = pg =87A _(8)(9+5.55+18) Sou) Vi 2 = TTT asa Note that this is the average switch current during “on” time, It must be multiplied by duty cycle and switch voltage drop to obtain switch power loss. Total loss also includes switch fall time (ise time losses are minimal due to leakage inductance in L1). Application Note 44 Powrcu = (Isw) (DC) |1.8V + (0.4) (Igw)] + (35) (Vin * Vz) (sw) (1) (tsw) 50ns+3nse ley = (8.85) 0.64)(1.8+ (0.1) 8.85)]= (20-+30) 3.85) 10°) (62ns) 5.3W+119W =6.5W 30+3.5 Voypene) = 2-39 11.254 (36) Vow = 20+ 90 5:35 yt =64v * This assumes 2" of lead length Snubber The tapped-inductor converter requires a snubber (D2 and 03) toclip off negative switching spikes created by the leakage inductance of Lt. Thisinductance (L,) isthe value measured between the tap and the switch (N) terminal with the tap shorted to the output terminal. Theoretically, luctance wll be zero because the shorted ohms back to any other terminals. In practice, even with bifilar winding techniques, there is 21% leakage inductance compared to total inductance. This is =1.2uH for the PE-65282. L; is modeled as a separate induotance in series with the “N” section input, which does not couple to the rest of the inductor. This gives rise to a negative spike at the switch pin at switch tumoff. 02 and 03 clip this spike to prevent switch damage, but 02 dissipates a significant amount of power. This power is equal to the energy stored in L, at switch turnoff, (E = (Isw)? # Ly/2) multiplied by switching fre- quency and a multiplier term which is dependent on the difference between D2 voltage and the normal reverse voltage swing at the inductor input. 37) AT nee AN44-25Application Note 44 For this example; Poo= (3.857 (12x i) (10°| 1 30 —_30__|_aw 2 (ates) (38) Output Ripple Voltage Output ripple on a tapped-inductor converter is higher than a simple buck converter because a square wave of ‘current is superimposed on the normal triangular current fed to the output. Peak-to-peak ripple current delivered to the output is: tp-o= Nour (Ne Vour-+Vin)(N) | (+8) (Vin~ Vout) Vint) Ww auf Nour 9) (Use Minimum in) A conservative approximation of RMS ripple current is, ‘one-half of peak-to-peak current. Output ripple voltage is simply the ESR of the output capacitor multiplied times Ip-p. In this example, with ESR = 0.030 Ip-p= (40) (8)G+5-+20)(3) (t+ 3) 2 ciuaa 20(1+3) —(108)(10°4) lays =8.7A Vp ~p=(0.08) (114) =340mv This high value of ripple current and voltage requires some thought about the output capacitor. To avoid an exces sively large capacitor, several smaller units are paralleled to achieve a combined 5.7A ripple current rating. The ripple voltage is stil a problem for many applications. However, to reduce ripple voltage to 5OmV would require an ESR of less than 0.005W—an impractical value. in- stead, an output fteris added which attenuates ripple by more than 20:1 Input Capacitor The input bypass capacitor is selected by ripple current rating. It is assumed that all the converter input ripple current is supplied by the input capacitor. RMS input cipple current is approximately I Ve uy =a die ate) (ge) 49 jour (Use Minimum Vy) (8)(5.5) 8 ~aaaea (35 The input capacitor value in microtaradsis not particularly important since itis purely resistive at 100k#z; but it must be rated atthe required ripple current and maximum input voltage. Radial lead types should be used to minimize lead inductance. POSITIVE TO NEGATIVE CONVERTER ‘The LT1074 can be used to convert positive voltages to negative if the sum of input and output voltage is greater ‘than the 8V minimum supply voltage specification, andthe minimum positive supply is 4.75V. Figure 16 shows the LT1074 used to generate negative 5V. The ground pin of the device is connected tothe negative output. This allows the feedback divider, R3 and R4, to be connected in the normal fashion. If the ground pin were tied to ground, ‘some sort of level shiftand inversion would be required to ‘generate the proper feedback signal Positive to negative converters have a “right half plane zero” inthe transfer function which makes them particu- larly hard to frequency stabilize, especially with low input voltage. R1, R2, and C4 have been added to the basic design solely to quarantee loop stability at low input voltage. They may be omitted for Viy> 10V, or VivVour > 2.1 plus R2 sin parallel with RS for DC output voltage calculations. Use the following guidelines for these resistors: AN44-26 ATERApplication Note 44 Ven Plows] See T™“ ~™ am br -woroRoueta LOWER CURRENT AX ALLOWED FR LOWER OP G1 = MEM UPLICZOMRME + oyeR cuRaENT RATING MAY BE USED FORLOWERO Us eactaawesnas #52” “Ae, AOL ARE USED FOR LOO FREQUENCY COMPENSATION. UT RY MORE tui mca voeo WT caLcWaTon FOR OUTPUT VOLTAGE GEA WALES, Bn 237 9) 38 ua QUT CURRENT OF OETERMINED BY SEMAN APT VOLTAGE 4 ken MOMMA MPT OLTAGE WL LLOW MUCH GER bunrur comeNs Figure 16. Positive to Negative Converter t Maal 37 (Inka) 00 =o (42) R2=R3 (365) (Use absolute value for Vour) IRI and R2 are omitted Peak switch current for continuous mode is R4=2.21k ‘ew(peaK) = (43) R3= |Vour! -2.21 (inka) four (V'+ Your) , (Mini) (Your) A+12V to -5V converter would have Ra = 2.21k and R3 274k. Mw 2foL (Mw + Vour') To calculate maximum output current for a given maxi- Recommended compensation components would be C3. mum switch current (Iy) this can be rearranged as; = 0.005uF in parallel with a series RC of O.1,.F and 10. lout aux) = (44) The converter works by charging L1 through the input ; vottage when the LT1074 switch on.” During switon Ww =(ha) (Ri) f,__(Vn) Your) “off” time, the inductor current is diverted through D1 to. Viv Vour’ | 2feL (Vi-+ Vour) the negative output: For continuous mode operation, duty . cyele ofthe switch is (Use Minimum Vi) AT nee AN44-27Application Note 44 Note that an extra term (Iy # Ry) has been added. This is to account for the series resistance (R,) of the inductor, which may becomea significant lossat low input voltages. Maximum output current is. dependent upon input and output voltage, unlike the buck converter which will supply essentially 2 constant output current. The circuit shown will supply over 4A at Vin = 30V, but only 1.3A at Vip =5V. The louryrax) equation does notinclude second order loss ‘terms such as capacitor ripple current, switch rise and fall time, core loss, and output iter. These factors may reduce maximum output current by up to 10% at low input and or output voltages. Figure 17 shows loyrwax) versus input voltage for various output voltages. It assumes a ‘25,H inductor for Voyr =~5V, 50H for Voyr=—12V, and 100uH for Voyr = -25V. 1 cuRRENT neu vr Figure 17. Maximum Output Curent of Positive o Negative Conve If absolute minimum circuit size is required and load ‘currents are not too high, discontinuous mode can be used. Minimum inductance required fora specified loadis; Discontinuous Mode (45) 2lout (our) (Iu)et There is @ maximum load current that can be supplied in discontinuous mode, Above this current, the formula for Ly is invalid. Maximum load current in discontinuous mode is; Gan onus =)(2) (WAN) Win Vour 2 J (46) (Use Minimum iy) Example: Voyr = 5V, | (OOkHz, Load Current = 0.5A. Diode Forward Voltage = 0.5V, giving Voyy' = 55. Vin=4.7Vt05.3V, Assume Viy guy) =4.7V-2.3V=2.4V. 24 \(5 Your) -(eaa)(2)- 7A (a7) The required load current of 0.5A is less than the maxi- mum of 0.76A, so discontinuous can be used. 2(0.5)(5.5) (5) (10 } To ensure full load current with production variations of frequency and inductance, 3uH should be used. The formula for minimum inductance assumes a high peak current in the inductor (=5A). fthe minimum induc- tanceis used, the inductor must be specified to handle the high peak current without saturating, The high ripple Current will also cause relatively high core loss and output ripple voltage, so some judgment must be used in mini- mizing the inductor size. See the “Inductor Selection” section for more details. (48) To calculate peak inductor and switch current in discon- tinuous mode, use lout Vout Let "peak (49) Input Capacitor C3 is used to absorb the large square wave switching currents drawn by positive to negative converters. It must have low ESR to handle the RMS ripple current and to avoid input voltage “dips” during switch on time, espe- cially with 5V inputs. Capacitance value is not particularly important if ripple current and operating voltage require- ‘ments are met. RMS ripple current in the capacitor is AN44-28 AT NERApplication Note 44 Continuous Mode (60) Vour' Nw (Use Minimum Viy) Saws =lour y Discontinuous Mode* 1) -+0A7m? +1-m Mw — m= yeL flour Your hw “This formula isa test for calculator students Examples: A continuous mode design with Viy = 12V, Vout = ~8V, lout = 14, Vout’ = 5.5, and Vin’ = 10V. vas =(0)) 52 o.7eanus (ea Now change to a discontinuous design with the same conditions and L = 5H, f = 400kHz m= \(2)(t010°4(105)(1)(6.5) 0.98 (62) 3 /1.35 (1- 0.165) ins = 2668) is ; sO \0.17(0.38)? +1-0.93, 96A RMS Notice that discontinuous mode saves on inductor size, but may require a a larger input capacitor to handle the ripple current increase. The 30% increases in ripple cur- rent generates 70% more heating in the capacitor ESR, Output Capacitor ‘The inductor on a positive to negative converter does not operate as after. It simply acts as an energy storage device so that energy can be transferred from input to output ‘Therefore, al fitering is done by the output capacitor, and t must have adequate ripple current rating and low ESR Output ripple voltage for continuous mode will contain three cistinct components; a “spike” on switch transitions which {is equal othe rate of rise/fall of switch current multiplied by the effective series inductance (ESL) ofthe output capacitor, 2 square wave proportional to load current and capacitor ESR, and a triangular component dependent on inductor valueandESR. The spikes are very narrow, typicallylessthan 100ns, and often “disappear” in the parasitic filter created by the inductance of PC board traces between the converter and {oad combined with theload bypass capacitors. One must be extremely careful when looking at these spikes with an oscilloscope. The magnetic fields created by currents tran- sitions in converter wiring will generate “spikes” on the screen even wien they do not exist atthe converter output See the “Oscilloscope Techniques” section for details, The peak-to-peak sum of square wave and triangular output ripple voltage is Vp-p= (64) egp|lour(¥ni+Your), (Vour)(Mn) _] wi 2 (Vour + Md (f)(L) (Use Minimum Vi) Example: Viy = SV, Vout 25uH, louriax) = 1A, = 100ktH2. Assume Viy' = 2.8V, Vour = 5.8V, and ESR = 0.052. Vo~ (55) o5| 02-855), (6.942.8) ] ze 2(6.5+2.8)(10°)(26 x 10-9} | =17omv For some applications ths rather high ripple voltage may be acceptable, but more commonly it will be necessary to reduce ripple vottage to SOmV or less. This may be impractical to achieve simply by reducing ESR, so an output filter (L2, C4) is shown, The fiter components are relatively small and low cost, both of which areadditionally offset by possible reduction inthe size ofthe main output capacitor C1. See the “Output Filters” section for details AT Ae AN44-29Application Note 44 C1 must be chosen for ripple current as weil as ESR. Ripple current into the output capacitor is given by; Continuous Mode (56) = trays = tour OUT Vw Discontinuous Mode — tour), 067( oor , 2laut 7 Vout to) (oP D Where Ip =Peak InductorCurrent 2lgut (Your) Let For the Continuous Mode example = (0a) (25 tras =(14) 5 37 ARMS (58) With Discontinuous Mode using a 3A inductor, with lour = 0.5A tex | POSES) 69) \foxso News _ (0. 67(4.28- os) (0.70.5) a 03), Ti Y (osyazy (azay a = 1.098 RMS Notice that output capacitor ripple currentis over twice the DC output current in this discontinuous example, The smaller inductor size obtained by discontinuous mode may be somewhat offset by the larger capacitors required ‘on input and output to meet ripple current conditions. Efficiency Efficiency for this positive to negative converter can be quite high or larger input and output voltages (>90%), but can be much lower for low input voltages. Losses are summarized below for a continuous mode design. Dis- Continuous losses are much more difficult to express analytically, but wil typically be 1.2 to 1.3 times higher than in continuous mode. Conduction toss in switch = Pew (DC) Pow (D0)= (60) Coan avs 0:2 our) (Your + i‘) [ eel Transient switch loss = Pgwy (AC) 2 | Vour'+ Min} 2(t: f) Py (ac) Lou" out + Wn) 2Utswil) gy Min Where ts = S0ns + 3ns (Vour' + Vin). The 111074 quiescent current generates a loss called PsuppLy 7mA.+ mA (Vou Psupauy= (Nin moa meet (62) Catch diode loss = Poy = ‘Where V; (lour)(Vi) Forward Voltage of D1 at a current equal to; Nour (Vour' + Vin‘ Vin’ Capacitor losses can be found by calculating RMS ripple ‘current and multiplying by capacitor ESR. Inductor losses are the sum of copper (wire) loss and core loss rent a (63) Vw! = Inductor Copper Resistance cone can be calculated ifthe inductor core material is known, See the "Inductor Selection” section Example: Vj =12V, Voyr=—12V, loyr= 1.58, f= 100kHz Let L1=50uH, with Ry = 0.040 Assume ESR of inputand ‘output capacitor is 0.0602. Viy'= 12V-2V = 10V, Vout" 12V+0.8V= 125V. AN44-30 AT NERPow (DC)= (64) oie fg ALEGRE Paw (AC) (1.5) (12.54 10.5 (12.5+10)]) CeO [aso am OT G8) Poy =({.5)(0.5)=0.75W 2.5 x Irwsqeurcae)= 15 2:2 = .60ARMS Pes = (1-68)? (0.05) ~ 0.1407 "ays(ourPur CaP) = wr _ (12-8) + (12-8)(10) 534 ams \ OY Troy 2.510) oy =(1.68)° (0.05) = 0.140 2 oy =0.0{ SUES) 9 as Assume Pooae =0.20 Jour Your, Tour Vour + EPcoss Piogs = 4+ 0.86 +0.23+0.75+0.14+ 0.14+0.46 + 0.2=6.78W (1.5)(12) Eeeney= aa) a8" Efficiency = NEGATIVE BOOST CONVERTER Note: Ai! equations in this section use the absolute value of Vy and Vout. The LT1074 can be configured as a negative boost con- verter (Figure 18) by tying the ground pin to the negative output. This allows the regulator to operate from input voltages as low as 4.75 ifthe regulated output is at least 8V. Ri and R2 set the output voltage asin a conventional connection, with R1 selected from y Ri UL Veer (65) Application Note 44 Boost converters have a “right half plane zero” in the forward part of the signal path and for this reason, Lt is ‘eptto alow value to maximize the “zero” frequency. With larger values for L1, it becomes dificult to stabilize the regulator, especialy at ow input voltages. IfVjy >10V, L4 ‘an be increased to 50H ‘There are two important characteristics of boost convert- ers to keepin mind Firs, the input voltage cannot exceed the output voltage, or D1 will simply pull the output unregulated high. Second, the output cannot be pulled below the input, or D1 will drag down the input supply. For this reason, boost converters are not normally considered short circuit protected unless some form of fusing is provided. Even with fuses, there is the possibilty of damage to D1 it the input supply can deliver very large surge currents Boost converters require switch currents which can be much greater than output load current. Peak switch cur- rent is given by Va (Mour'= Ww) ‘our * Your wi For the circuit in Figure 18, with Vin = SV, (Vin' =3V), Vour' =15.5V, with an output load of 0.54; (66) "sw pen a four ‘sy etaK) = (67) (0.54)(15.5) |__3(15.5-3) gry 3 2 (25uH)(10°) 15.5) This formula can be rearranged to yield maximum load current for a given maximum switch current (ly) +n’ _ (iw P Your'= Vw’ Vour') ~ abet 4 lour(max) (68) Your" For ly =5.5A, this equation yields 0.828 with Viy = 4.5V, 1.84 with Viy = BV, and 3.1A for Vin = 12V, ‘The explanation for switch current which is much higher than output current is that current is delivered to the output only during switch “off” time. With low input voltages, the switch is “on” a high percentage of the total switching cycle and current is delivered to the output only ‘a small percent ofthe time. Switch duty eycle is given by LT NEAR AN44-31Application Note 44 oars + tpi = sorreNONG OwAPUT VLA Figure 18. Negative Boost Converter Mw! (69) For Viy = 5V, Vour= 18V, Vin' = 3V, Vour' = 15.5V and; 85-8 91% (70) 5.5 Peak inductor current is equal to peak switch current. ‘Average inductor current in continuous mode is equal to lout * Your ‘eave = (74 ‘A.5A toad requires 2.6A inductor current for Viy = 5V. ‘Along with high switch currents, Keepin mind that boost converters draw DC input currents higher than the output toad current. Average input current to the converter is, (lour)(Vour) I (00) =e (72) With lout = 0.54, and Viy = SV (Viy' = 3V) (73) This formula does not take into account secondary loss terms such as the inductor, output capacitor, etc., soit is somewhat optimistic. Actual input current may be closer to3A. Be sure the input supply is capable of providing the required boost converter input current. Output Diode ‘The averagecurrent through D1 is equalto output current, but the peak pulse currents equal to peak switch current, which can be many times output current. D1 should be conservatively rated at 2 to 3 times output current. Output Capacitor The output capacitor of a boost converter has high RMS Fipple current so this is often the deciding factor in the selection of C1. RMS ripple current is approximately !Nour' a (74) (75) C1 must have a ripple current rating of 1A RMS. Its actual capacitance value isnot critical. ESR of the capacitor will determine output ripple voltage. AN44-32 AT ERApplication Note 44 Output Ripple Boost converters tend to have high output ripple because of ‘the high pulse currents delivered to the output capacitor. lot «Vout, Yn (Your'~Yw) Vp-p=ESR (76) Vw 2b ef eVour This formula assumes continuous mode operation, and it ignores the inductance of C1. In actual operation, C1 inductance will allow output “spikes” which should be removed with an output fier. The filter can be as simple as several inches of output wire of trace and a small solid tantalum capacitor if only the spikes need to be removed A filter inductor is required if significant reduction of the fundamental is needed. See the “Output Filter” section For the circuit in Figure 18, wth Igy = 0.5A, Vin=5V; and ‘an output capacitor ESR of 0.050 Vp-p= mm ool O2K055), _ 90055-2) | 3” 2(6x10-®108)A5.5)| Input Capacitor Boost converters are more benign with respect to input current pulsing than buck o inverting converters. The input currents a DC level witha triangular ripple superim- posed. RMS value of input current ripple is Vii (Your'= i) 7 BL feVoyr (78) ‘sic Notice that ripple current is independent of load current assuming that load current is high enough to keep the converter in continuous mode. For the converter in Figure 18, with Vin = BV ) ‘peas = —— 3(155-3) __g soanms 3 (25 10°F) (10°) (15.5) (79) C3 may be chosen on a ripple current basis to minimize size. Larger values willallow less conducted EMI backinto the input supply. INDUCTOR SELECTION There are five main criteria in selecting an inductor for switching regulators. First, and most important, is the actual inductance value. if inductance is too low, output ower wil be restricted. Too much inductance results in large physical size and poor transient response. Second, the inductor must be capable of handling both RMS and peak currents which may be significantly higher than load current. Peak currents ae limited by core saturation, with resultant loss of inductance. RMS currents are limited by heating effects in the winding, Also important is peak-to- peak current which determines heating effects in the core itself. Third, the physical size or weight oftheinductor may be important in many applications. Fourth, power losses inthe inductor can significantly affect regulator efficiency, especialy at higher switching frequencies. Last, the price of inductors is very dependent on particular construction techniques and core materials, which impact overal size, efficiency, mountabilty, EMI, and form factor. There may bea significant cost penalty, fo instance if more expensive core materials are needed in “minimum size” applications. The issues of price and size become particularly compli- cated at higher frequencies. High frequencies are used to reduce component size, and indeed, the inductance values required scale inversely with frequency. The problem with a scaled-down high frequency inductor is that total core loss increases slightly with frequency for constant ripple curtent, and this poweris nowdissipated inasmaller core, so temperature rise and efficiency can limit size reduc- tions. Also, the smaller corehas ess room for wire, so wire losses may increase. The only solution to this problem is to ind abetter core material. Common fow cost inductors Use powdered iron cores, wiich are very low cost. These cores exhibit modest losses at 40kHz with atypical flux density of 300 gauss. At 100kH2, core lasses can become tunaoceptably high at these flux densities. Reducing flux density requires a larger core, canceling part ofthe advan- tage gained in reducing inductance at the higher frequency. Molypermalloy, “high flux,” “Kool Me" (Magnetics, Inc), and ferrite cores have considerably lower coreloss, and can be used at 100kH2 and above with higher flux density, but these cores are expensive. The basic lesson here is that attentionto inductor selection is very important to minimize costs and achieve desired goals of size and eficienoy. LT HER AN44-33Application Note 44 ———_ AA special equation has been developed in the following section which shows that for a given core material, total core loss is dependent almost totally on frequency and ‘inductance value, not physical size or shape. The formula is arranged to solve for the inductance required to achieve a given core loss. It shows that, in atypical 100kHz buck converter, inductance has to be increased by a factor of three over the minimum required, if a low cost powdered iron care is used. “Standard” switching regulator inductors are toroids. Although this shape is hardest to wind, it offers excellent utilization of the core, and more importantly, has low EMI fringing fields. Rod or drum shaped inductors have very high fringing fields and are not recommended except possibly for secondary output filters. Inductors made with “E-E" or“E-C" splitcores are easy to wind on the separate bobbin, but tend to be much taller than toroids and more expensive. “Pot” cores reverse the position of windingand core—the core surrounds the winding. These cores offer the best EMI shielding, but tend to be bulky and more expensive. Also, temperature rise is higher because of the enclosed winding, Special low profile split cores (TOK “EPC,” etc.) are now offered in a wide range of sizes. Although not as efficient as EC cores in terms of watts! volume, these cores are attractive for restricted height applications, The best way to select an inductor isto first calculate the limitations on its minimum value, These limitations are imposed by a maximum allowed switch current, maxi- mum allowable efficiency loss, and the necessity to operate in continuous versus discontinuous mode. (See discussion elsewhere of the consequences re- fated to these two modes.) After the minimum value has been established, calculations are done to establish the operating conditions of the inductor; i, RMS current, peak-to-peak ripple current, and peak current. With this information, next select an “off the shelf" inductor which meets all the calculated requirements, or is reasonably close, Then ascertain the physical size and price of the selected inductor. Ifitfits in the allowed “budget” of space, height, and cost, you can then give some consideration to increasing the inductance to gain better efficiency, lower output ripple, lower input ripple, more output power, or some combination of these. If the selected inductor is Physically oo large, there are several possibilities; select adifferent core shape, different core material, (which will require recalculating the minimum inductance based on etticiency loss), a higher operating frequency, of consider a custom wound inductor which is optimized for the application. Keepin mind when attempting toshoehorn an inductor into the smallest possible space that output overload conditions may cause currents to increaseto the point of inductor failure, The major failure mode to con- sider is winding insulation failure due to high winding temperature. IC failure caused by lass of inductance due to core saturation of core temperature is not usually a problem because the LT1074 has pulse-by-pulse current Jimiting which is effective even with drastically lowered inductance The following equations solve for minimum inductance based on the assumption af limited peak switch current (lw). ‘Minimum inductance to Achieve a Required Output Power h Buck Mode Discontinuous, Inyr =“ Use Maximum Vy (80) 2 lout * Vour ( Vin’ ~ Your } yan = (iu)? (Vai) Buck Mode Continuous, four < I, Use Maximum Vy (81) Your (Vin = Your) Lain ei Vin C= TOUr) InveringMode Discontinuous, yt Fy - a = Boat ra (OE ow) i= ¥) «6 [20200-) (econo | VE {oor | ) a Values gen for tappecinauctor yg ae average caren rough Trax S80 ensure the core doesnt saturate and shoul be used entre inductor during seh “ont st erm), andaverape currant wth th entire ndutanee, through ouput sacton dung swt of te (second ter). To Pa to-peak curent used wth te entire inductance to eae core calulate Metin, asa eating losses. ts the equivalent vale the indvcter sna tapped. winding resistance ana AT WER AN44-37Application Note 44 oS ——— _ This inductor must be atleast 35.H, rated at 3A and > 42V us @ 100kH2. It must not saturate at a peak current of 3.64. inverting mode with Viy=4.7-5.3V, Vout =-5V, 100kH2, maximum inductor ioss = 0.3W. Let ZV, Nour = 5.5V. Maximum output current for discontinuous mode equation 82) is 0.82A, souse continu- ous mode. Lain = (96) 2.7068) x105 + 2x105(6.5+2.7)" (R25 Now calculate minimum inductance from core loss. As- sume core loss is 1/2 of total inductor loss, (Pc .0.15W). =4.6uH (From Tate 2) = 2-2)(69) 6 095 (97) 2(27+5.5) ‘Assuming Micrometals type #26 material, 2 1.3 10-*)(75}(0.908) aw Desfoses nH (98) mH 2-4 (0.1979. (108)°" 288 ‘This values over fivetimes the minimum of 4.6, Perhaps a higher core loss is acceptable, Here's how to do a quick check. If we assume total efficiency is ~60% (+ 10 - conversion with a 5V inputs inefficient dueto switch loss), then input power is equal to output power divided by 0.6 = 8.33W. If we double core loss from 0.18W to 0.3W, efficiency wil be SWi(8.33 + 0.15)=59%. Thisis only a1% drop in ficiency. Acore oss of O.3W allows inductance to drop to 12uH, assuming that the 12uH inductor will tolerate the core loss plus winding loss without overheat- ing. Inductor currents are te(Fom rave) (A) 2.758) og a be (weress),_27)68) _ aga (i2x10-8)(10°)(27+538) “ eS MICROPOWER SHUTDOWN ‘The LT1074 will go into a micropower shutdown mode, with Isuppry = 150), when the shutdown pin is held below 0.3V. This can be accomplished with an open collector TTL gate, a CMOS gate, or a discrete NPN or NMOS device, as shown in Figure 19, orev onan 4 Figure 19. Shutdown ‘The basic requirementis thatthe pull down device can sink ‘50 of current at a worst case threshold of 0.1V. This requirementis easly met with any open collector TTL gate (not Schattky clamped), a CMOS gate, or discrete device. The sink requirements are more stringent f Ri and R2are added for under voltage lockout. Sink capability must be ‘OWA + Viy/R1 at the worst case threshold of 0.1V. The ‘suggested value for R2 is Sk to minimize the effect of shutdown pin bias current. This sets the current through Ri and R2 at ~ 500uA at the undervoltage lockout point. tan input voltage of twice the lockout point, Rt current will be slightly over 1mA, so the pull down davice must sink this current down to 0.1V. AVN2222 or equivalent is suggested for these conditions. Start-Up Time Delay Adding a capacitor to the shutdown pin will generate a delayed start-up. The internal current averages to about 25nA during the delay period, so delay time will be =(2.45V)/(C » 25yA), #50%, If more accurate time outis required, Ri can be added to swamp out te effects of the interval current, buta larger capacitor is needed, and time out is dependent on input voltage Some thought must be given to reset of the timing capacitor. Ifa resistor to ground is used, it must be large enough to not drastically affect timing, so reset time is typically ten times longer than time delay. A diode to Vin AN44-38 AT WERApplication Note 44 oo resets quickly, but if Viy does not drop to near zero, time delay will be shortened when power is recycled immediately. 5-PIN CURRENT LIMIT ‘Sometimes it may be desirable to current limit the 5-pin version of the LT1074. This is particularly helpful where ‘maximum load current is significantly less than the 6.54, internal current limit, and the inductor and/or catch diode are minimum size to save space. Short circuit conditions put maximum stress on these components. ‘The circuit in Figure 20 uses a small toroidal inductor slipped over one lead of the catch diode to sense diode ‘current. Diode current during switch “off time is almost directly proportional to output current, and L2 can gener- ate an accurate limit signal without affecting regulator efficiency. Total power lost in the limit circuitry is less than 0.1W. L2 has 100 turns. It therefore delivers 1/100 times diode current to Rg when D1 conducts. The voltage across Rg required to current limit the LT1074 is equal to the voltage across R4 plus the forward biased emitter base voltage Q1 (=600mV @25°C). The voltage across Rd is set at 1.1V by R3, which is connected to the output. Current limit is set by selecting Rs; Ralx + Vae ‘uu 100 y= ULE 0.4m 3 (100) “covTRoncs ure 20. Low Loss External Current Limit vom Vee = Forward biased emitter base voltage of O1 @ Ig = S00WA (=600mV), N= Turns on L2. Jum = Desired output current limit. yy should be set 1.25 times maximum lead current to allow for Variations in Vee and component tolerances. ‘The circuit in Figure 20 is intended to supply 3A maximum load current, sol, was set at 3.75A. Nominal Viyis 25V, giving j= $406 . 40-9 = 227x109 apt 04x10 0 3) hee (470) (2 2x107)+08 yo 3.75/10 - 2.27103 This circuit has “foldback” current limit, meaning that short circuit current is lower than the current limit at full output voltage. This is the result of using the output voltage to generate part ofthe current limittrip level. Short circuit current will be approximately 45% of peak current limit, minimizing temperature rise in D1 (10%) 5, C3, and D3 allow separate frequency compensation of the current limit loop. 03is reversed biased during normal operation, For higher output voltages, scale R3 and RS to provide approximately the same currents. ‘SOFT START Soft start is a means for ramping switch currents during the turn on of a switching regulator. The reasons for doing this include surge protection for the input supply, protec- tion of switching elements, and prevention of output AT WHER AN44-39Application Note 44 ‘overshoot. Linear Technology switching regulators have built-in switch protection that eliminates concern over device failure, but some input supplies may not tolerate the inrush current of a switching regulator. The problem ‘occurs with current limited input supplies or those with relatively high source resistance. These supplies can “Tatch” ina low voltage state where the current drawn by the switching regulator in much higher than the normal input current. This is shown by the general formula for switching regulator input current and input resistance; Wo) Fo HIE) “ ban ae NAF aarae 20) E = Efficiency (=07-0.9) These formulas show that input current is proportional to the reciprocal of input voltage, so that if input voltage ‘drops by 3:1, input current increases by 3:1. An input supply Wich rises slowly will “see” a much heavier ‘current load during its low voltage state. This can activate ‘current imit inthe input supply and “latch” it permanently ina low voltage condition. By instituting a soft startin the switching regulator which is slower than the input supply rise time, regulator input current is held low until the input supply has a chance to reach full voltage. ‘The formula for regulator input resistance shows thatit is negative and decreasesas the square of input voltage, The maximum allowed positive source resistance to avoid latch-up is given by; ranch 4(Vour) (k lout) The formula shows that a +12V to ~12V converter with 80% efficiency and 1A load must have a source resistance tess than 2.42. This may sound like much ado about nothing, because an input supply designed to deliver 1A ‘would not normally have such a high source resistance, but a sudden output load surge or a dip in the source voltage might trigger a permanent overload condition LowVinandhigh outputloadrequirelowersourceresistance. (103) ay Figure 21. Soft Start Using yy Pin InFigure 21,2 generatesa soft stat of switching current by forcing the pin toramp up slowly. Current out ofthe Ii pinis=300uA, so the time for the L71074 to reach tull switch current (Via =5¥) is =(1.6 x 104)(C). To ensure low switch current until Viy has reached full value, an approximate value for C2 is 2=(10-*)(T) (104) T = Time for input voltage to rise to within 10% of final value. (C2 must be reset to zero volts whenever the input voltage {90@s low. Aninternalresetis provided when the shutdown pin is used to generate undervoltage lockout. The “undervottage” state resets C2. If lockout is not used, R3 should be added to reset C2. For full current limit, R3 should be 30kQ. If reduced current limit is desired, R3's value is set by desired current limit. See the “Current Limit” section. {f the only reason for adding sot stat is to prevent input supply latchup, a better alternative may be undervoltage lockout (UVLO). This prevents the regulator from drawing input current until the input voltage reaches a preset Voltage. The advantage of UVLO is that it is a true DC function and cannot be defeated by a slow rising input, short reset times, momentary output shorts, etc OUTPUT FILTERS When converter output ripple voltage must be less than =2% of output voltage, itis usvally better to add an output filter (Figure 22) than to simply “brute force" the ripple by using very large output capacitors. The output filter con- sists of a small inductor (=2uH-10uH) and a second AN44-40 STR‘output capacitor, usually 50,F-200uF. The inductor must be rated at full load current. Its core material is not important (core loss is negligible) except that core mate- rial will determine the size and shape of the inductor. ‘Series resistance should be lowenough toavoid unwanted efficiency loss. This can be estimated from; (8)(Vour) ae + Cour? (108) cwkton Figure 22. Output Fitter is overall efficiency and AE is the loss in efficiency allocatedtothe filter. Both are expressed asa ratio, i... 2% AE = 0.02, and 80% E= 0.8, Toobtain the required component values for the fiter, one ‘must assume a value for inductance or capacitor ESR, then calculate the remaining value. Actual capacitance in tmicrofarads is of secondary importance because it is assumed that the capacitor will be basically resistive at ripple frequencies. One consideration on filter capacitor value is the load transient response of the converter. A ‘small output filter capacitor (high ESR) will alow the ‘output to “bounce” excessively if large amplitude load transients occur. When these load transients are ex- pected, the size of the output fiter capacitor must be increased to meet transient requirements rather than just ripple limits. In this situation, the main output capacitor can be reduced to simply meet ripple current require- ments. The complete design should be checked for tran- sient response with full expected load change. It the capacitor is selected first, the inductor value can be found from ripple attenuation requirements. Buck converter with triangular ripple into filter = ESAVATIN) a (108) Application Note 44 Allother converters with essentially rectangular ripple into filter (ESA) (ATTN) (0G) (1~DC) awe ESR = Filter capacitor series resistance. ATTN = Rippleattenuation required, asa ratio of peak-to- peak ripple IN to peak-to-peak ripple OUT. DC = Duty cycle of converter. (If unknown, use worst case of 05). (107) Example: A100kH2 buck converter with 150mVp-p ripple Which must be reduced to 20mV. ATTN = 150/20 = 755. Assume a fiter capacitor with ESR = 0.302 _(0.3)(7.5) (105) uh (108) Example: A 100kH2 positive to negative converter with output ripple of 250mVp-p which must be reduced to 30mY. Assume duty cycle has been calculated at 30% = 0.3, and ESR offer capacitor is 0.20 (0.2)(250/30)(0.3)(1-0.3) 10° ifthe inductors known, the equations can be rearranged to solve for capacitor ESR. Buck Converter at(L) AAW L Sul (109) (110) ESR = Square WaveRipplein; fel (aTIN (00) (06) ‘The output filter wil affect ioad regulation iit the regulator feedback oop. Series resistance of the fter inductor will add directly to the closed loop output resis- tance of the converter. This closed loop resistance is ‘ypicallyinthe range of0,00202-0.0102, soattiter inductor resistance of 0.020 may represent a significant loss in load regulation. One solution is to move the fiter “inside” the feedback loop by moving the sense pointstothe output of the filter. This should be avoided i possible because the added phase shitt of the filter can cause dificulties in AT HER AN44-41Application Note 44 stabilizing the converter. Buck converters will tolerate an output filter inside the feedback loop by simply reducing the loop unity gain frequency. Positive to negative con \erters and boost converters have “right half plane 2er Which makes them very sensitive to addtional phase shift To avoid stability problems, one should frst determine if the load regulation degradation caused by a filter is really a problem. Most digital and analog “chips” in use today tolerate modest changes in supply voltage with ite or no effect on performance. When the sense resistor is tied to the output ofthe fiter, “fix” for stability problems is to connect a capacitor from the input of the filter to a tap on the feedback divider as shown in Figure 23. This acts as a “feedforward” path around the fier. The minimum size of Cx will be deter- ‘mined by the filter response, but should bein the range of OwFABF x could theoretically be connected directly to the FB pin, ‘but this should be done only ifthe peak-to-peak ripple on the main output capacitor is less than 75mVp-p. ‘A word about “measured fiter output ripple. The true ripple voltage should contain only the fundamental of the switching frequency because higher harmonics and “spikes” are very heavily attenuated. If the ripple as measured on an oscilloscope is abnormally high or con- tains high frequencies, the measurement technique is probably at fault. See the “Oscilloscope Techniques” section. san oe cameron ® 907 a Figure 23. Feedforward when Output Filter is Inside Feedback Loop INPUT FILTERS Most switching regulators draw power from the input ‘supply with rectangular or triangular current pulses. (The exception isa boost converter where the inductor acts as a filter for input current). These current pulses are ab- sorbed primarily by the input bypass capacitor which is located right at the regulator input. Significant ripple ‘current can stil flow in the input lines, however, if the impedance of the source, including the inductance of supply lines, is low. This ripple current may cause un- wanted ripple voltage on the input supply or may cause EMMI inthe form of magnetic radiation from supply ines. In these cases, an input fiter may be required. The filter consists of an inductor in series with the input supply combined with the input capacitor of the converter, as shown in Figure 24 Figure 24, Input Filter To calculate a value for L requires knowledge of what ripple current is.allowed in the supply line. This isnormally ‘an unknown parameter, so much hand waving may go on in search of a value. Assuming that a value has been arrived at, Lis found from; SSR (0C) (1-DC) a ESR = Effective series resistance of input capacitor. C= Converter duty cyte. unknown, use 5s worstcase Icow=Peak-to-peak ripple current drawn by teconverter, assuming continuous mode. For buck converters, Icon lour. Positive to negative converters have Icon = lout (Vour' + Vin)". Tapped-inductor Icon = lour (N # Vour’ + Vin')/{Vin'(1+N)]. cak-to-peak ripple allowed in supply lines. ‘Damping” resistor which may be required to prevent instabilities in the converter AN44-42 ATRApplication Note 44 Example: A 100kH2 buck converter with Vour = 5V, Jour =4A, Vin =20V, (DC = 0.25). Input capacitor ESR is 0.059. Itis desired to reduce supply tne ripple current to 100mA(p-p). Assume Py isnot needed (= eo) (0.05)(0.25) (10.25) 2) 3,754 50.1 10 ( 9} For further deals on input fies, including the possible need for a damping resistor (Ry), see the “input Filters” section in Application Note 19. (12) ‘The current rating of the input inductor must be a mini- mum of; Your tour) (Mn) (Use Minimurn Vin) For this example; 5) (4 eae’, nm Efficiency or overload considerations may dictate an in- ductor with higher current rating to minimize copper losses. Core losses will usually be negligible. he ‘Amps. (113) OSCILLOSCOPE TECHNIQUES Switching regulators are a perfect test bed for poor oscil- loscope techniques. A “scope” can li in many ways and they all show up in a switching regulator because of the combination of fast and slow signals, coupled with both large and very small amplitudes. The following Rogue's Gallery will hopefully help the reader avoid many hours of frustration (and eliminate some embarrassing phone calls to the author) Ground Loops Good safety practice requires most instruments to have their “ground” system tied to a “third” (green) wire in the power cord. This unfortunately results in current flow through oscilloscope probe ground leads (shield) when other instruments Source or sink current to the device under test. Figure 25 details this effect. A generator is driving a SV signal into 5002 on the bread- board, resulting in a 100mA current. The return path for this current divides between the ground from the signal generator (typically the shield on a BNC cable) and the secondary ground “loop” created by the oscilloscope probe ground clip (shield), and the two “third wire” connections on the signal generator and oscilloscope. in weauaron Ghose sr SLSR oessreaca| ES ve Tear Figure 25. Ground Loop Errors AT nee AN44-43Application Note 44 ‘his case, it was assumed that 20mA flows in the parasitic {ground loop. Ifthe oscilloscope ground lead has a resis tance of 0.20, the screen will show a 4mV “bogus” signal. The problem gets much worse for higher currents, and fast signal edges where the inductance of the scope probe shield is important DC ground loops can be eliminated by disconnecting the third wire on the oscilloscope (ts called a cheater plug, and my lawyers will not let me recommend it!) or by the use of an isolation transformer in the oscillo- scope power connection. Another source of circulating current in the probe shield wire isa second connection between a signal source and the scope. Atypical example sa trigger signal connection between the generator trigger output and the scope exter- nal trigger input. This is most often a BNC cable with its ‘own grounded shield connection. This forms a second path forsignal groundreturn current, wth thescope probe shield completing the path. My solution is to use a BNC cable which has had its shield intentionally broken. The trigger signal may be less than perfect, but the scope will not care. Mark the cable to prevent normal use! Rule #1: Before making any low level measurements, touch the scope probe “tip” tothe probe ground clip with the lip connected to the desired breadboard ground. The “scope” should indicate flatine. Any signal displayed is a (ground loop le ‘Miscompensated Scope Probe 10X scope probes must be “compensated” to adjust AC attenuation so it precisely matches the 10:1 DC attenua- tion of the probe. If this is not done correctly, low fre- quency signals will be distorted and high frequency signals will have the wrong amplitude. In switching regulator applications, a “miscompensated” probe may show “impossible” waveforms. A typical example is the switching node of an LT1074 buck converter. This node swings positive to level 1.5V-2V befowthe input voltage, and negative to one diode drop below ground. A 10X probe with too little AC attenuation could show the node swing- ing above the supply, and so far negative that the diode forward voltage appears to be many volts instead of the expected 0.5V. Remember that at these frequencies (100kti2), the wave shape looks right because the probe acts purely capacitive, so the wrong amplitude may not be immediately obvious, Rule #2: Check 10X scope probe compensation before being embarrassed by a savvy tech Ground “Clip” Pickup Oscilloscope probes are most often used with a short ‘ground “lead” with an alligator clip onthe end. This ground wire is @ remarkably good antenna. It picks up local magnetic fields and displays them in full color on the oscilloscope screen. Switching regulators generate lots of magnetic fields. Switch wires, diodes, capacitor and inductor leads, even “DC” supply lines can radiate signiti- ‘cant magnetic fields because of the high currents and fast rise/fall times encountered, The test for ground clip prob- lemsis to touch the probe tip to the aligator clip, withthe clip connected to the regulator ground point. Any trace seen on the screen is caused either by circulating currents ina ground loop, or by antenna action ofthe ground clip. ‘The fix for ground clip “pickup” isto throw the clip wire away and replace it with a special soldered-in probe terminator which can be obtained from the probe manu facturer. The plastic probe tip cover is pulled off to reveal the naked coaxial metal tube shield which extends to the small needle tip. This tube slips into the terminator to complete the groundconnection. This technique will alow you fo measure milivotts of output ripple on a switching regulator even in the presence of high magnetic fields. Rule #3: Don't make any low level measurements on a switching regulator using a standard ground clip lead. an official terminator is not available, solder a solid bare hookup wire to the desired ground point and wrap it around the exposed probe coaxial tube with absolute ‘minimum distance between the ground pointand the tube. Position the ground point so thatthe probe needle tip can touch the desired test point. Wires Are Not Shorts ‘A common error in probing switching regulators is to assume that the voltage anywhere on a wire path Is the ‘same. A typical example isthe ripple voltage measured at the output of aswitching regulator. the regulator delivers ‘square waves of current tothe output capacitor, a positive AN44-44 AT WERApplication Note 44 to negative converter for instance, the current rise/ fall time will be approximately 10%A/sec. This di/dt will generate =2V per inch “spikes” in the lead induc- tance of the output capacitor. The output (load) traces of the regulator should connect directly tothe through-hole Points where the radial-lead output capacitor leads are soldered in. The oscilloscope probe tip terminator (no ground clips, please) must be tied in directly at he base of the capacitor also The 2V/in. number can cause significant measurement errors even at high evel points. When the input voltage to a switching regulators measured across the input bypass capacitor, the spikes seen may be only a few tenths of a volt. If that capacitor is several inches away from the 71074 though, the spikes “seen” by the regulator may be ‘many volts. Tis can cause problems, especialy at alow input voltage. Probing the “wrong” point onthe input wire might mask these spikes, Rule #4: I you want to know what the voltage is ona high AC current signal path, define exactly which component voltage you are measuring and connect the probe termi- nator directly across that component. As an example, if your circuit has a snubber to protect against switch over~ voltage, connect the probe terminator directly to the IC switch terminals. Inductance in the leads connecting the switch to the snubber may cause the switch voltage to be ‘many volts higher than the snubber voltage. EMI SUPPRESSION Electromagnetic interference (EMI) is a fact of life with switching regulators. Consideration of its effects should occur early in the design so that the electrical, physical, ‘and monetary implications of any required filtering or shielding are understood and accounted for. EMI takes ‘wo basic forms; “conducted,” which travels down input ‘and output wiring, and “radiated,” which takes the form of electric and magnetic fields, Conducted EMI occurs on input ines because switching regulators draw current from their input supply in pulses, either square wave, of triangular, or a combination of these. This pulsating current can create bothersome ripple voltage on the input supply and it can radiate from input lines to surrounding lines or circuitry. Conducted EM! on the output of a switching regulator is usually limited to the voltage ripple on the output nodes. Ripple frequencies from buck regulators consist almost entirely of the fundamental switching frequency, whereas boost and inverting regulator outputs contain much higher frequency harmonics if no additional filtering is used. Electric fields are generated by the fast rise and fall times ofthe switch node in the regulator. EMI from this source is usually of secondary concern and can be minimized by keeping all connections to this node as short as possible and by keeping this node “internal” to the switching regulator circuitry sothat surrounding components act as shield. The primary source of electri field problems within the regulator itsef is coupling between the switching node ‘and the feedback pin, The switching node has atypical slew rate of 0.8 x 10°V/sec., and the impedance at the feedback pin is typically 1.2kA. Just 1PF coupling be- tween these pins will generate 1V spikes atthe feedback pin, cteating erratic switching waveforms. Avoid long {races onthe feedback pin by locating the feedback resis- tors immediately adjacent to the pin. When coupling to switching node cannot be avoided, a 1000pF capacitor from the LT1074 ground pin to the feedback pin will Prevent most pickup problems, Magnetic fields are more troublesome because they are generated by avarety of components, including the input ‘and output capacitors, catch diode, snubber networks, the inductor, the LT1074 itself, and many of the wires con- necting these components. While these fields do not usvally cause regulator problems, they can create prob- lems for surrounding circuitry, especially with low level signals such as disc drives, data acquisition, communica- tion, or video processing. The following guidelines wil be helpful in minimizing magnetic field problems. 1. Use inductors or transformers with good EMI! charac- teristics such as toroids or pot cores. The worst offenders from an EMI standpoint are “rod” inductors. Think of them as cannon barrels firing magnetic flux lines in every direction. Their only application in switchers should be in the output filter where ripple current is very low. AT EAR AN44-45Application Note 44 2. Route all traces carrying high ripple current over a ‘ground plane to minimize radiated fields. This includes the catch diode leads, input and output capacitor leads, snub ber leads, inductor leads, LT1074 input and switch pin {eads, and input power leads. Keep these leads short and the components close to the ground plane. 3. Keep sensitive low level circuitry as faraway as possible, and use field-canceling tricks such as twisted-pairdiffer- ential lines, 4. In ritical applications, add a “spike Killer" bead on the catch diode to suppress high harmonics. These beads will prevent very high di/dt signals, but will also make the diode appear to turn “on” slowly. This can create higher transient switch voltages at switch turn-off, so switch waveforms should be checked carefully. ‘5, Add an input fiter if radiation from input lines could be a problem. Just a few uM in the input fine will allow the regulator input capacitor to swallow nearly all the ripple current created atthe regulator input ‘TROUBLESHOOTING HINTS Low Efficiency The major contributors here are switch and diode toss. Theseare readily calculable. if etficiencyis abnormally ow atter factoring in these effects, zero in on the inductor. Core or copper loss may be the problem, Remember that inductor current may be much higher than output current in some topologies. A very handy substitution tool is a 500xH inductor wound with heavy wire on a large molypermalloy core. 100,H and 200uH taps are helpful This inductor can be substituted for suspect units when inductor losses are suspected. If you read this App Note, you will know that a large core is used not to reduce core loss, but to allow enough room for large wire that elimi- nates copper loss. lfinductor tosses are not the problem, check all the nickel and dime effects such as quiescent current and capacitor loss to see if the sum is no longer negligible. Alternating Switch Timing Switch “on” time may alternate from cycle to cycle if excess switching frequency ripple appears on the Vc pin. This can occur naturally because of high ESR in the output ‘capacitor or because of pickup on the FB pin or the Vc pn. ‘Asimple checkis to puta 30009F capacitor from Vc pin to the ground pin close to the IC. If the erratic switching Improves ors cured, excess Vc pin ripple is the problem. Isolate it by connecting the capacitor from FB to ground pin, I this also makes the problem disappear, Vo pin pickups eliminated, and FB pickup isthelikely culprit. The feedback resistors shouldbe located close tothe IC sothat connections to the FB pin are short and routed away from switching nodes. ASOOpF capacitor from FB to ground pin ‘will usually be sufficient if pickup cannot be eliminated, Occasionally, excess output rippleis the problem. Thiscan be checked by paralleling the output capacitor with a second unit, A 1000pF-3000pF capacitor on Vo can often be used to stop erratic switching caused by high output ripple, but be sure the ripple current rating ofthe output capacitor is adequate! Input Supply Won't Come Up ‘Switching regulators have negative input resistance at OC. Therefore, they draw high currentat lowVy This can atch input supplies low. See “Soft Star” section for details. ‘Switching Frequency is Low in Current Limit This is normal, See “Frequency Shitting at the Feedback Pin’ in the Pin Description section, 1c Blows Up! Like the LT1070 before it, the only thing that can destroy the LT1074 or LT1076 is excess switch voltage. (1 am ignoring obvious stutt like voltage reversal or wiring errors). Start-up surges can sometimes cause momentary large ‘switch voltages, so check voltages carefully with an oscil- loscope. Read the section on oscilloscope techniques. AN44-46 LT WERIC Runs Hot ‘A common mistake is to assume that heat sinks are no longer needed with a switching design. This is often true for small load currents, but as load current climbs above 1A, switch loss may increase to the point where a heat sink is needed. A 70-220 package has a thermal resistance of 50°C/W with no heatsink. ASV, 3A output (15W) with 10% switch loss, wil dissipate over 1.5Win the IC. This means a 75°C temperature rise, or 100°C case temperature at room ambient. This is normally referred to as hot! Asmall heatsink solves the problem. Simply soldering the T0-220 tab to an enlarged copper pad on the PC board will reduce thermal resistance to ~25°O/W. High Output Ripple or Noise Spikes First read “Oscillescope Techniques” section to avoid possible embarrassment, then check ESR of the output capacitor. Remember that fast (<100ns) spikes will be greatly attenuated by parasitic supply line inductance and load capacitance even if supply lines are only afew inches long Application Note 44 Poor Load or Line Regulation Check inthis order: 1. Secondary output fiter DC resistance if itis outside the loop. 2. Ground loop error in oscilloscope. 3. Improper connection of output divider resis tors to current carrying tines, 4. Excess output ripple. The LT1074 can peak detect ripple voltages on the FB pin if they exceed 50mVp-p. ‘See “Reference Shitt with Ripple Voltage" graph in Typical Performance Characteristics section, ‘500kH2-5MHz Oscillations, Especially at Light Load This is discontinuous mode ringing and is quite normal and harmless. See buck converter waveform description {or more details AT WEAR AN44-47Application Note 44 AN44-48 ATEnt ] \R Application Note 45 TECHNOLOGY June1991 Measurement and Control Circuit Collection Diapers and Designs on the Night shift din Willian Introduction During my wife's pregnancy | wondered what it would really be lke when the baby was finally born. Before that time, there just wasn’t much mothering and fathering to do. AS a consolation, we busied ourselves watching the baby’s heartbeat (Figure 1) on a thrown-together fetal heart monitor (see References). Wie wy Figure 1. Michael's Fetal Heartbeat 41/2 Months into Pregnancy When Michael was born things got noticeably busier in a hurry. My wife and | split up the evening duties. ! got the night shift, 2 am to 7 am. After a few weeks, Michael and | got the hang of it and things began to go (relatively) smoothly. The two of us had mastered feedings, naps, crying jags, bottles, diapers and such and we began looking around for something todo. I decided to introduce Michael to the glories of late night circuit hacking. | frst learned about wee hours circuit design at MIT in the 1970s. There was a subculture there that loaded up on pizza, soft drinks, and junk food, took itall into the lab, and Closed the door until fong after daylight. |wasan enthusi- astic convert Michael and | changed the rules just abit, We loaded up on ‘formula, diapers, and bottles and went into the lb, The circuits in this collection represent our efforts, which stopped when he (more or less) began sleeping through the night. Most of the breadboarding occurred between feedings, with design reviews and discussions during feedings. As such, the circuits are annotated with the ‘number of feedings required for their completion; e.g. a “3-bottle circuit" took three feedings. The circuit's degree of dificulty, and Michael's degree of cooperation, com- bined to determine the bottle rating, which is duly re- corded in each figure. Low Noise and Drift Chopped Bipolar Amplifier Figure 2's circuit combines the low noise of an LT1028 witha chopper based carrier modulation scheme toachieve an extraordinarily low noise, low drift DC amplifier. DC driftand noise performance exceed any currently available monolithic amplifier. Offset is inside 1uV, with drift less than 0.05nV/*C. Noise in a 10Hz bandwidth is less than 40nV, far below monolithic chopper stabilized amplifiers, Bias current, set by the bipolar LT1028 input, is about 25nA. These specifications suit demanding transducer signal conditioning situations such as high resolution scales and magnetic search coils The 74C04 inverters form a simple two-phase square wave clock running at about 350H2, The oscillator pro- vides complementary drive to $1 and 2, causing AY to ‘see a chopped version of the input voltage. At amplifies this AC signal. A1's square wave output is synchronously demodulated by S3 and $4. Because these switches are synchronously driven with the input chopper, proper amplitude and polarity information is presented to A2, the DC output amplifier. This stageintegrates the square wave into a DC voltage, providing the output. The output is divided down (R2 and Rt) and fed back to the input chopper where it serves as a zero signal reference. Gain, inthis case 1000, is set by the R1-R2 ratio. Because At is AG coupled, its OC offset and drit do not affect overall circuit offset, resulting in the extremely ow offset and drift noted. AT WEAR AN45-1Application Note 45 oo Rs ren tcorsa «38 ‘iro “Tez owo ~~ Figure 3, a noise plot of the amplifier in a 0.1Hz-10H2 bandwidth, shows less than 40nV of peak-to-peak noise. At and the 6002 resistance of $1-S2 contribute about equally to form this noise. When using this amplifier itis, important to realize that A1's bias current flowing through the input source impedance causes additional noise. In (general, to maintain low noise performance, source resis- tance should be kept below 50082. Fortunately, transduc- ers such as strain gauge bridges, RTDs, and magnetic detectors are well below this figure. nen ail Pe 0.1Hz-10Hz Bandwidh is Less Than 400 with 0.05,°C D Low Noise and Drift Chopped FET Amplifier Figure 4's circuit combines the low drift of a chopper stabilized amplifier witha pairof lov noise FETS. Theresult isanamplfierwith0.05uV/°C dri, offset within, 500A bias current, and 200nV noise in a.1H2-10Hz bandwidth, The noise performance is especially noteworthy; it is almost eight times better than monolithic chopper stabi- ‘zed ampiiiers. FET pair Q1 differentially feeds A2 to form a simple low noise op amp. Feedback, provided by R1 and R2, sets closed loop gain (in this case 1000) in the usual fashion. ‘Although 01 has extraordinarily lw noise characteristics, its 15mV offset and 25.V/°C dritt are poor. A1, a chopper stabilized amplifier, corrects these deficiencies. It does this by measuring the difference between the amplifier's inputs and adjusting Q1A's channel current to minimize the difference. Q1’s skewed drain values ensure that A1 will be able to capture the offset. At supplies whatever current is required into Q1A’s channel to force offset within 5,V. Additionally, A1's low bias current does not appreciably add to the overall SOpA amplifier bias current. ‘As shown, the amplifier is set up for a non-inverting gain of 1000, although other gains and inverting operation are AN45-2 LT NEARApplication Note 45 iil Possible. Figure 5 isa plot of noise measured in a 0.1Hz- 410Hz bandwidth. The performance obtained is almost an ‘order of magnitude better than any monolithic chopper stabilized amplifier, while retaining low offset and drift. M's Low Orit are Retained, but Noise is Almost Ten Times Be ‘A2's optional overcompensation can be used (capacitor to ground) to optimize damping for low closed loop gains, Stabilized, Wideband Cable Driving Amplifier with Low Input Capacitance Figure 6's amplifier has over 20MHz of small signal ‘bandwidth driving 100mA loads, capacitance or cable, oPnomaL ek coweennon igure 4. Chopper Stabilized FET Pair Combines Low Bias, Otset and Dri with 200HV Noise Input capacitance is below 1.5pF and bias current about 100pA. The output is fully protected. These features make this amplifier ideal as an ATE pin amplifier, video A-Dinput buffer, or cable river. Theamplifieraiso permits wideband probing when oscilloscope probe loading is not tolerable. The overall amplifier is composed of a low input capaci- tance FET, two LT1010 buffers, and a discrete gain stage. ‘AB acts as a DC restoration loop. The 330 resistors sense At’s operating current, biasing 03 and Q4. These devices furnish complementary voltage gain toA2, which provides the circuit's output. Feedback is from A2's output to A's ‘output, which is a low impedance point. This “current mode" feedback permits fixed bandwidth over a wide range of closed loop gains. This contrasts with normal feedback schemes where bandwidth degrades as closed loop gain increases. ‘A3's stabilizing loop compensates large offsets in the signal path, which are dominated by mismatch in 03 and 04. A3 measures the DC difference between theamplifier’s input and output and biases the signal path to correct for offset. Correction is implemented by controlling 1s channel current via Q2. The channel current sets Q1's Ves, allowing A3 to control overall circuit offset. The 9k-tk feedback divider feeding A3 is selected to equal the gain ‘aio of the circuit, in this case 10, STW AN45-3Application Note 45 The feedback scheme makes A1's output look like the negative input of the amplifier, with closed loop gain setby the ratio of the 4700 and 510 resistors. The outstanding feature of this connection is that the bandwidth becomes relatively independent of closed loop gain over a reason- able range, For this circuit, small signal bandwidth ex- ceeds 20MH2 over gains f 1020. Theloopisquitestable, and the 10pF value at A2’s input provides good damping over a wide range of gains, Figure 7 shows large signal performance at a gain of 10 driving 10 feet of cable. A fast input pulse (trace A) produces the output shown (trace 8). Response is quick and ciean with no slew residue or poor dynamics Voltage Programmable, Ground Referred Current Source Precise, voltage programmable, ground referred current sources are usually complexand require trimming, Figure 8's simple, powerful configuration produces output cur= rent in strict accordance with the sign and magnitude of the control voltage. Dynamic response is well controlled, Figure 7. Wideband Amplitir’s Resporse Diving A 10 Foot Cable and no trimming is required, The circuit's accuracy and stability are almost entirely dependent upon resistor R. A, biased by Vy, drives current through R (in this case 102) and the lo2d. Instrumentation amplifier A2, operat ing at a gain of 100, senses across R. A2's output closes loop backto At, Because A1’sloop forces. fixed voltage AN45-4 LI WeeApplication Note 45 ‘he across R, the current through the load is constant. The 10k-0.05,F combination sets A's rolloff, and the circuit is stable Assuming an erroriess component for R, the circuit's initial erroris dominated by A2's 0.05% gain specification and its Sppm/*C temperature coefficient. High grade film or wirewound resistors will maintain this level of performance. Figure 9 shows dynamic response for a full scale input step. Trace A is the voltage control input while trace B shows the output current. Response is clean, with no slew residue or aberrations. 5V Powered, Fully Floating 4mA to 20mA Current Loop Transmitter 4mA to 20mA current loop transmitters are frequently required in industrial process control. Often, because of uncertain or dangerous common mode voltages, it is desirable that the generated 4mA to 20mA current be completely galvanically isolated from the transmitter’s input. Figure 10's circuit does this while operating from a single 5V supply. AA2's positive input assumes a bias dependent upon the input and the 4mA trim setting. Under these conditions A2's output heads positive, turning on 1 and Q2. 02's collector drives T1's primary, which is chopped by 0 and 4, Complementary chopper drive comes from the 74C74 flip-flop outputs, with oscilator 1 setting a 25KHz clock ona 2.00 Figure 9. Current Source Dynamics are Clean, with No Slew esidue or Aberrations rate. T1's output, producing voltage step-up, is rectified, filtered, and applied to the load. A3 senses load current across the 16¢2 shunt and drives T2's center tap. 09 and (010, receiving complementary drive picked-off from T1's secondary, modulate T2's DC center tap voltage. T2's secondary receives this information, with flip-flop driven 06-07 demodulating it back to DC at T2's center tap. T2's center tap voltageis fed A2, completinganisolated control (oop. Changes in the circuits input voltage cause this loop to adjust the load current accordingly. Conversely, load resistance changes have no effect, because the’ loop forces whatever voltage is necessary to maintain a con- stant 162 shunt vottage. Because T1 can supply up to 50V, load current remains fixed over load resistance swings trom 02 to 25000. Power supply shifts are similarly rejected by the loop, and the transformer modu- tation-demodulation scheme permits 0.05% accuracy and stability over temperature and a 250V common mode range. Greater common mode voltages are possible with increased transformer breakdown ratings. Several subtleties aid circuit performance, 12-3 and 14-15 provide drive delays to 06 and Q7. These delays approxi- mate the delay through T! to modulator pair 09/010, This helps the four transistors switch simultaneously, aiding modulator-demodulator accuracy. Zener connected O5 ensures thatT1 produces enough voltage to power ABand 09/010, even when the load is 00. 08, similarly zener Connected, clamps gate drive to 09 and 010, improving modulator linearity by preventing excessive gate drive variations over operating conditions. The diodes in A3's a LINEAR AN45-5Application Note 45 hy - ores common E - weurcomon Bh eins Denn Oho te SE EIGNEERMG PEI if Figure 10. 5 Powered, Fully Floating 4mA-20mA Current Loop Transmitter output ensure proper loop start-up. They prevent T2’s apply 2.56Vinputand set the 20mA trimmer for 20.00mA center tap from receiving any bias until AB has enough output (0.3200V across the 16¢2 shunt). Repeat this power supply voltage to function normally. To calibrate procedure until both points are fixed. Note that the 2.56V this circuit apply OV input and adjust the 4mA trim for input range is directly compatible with D-A converter 4,00mA output (0.064V across the 160 shunt). Next, outputs, permitting digital control AN45-6 AT WERTransistor AVge Based Thermometer Low cost makes transistors potentially attractive as tem- perature sensors. Almost all transistor-sensed thermom- eter circuits utilize the base-emitter diode voltage shift with temperature as the sensing mechanism. Unfortu- nately, the absolute diode voltage is unpredictable, neces- sitating circuit calibration. Additionally, if the transistor sensor ever requires replacement, the calibration must be repeated. This constraint often negates the transistor sensor's cost and convenience advantages. Figure 11's transistor sensor thermometer overcomes this difficulty, The circuit provides a OV-10V output corre- sponding toa 0°C to 100°C temperature excursion atthe sensor transistor. Accuracy is 41°C. No calibration is required, and any common small signal NPN transistor can serve as the sensor. The circuit is based on the predictable relationship between current and voltage ina transistor Vag junction. At room temperature, the Vp junction diode shifts 58, 16mV per decade of current. The temperature dependence ofthis constant is 0.33%°C, or 198LV/°C. This AVge versus curcent relationship holds, regardless of the Vse diode’s absolute valu. Note: Soe Reterencs trough Season ration conta T oye ru aessi08 oe Application Note 45 The LTC1043 contains switches whose states controled by an on-chip oscillator. The 0.01. capacitor at pin 16 sets oscillator frequency at about 500Hz. Qt operates as a switched value current source, alternating between about 10wAand 100jA traced, Figure 12)as heLTC1043 commutates switch pin 12 and pin 14, The two currents’ exact value is unimportant, so long as their ratio remains constant. Because of this, Q1 requires no reference, although its emitter resistor’s ratio isprecise. Thealternat- ing 10uA-100uA stepped current tothe sensor transistor ‘Ae eowaon 8 einvow sccounen ona 50 Figure 12. Wavetorms forthe AVge Based Thermometer AT NEAR AN45-7Application Note 45 (02) causes the theoretical 59.16mV (25°C) excursion (trace B) to appear across the Vge junction. This signal is ‘coupled toa switched demodulator via C1, which strips off 02's DC bias. L161043 switch pin2 (trace C) sees only the ‘59mV waveform, which is referenced to ground via de- ‘modulator action at pin 5 and pin 6. Pin 5, connected to capacitor C2, sits at pin 2's OC peak value. At amplifies this DC signal, with the LT1004 providing offset so 0°C equals OV. The optional 10k resistor protects against ESD events, which may occur if Q2 is located at the end of a cable Using the components shown, the circuit achieves +1°C accuracy over a sensed 0°C to 100°C range. Substituting randomly selected 2N3904s and 2N2222s for Q2 showed less than 0.4°C spread over 25 devices from various ‘manufactures. Micropower, Cold Junction Compensated Thermocouple-to-Frequency Converter Figure 13 is a complete, digital output, thermocouple signal conditioner. The circuit produces a OkH2-1kHz output in response toa sensed 0° to 100°C temperature coven * week JE i yeeobine aE urs oo tr excursion. Cold junction compensation is included, and accuracy is within 1°C with stable 0.1°C resolution. Addi- tionally, the circuit functions from a single supply, which may range from 4.75V to 10V. Maximum current con- sumption is 360A, ‘The LT1025 provides an appropriately scaled cold junc- tion compensation voltage tothe typeK thermocouple. As a result, the vottage at Schematic point “A” varies from ‘mY to 4.06mV over a sensed 0°C to 100°C range (type K slope is 40,6,V/%). The remaining components form a voltage-to-frequency converter that directly converts this mrllvolt level signal without the usual DC gain stage. At's negative inputs biased by the thermocouple. A1’s output drives a crude V-F converter, comprised of 02, the 74014 inverters, and associated components. Each V-F output pulse causes a fixed quantity of charge to be dispensed into C3 from C2 via the LTC201 based charge pump. C3 integrates the charge packets, producing a voltage at A1's positive input. At's output forces the V-F converter to run atwhateverfrequencyis required to balance the amplifier’s inputs. This feedback action eliminates drift and nonlinearities in he V-F converter as an error term and the LL T1025 PAR AND DRWVE POMT'A Ao-Frequency Converter AN45-8 AT Wee‘output frequency is solely afunction of the DC conditions at At’s inputs, The 0.02uF capacitor forms a dominant respanse pole at 41, stabilizing the loop. Chopper stabi- lized A1’s low Vos offset and drift eliminate offset error in the circuit, despite an output LSB value of only 4.06,V (041°C). Figure 14 details circuit operation. At’s output biases current source Q2, producing a ramp (trace A, Figure 14) across C1. When the ramp crosses It's threshold, the cascaded inverter chain switches, producing complemen- tary outputsat 1 (trace B) and I2 (race). I's RC delayed response (trace D) turns on diode connected Qt, dis- charging C1 and resetting the ramp. The ramp aberrations before the reset are due to transient 11 input currents during switching (near top of ramp). Q1s Vag diode rounding and reverse charge transfer (bottom of ramp) ‘account for the discontinuities during the ramp’s low point cco one 2me0W Figure 14. Wavetorms forthe Thermocoupleto-Frequency Converter ‘Thecomplementary 1-12 outputs clocktheLTC201 switch based charge pump. C2 is alternately charged to the 1004's reference voltage via $1 and $4 and discharged into C3 through $2 and $3. Each time this cycle occurs, C3's voltages forced up (trace E).C3's average voltage is set by the 6.81k-1.5k trimmer resistance across it. At ‘servo controls the repetition rate of the V-F to bring its inputs to the same value, closing a control loop. The 0.02uF capacitor smooths A1's response to DC. To calibrate this circuit, disconnect the thermocouple and drive point “A” with 4 O6mnV. Next, set the 1.5k trimmer for Application Note 45 exactly 1000Hz output. Connect the thermocoupleand the circuit is ready for use. Recalibration is not required if the thermocouple is replaced. Itis worth noting that this circuit can directly digitize any millvolt level signal by deleting the LT1025 thermocouple pair and directly driving point Rel ive Humidity Signal Conditioner Relative humidity isa difficult physical parameter to trans- duce, and most transducers requite fairly complex signal Conditioning circuitry. Figure 15 combines simple cir- cuitry with a capacitively based transducer to achieve (900d results. This circuit, which runs froma SV battery, is accurate within 2% in the 5% to 90% relative humidity range. The sensor specified has a nominal 500pF capacitance at RH = 76%, with a slope of 1.7pF/% RH. The average Voltage across the device must be zero. This prevents deleterious electrochemical migration in the sensor. 1701043 section “A,” driven by an internal oscillator, altemately charges the sensor from a resistively scaled portion ofthe LT1004 reference and dischargesitinto AT'S ‘summing point. Note that the switching is arranged so that sensor related current flows out of At's summing point. ‘The O.1uF series capacitor ensures the sensor sees the required zero average voltage, with the 2MQ2 resistor preventing charge accumulation, which would stop cur- rent flow. The average current out of At’s summing point és balanced by packets of charge delivered by the LTG1043 switched capacitor section °C" in At's feedback loop. The .1yF feedback capacitor gives At an integrator-like re- sponse, and its ouput is DC. As such, changes in sensor ‘capacitance are seen as DC shifts in AY’s output. At responds by raising its output positive to whatever DC Potentials required to maintain its summing point at zero. To allow 0% RH to equal OV, offsetting is required. The signal and feedback terms biasing A1's summing pointare expressed incharge form. Because ofthis, the offset must also be delivered to the summing point as charge, instead fa simple DC current. If this is not done, the circuit will be affected by drift in the LTC1043's intemal oscilator. LTC1043 section “B” serves this function, delivering 11004 referenced offsetting charge to At — LT WEAR AN45-9Application Note 45 secon aseoNse iE Lol Drift terms inthis circuit include the L11004 and th ratio. stability of the sensor and the polystyrene capacitors. These terms are well within the sensor's 2% accuracy specification, and temperature compensation is nat re- quired. To calibrate this circuit, place the sensor in a 5% RH environment and set the “5% RH trim” for SOmV ‘output. Next, place the sensor in a 90% RH environment and set the "90% trim” for 900mV output. Repeat this procedure unti both pointsare fixed. Ifknown RH environ- ments are unavailable, the capacitance versus RH table in, Figure 15 may be utilized, although it applies for an ideal sensor. The capacitor values may be built-up or directly dialed out on a precision variable air capacitor (General Radio #7220) Inexpensive Precision Electronic Barometer Until recently, precision electronically based pressure measurements requited expensive transducers. Capaci- tive and bonded strain gauge based approaches provide unmatched results, but costs are often prohibitive, Addi- tionally, if low power operation is desired, signal condi- tioning for these devices can become complex. Semiconductor based pressure transducers becoming available offer significant improvement over earlier de- vices, Figure 16's circuit utilizes such a device to form a low cost barometer. The LT1027 reference and At forma $F srs crus eestor current source to put precisely 1.5mA through transducer 1, in accordance with the manufacturer's specifications. Instrumentation amplifier A3 takes a diferential gain of 10 from T1’s bridge output. A2 provides additional gain to yield a calibrated output directly in inches of mercury, T1’smanufacturerspecifiesanominal1 15mV at fullscale, although each device is supplied with precise calibration data. This information considerably simplifies calibration, ‘Tocalibratethe circuit, simply adjust the potentiometer at ‘At until the output corresponds to the scale factor sup- plied with the unit Thiscircuit, compared toalong column mercury barometer, tracked ambient pressure variations from 29.75" to 30.32" over three months with only two counts of uncertainty. Additionally, over 50 tura-orvturn-off cycles had no ‘measurable effect. Changes in pressure, particularly rapid ones, correlated quite nicely to changing weather conditions. 1.5V Powered Radiation Detector Figure 17's circuit provides an audible tick” signal each time radiation ora cosmic ray passes through he detector. ‘The LT1073 switching regulator pulses T1. 11 takes gain via its turns ratio and drives a voltage tripler, providing 500V bias to the detector. R1 and R2 provide scaled AN45-10 AT WEApplication Note 45 savin unas feos Hox 8 DerecrOn = TH2LNDEOR ONG AY. ” FH) eve. Pvert tattn beeen LT WEAR AN45-11Application Note 45 feedbackto the LT1073, closing acontrolloop. The 0.01uF lag adds AC hysteresis and the Schottky diode clamps negative going T1 excursions. When radiation ora cosmic ray strikes the detector, impedance drops briefly transferring a quiok negative going spike through the 68pF capacitor. This spike triggers the LT1073's auxiliary gain block, configured hereasa comparator. 1 and 02 provide additional gain to drive the audible beeper. About 10 to 15 cosmic rays per minute are recorded in a normal environment, ‘9ppm Distortion, Quartz Stabilized Oscillator A spectrally pure sine wave oscillator is required for data converter, fiter and audio testing. Figure 18 provides a stable frequency output with extremely low distortion This quartz stabilized 4kH2 oscillator has less than 9ppm (0.009%) aistortion in its 10¥p-p output. Tounderstand circuit operation, temporarily assume A2's ‘outputs grounded. With the crystal removed, At and the 3 power buffer form a non-inverting amplifier with a grounded input. The gain is set by the ratio of the 47k resistor to the 50k potentiometer — opto-solator pair. Inserting the crystal closes a postive feedback path at the crystal’s resonant frequency, and oscillations occur. Ad compares 3's positive peaks with the LT1004 2.5V negative reference. The diode in series with the LT1004 provides temperature compensation for A3's rectifier di- ode. Ad biases the LED portion of the opto-isolator, ie |] mie Figure 18. uartz Stabilized 4kz Oscillator with Sppm Distortion AN45-12 AT ERcontroling the photoresistor’s resistance. This sets loop gain to a value permitting stable amplitude oscillations. The 10uF capacitor stabilizes this amplitude contra loop. ‘A2's function is to eliminate the comman made swing seen by At. This dramatically reduces distortion due to AAt’s common mode rection imitations. A2 does this by servo controling the 560kS2-photocell junction to main- tain its negative input at OV. This action eliminates com- ‘mon mode swing at A, leaving only the desired ditferen- tial signal Q1 and the LTC201 switch form a start-up loop. When ower is first applied oscillations may build very slow Under these conditions A4’s output saturates positive turning on Q1. The LTC201 switch tums on, shunting the 2k62 resistor across the 50KQ potentiometer. Ths raises AA1's loop gain, forcing a rapid build-up of oscilations. When oscillations rise high enough Ad comes out of saturation, and the switch go off andthe loop functions ‘normally, The crcuitis adjusted tor minimum distortion by adjusting ‘the 50k2 potentiometer while monitoring A3's output with a distortion analyzer. Ths trim sets the voltage across the photocell to the optimum value for lowest distortion, The circuit's power supply should be well regulated and bypassed to ensure the distortion figures quoted. After trimming, A3's output (trace A Figure 19) contains less than Sppm (0,0009%) distortion. Residual distortion components (trace B) include noise and second harmonic residue, Oscillation frequency, set by crystal tolerance, is typically within S0ppm with less than 2.5ppm*C drift. ost fa one-one Figure 19. Oscillator Output and its 9ppm Distortion Residue AT NEAR Application Note 45 1.5V Powered Temperature Compensated Crystal Oscillator Many single cell systems require a stable clock source. Crystal oscilators which run from 1.5V are relatively easy to construct. However, if good stability over temperature is required, things become more difficult. Ovenizing the Crystalis one approach, but power consumption is exces- sive, An alternate method provides open loop, frequency correcting bias to the oscillator. The bias value is deter- mined by absolute temperature, In this fashion, the oscilator’s thermal rit, which is repeatable, is corrected. The simplest way to do this is by slightly varying the Crystal's resonance point with a variable shunt or series Jmpedance. Varactor diodes, the capacitance of which varies with reverse voltage, are commonly employed for this purpose. Unfortunately, these diodes require volts of reverse bias to generate significant capacitance shift, making direct 1 5V powered operation impossible. Figure 20 improves the temperature stability of a 1.5V powered crystal oscillator by factor of 20. It does this by slightly tuning the crystal’s resonance as ambient tem- perature varies. Q1 and associated components form a ‘MHz Colpitts oscillator which normally has a tempera- ture coefficient of about 1ppmi/*C. The remainder of the Circuitimplements the temperature correction, The LM134 senses ambient temperature, converting it to a current Which flows through the 30.1k resistor. This resistor's voltages subtracted from a reference potential by At. The stable subtraction voltage is derived from the LT1073's 2i2mv reference via 02 and the 73.2k-27.4k resistors. Feedback from Q2's collector to the LT1073's auxiliary amplifier closes the reference loop, which also powers the Colpits oscilator. The 47uF capacitor frequency compen- sates the loop. AA's output controls the remaining portion ofthe LT1073, which is configured as a voltage step-up switching regulator. Ls high voltage inductive events are rectified and stored in the 47uF output capacitor, resulting in a stepped-up OC potential. This potentials fed backio At, closing a control loop. Because At is biased by the temperature sensitive LM134, the loop’s output varies. with ambient temperature in a controled manner. 03's drop forces the step-up converter toalways un, regardless of the oops required outputvoltage. This permits smooth and continuous varactor bias from Oto 3.9V over a0-70°C AN45-13Application Note 45 feats ae ambient operating environment. This output is applied to the varactor diode in the oscillator circuit. The varactor's capacitance, a function ofits DC bias, thus varies with ambient temperature. This change in capacitance shifts the crystal's resonant frequency, opposing temperature induced crystal drift. For the values given in the circuit and the crystal cut specified, residual oscillator drift is only 0.05ppmv°C. This compares favorably with Ippmv°C drift with no compensation used, The circuit functions from 1.7V down to 1.1V with no specification degradation. Current drain is only 230uA. Applications include portable high-accuracy clocks, survival radios, and secure communications. [oscar wos o os Peure 90,A Precision Voltage-to-Frequency Converter Figure 21 is a micropower voltage-to-frequency con- verter. A OV-5V input produces a OkH2-10KHz output with a linearity of 0.05%. Gain drift is BOppm/>C. Maximum current consumption is only 90,A, almost 30 times lower than currently available V-F converters. To understand circuit operation, assume C1s positive input is slightly below its negative input (C2's output is low). The input voltage causesa positive going ramp atCt'spasitiveinput (trace A Figure 22) C1's outputs low, biasing the CMOS inverter output high. Thisaliows current to flow trom 1's AN45-14 LT WERveo pf = ess 280 seer {mon Deere emitter, through the inverter supply pin to the 100pF capacitor. The 2.2uF capacitor provides high frequency bypass, maintaining low impedanceatQ1’se nitter.Diode ‘connected 06 provides a path to ground. The 100pF unit charges to a voltage that is a function of Q1's emitter potential and Q6's drop. When the ramp at 21's positive input goes high enough, C1’s output goes high (trace B) and the inverter switches fow (trace C). The Schottky clamp prevents CMOS inverter input overdive. This ac- tion pulls current from C1’s positive input caracitor via the Q5-100pF route (trace D). This current removal resets 1's positive input ramp to a potential slightly below ground, forcing C1's output to go low. The 50pF capacitor fummishes AC positive feedback, ensuring that C1's output remains positive long enough for a complete discharge of the 100pF capacitor. The Schottky diode prevents C1's input from being driven outside its negat ve common ‘mode limit. When the SOpF unit's feedback decays, C1 ite ‘Ach eves 0.05% Linearity While Requiring Only 9018 Supply Current again switches low and the entire cycle repeats. The oscilation frequency depends directly on theinputvoltage derived current Figure 22. Micropower V to F Converters Waveforms LT NEAR AN45-15Application Note 45 1's emitter voltage must be carefully contrlled to get low drive. 03 and 04 temperature compensate Q5 and 6 ‘while @2 compensates Q1’s Vee. The two LT1034s are the actual voltage reference and the LM334 current source provides 35uA bias to the stack. The current drive pro- vides excellent supply immunity (better than 40ppm/V) and also aids circuit temperature coefficient. It does this by utilizing the LM334’s 0.3%/°C temperature coefficient to slightly temperature modulate the voltage drop in the 02-04 trio. This correction’s sign and magnitude directly ‘oppose that of the -120ppm/°C, 100eF polystyrene ca- pacitor, aiding overal circuit stability. The Q1 emitter-follower efficiently delivers charge to the 100pF capacitor. Both base and collector current end up in ‘the capacitor. The CMOS inverter provides low loss SPOT reference switching without significant drive losses. The 100pF capacitor draws only small transient currents during its charge and discharge cycles. The S0pF-47k positive feedback combination draws insignificantly small switching currents. Figure 23, aplot of supply current versus operating frequency, reflects the low power design. Atzero frequency, the LT1017's quiescent current and the 35A reference stack bias account for all current drain. There are no other paths for loss. As frequency scales-up, the charge/ discharge cycle of the 100pF capacitor introduces the 1.5yA/KH2 increase shown, content COnsuMPTON uA PeseTe swine Figure 23, Current Consumption vs Frequency forthe Vo F Converter Circuit start-up or overdrive can cause the circuit's AC- coupled teedbackto latch. I this occurs, C1's output goes high. C2, detecting this viathe inverter and the2.7M-0.1F lag, also goes high. This lifts C1's negative input and grounds the positive input with Q7, initiating normal circuit action Because the charge pump is directly coupled to C1's output, response is fast. The output settles within one cycle fora fast input step. To calibrate this circuit, apply 50mV/and select the valueat 1s input fora 100H2 output. Then, apply SV and trim the input potentiometer for @ 10kH2 output. Bipolar (AC) Input V-F Converter No currently available V-F converter will accept bipolar (AC) inputs. Ths feature is desirable in power line moni- toring and other applications. Figure 24's V-F converter accepts +10V inputs, producing a OkH2-10kH2 output Linearity is 0,04%, and temperature coefficient measures about S0ppmy°C. To understand circuit operation, as- ‘sume a bipolar square wave (trace A, Figure 25) is applied tothe input. During the inputs positive phase, A1's output (trace B) swings negative, driving current through C1 via ‘the full wave diode bridge. A1's current causes C1 toramp linearly. Instrumentation amplifier A2, operating ata gain of 10, looks differentially across C1. A2's output (trace C) biases comparator A3's negative input. When A2's output crosses zero, A3 fires (trace D). AC positive feedback to 3's positive input (trace ) “hangs up” A3's output for about 20s. The Q1 level shitter drives ground referred inverters 1 and |2to deliver iphase drive (traces Gand H) to the LTC201 switch, The LTC201, set-up as a charge pump, places C2 across C1 each time the inverters switch, resetting C1 to a lower voltage. The LT1004 reference, along with C2’s value, determines how much charge is removed from C1 each time the charge pump cycles. Thus, each time A2’s output tries to cross zero, C2 is switched across C1, resetting ito. small negative voltage and forcing At to begin rechargingit The frequency of his ‘oscillatory behavior is directly proportional to the input derived current into A1. During the time G1 is ramping toward zero the LTC201 switches C2 across the LT1004, preparing it for the next discharge cycle. The action is the same for negative input excursions (See Figure 25), except that A's output phasingis reversed. A2, looking ifferen- tially across A1’s diode bridge, sees the same signals for positiveinputs and circuit action isidentical. A, detecting AAt’s output polarity, provides a sign bit output (trace). AN45-16 AT NEAApplication Note 45 "9 Pa as oy Ph etme bof ALL sn 15 SUPmLESexcaP acat mine TRS Figure 26, an amplitude expanded version of At and A2's e200 Se outputs, shows detail. Trace A i the input, while trace B andtrace Care and A2’s outputs, respectively. Comple- mentary bias points and ramping action are clearly visible inA1's output, while A2 responds identically for both input ‘hases. A1's output bias points are established by the two Conducting bridge diodes. When the input switches polar- ity, A1 responds immediately and oscillation frequency settles within 1 to 2 cycles of final value. v0 Start-up or overdrive conditions could cause this loop to sou {atch. A start-up mechanism, adapted from oscilloscope trigger circuitry, precludes latch-up.? If C1 charges past Hone som ve the point where C2 can reset it, oop closure ceases. A2's Figure 25, Wavetorms forthe Bipolar Input Vto F Converter —~ Note 2: Se eterences Sands Se AT NEAR AN45-17Application Note 45 output saturates positive, causing A3 to go negative, A3's prolonged negative state, detected by the R1-C3 ‘iter pulls its negative input toward ~15V. When AG's negative input crosses zero, its output changes state and charges R1-C3 positively. A3's input rises above zero, causing output reversal and free-running osclation commences. As in normal mode, the 100pF-33k RC aids transitions. ‘3's oscilations are transmitted to the LTC201 based charge pump via At and the inverters. C2 pumps charge cout of C1, driving the voltage across it toward zero. A2 ‘comes out of positive saturation and heads negative, Within a coos fA on =san0n0 nd Ditferentia! Amplifier Outputs Figure 26, Detail of In Dh wee SELECT 1 ANO oF VALUE eliminating positive bias at A3's input. A3's free-running oscillation stops, and normal loop action begins To calibrate this circuit apply either a -10V or a +10V input and set the 10k trimmer for exactly 10kHz output The low offsets of At and A2 permit operation down toa few hertz with no zero trim required. 1.5V Powered, 350ps Rise Time Pulse Generator Verifying the rise time limit of wideband test equipment set-ups is a difficult task. In particular, the “end-to-end” rise time af oscilloscope-prabe combinations is often required toassure measurementintegrty. Conceptually, pulse generator with rise times substantially faster than the oscilloscope-prabe combination can provide this in- formation, Figure 27's circuit does this, providing a 1ns pulse with rise and fall times inside 350ps. Pulse ampli- tude is 10V with a 500 source impedance. This circu, built into a small box and powered by a 1.5V battery, provides a simple, convenient way to verify the rise time capability of almost any osclloscope-probe combination. ‘The LT1073 switching regulator and associated compo- nents supply the nacessary high voltage. The LT1073 forms a flyback voltage boost regulator. Further voltage step-up is obtained from a diode-capacitor voltage dou bler network. L1 periodically receives charge, and its AN45-18 ATEflyback discharge delivers high voltage events to the doubler network. A portion of the doubler network's OC output is fed back to the L11073 via the Rt, R2 divider, closing a contro! loop. The regulator's 90V output is applied to Qt via the R3-C1 combination. 01, a 40V breakdown device, non-destruc- tively avalanches when G1 charges high enough? The result is a quickly rising, very fast pulse across Rd. C1 discharges, 01's collector voltage falls and breakdown ceases. C1 then recharges until breakdown again occurs. Thisaction causes free-running oscilltionatabout 200kK2. Figure 28 shows the output pulse. A 1GHz sampling oscilloscope (Tektronix 556 with 1$1 sampling plug-in) measures the pulse at 10V high with about a tns base Rise time is 350ps, with fall time also indicating 3509s. The figures may actually be faster, as the 1$1 is specified with a 350ps rise time limit 4 Figure 28. Avalanche Pulse Generator Output Pulse. Waveform Has 350ps Rise and Fall Times. Slightly Under Damped Turn-OMt {Probably Ove to Test Fatue Limitations 1 may require selection to get avalanche behavior. Such behavior, while characteristic of the device specified, is ‘not guaranteed by the manufacturer. A sample of 50 Motorola 2N2369s, spread over a 12 year date code span, yielded 82%. All “good” devices switched in less than 600ps. Ct is selected for a 10V amplitude output. Value spread is typically 2pF to 4pF. Ground plane type construc- tion with high speed layout techniques are essential for good results from this circuit. Current drain from the 1.5V. battery version is about SmA. Note 3: Se Reterence 7. Note 4m sory but 16 LT NEAR test Scope in my house Application Note 45 isn oeraoe Ure en atnt 900.0 ameter For those applications which mustrun from higher voltage inputs, Figure 29 s included. This circuit, which operates from inputs of 4V to 20V, will also power the avalanche stage. Cascoded high voltage transistor Q1 combines with the LT1072 switching regulator to form a high voltage switched mode control loop. The LT1072 pulse width modulates Q1 a its 40kH2clock ate. L1's inductive events are rectified and stored in the 2uF output capacitor. The 1M2-12k0 divider provides feedback to the LT1072. The diode and RC at 01's base damp inductor related parasitic behavior. The circuit's output drives the avalanche stage in similar fashion to the LT1073 based circuit. A Simple Ultra-Low Dropout Reguiator Switching regulator post regulators, battery powered ap- paratus, and other applications frequently require low Gropout linear regulators. Otten, battery lite is significantly affected by the regulator's dropout performance. Figure 30's simple circuit offers lower dropout voltage than any ‘monolithic regulator. Dropout is below 5OmV at 1A, in- creasing to only 450mAat 5A. Line and load regulation are within 5mV, and initial output accuracy is inside 1%. AN45-19Application Note 45 Additionally, the regulator is fully short circuit protected, and fas a no load quiescent current of 6O0WA, Circuit operation is straightforward. The 3-pin 11123 regulator (10-92 package) servo controls Q1's base to maintain its feedback pin (FB) at 5V. The 10uF output capacitor provides frequency compensation. I the circuit is located more than si inches from the input source, the optional 10uF capacitor should bypass the input. The optional 2002 resistoriimits LT1123 power dissipationand is selected based upon the maximum expected input Voltage (see Figure 31) Normally, configurations of this type offer unpredictable short circuit protection. Here, the MJE1123 transistor Figure 20. The Ultra-Low Dropost Regulator. 111128 Bi] Gains wih sei Seaes sort Cow Oropotand Short Creat Protection ad 425 19 475 50 525580 575 610 curPu uanen Figure s2-Str Gel cure for 0Randomly Selected AN45-20 shown has been specially designed for use with the 111123. Because of this, beta based current limiting is practical. Excessive output current causes the LT1123 to pull down harder on 01 until beta limiting occurs. Under ‘these conditions the controlied pull down current com- bines with Q1's beta and safe operating area characteris- tics to provide reliable short circuit limiting. Figure 32 details current limit characteristics for 30 randomly se- lected transistors. Figure 33 shows dropout characteristics. Even at 5A, ‘dropout is about 450mV, decreasing to only SOmV at 1A Monolithic regulators cannot approach these figures, pri- rmatily because monolithic power transistors do not offer ASSUME e081 neu vo.Ta 0 Figure 31. L11128 Power Dissipation Limiting Resistor Value vs Input Voltage Figure 33. Dropout Voltage vs Output Curent LT WERApplication Note 45 Figure 34, Dropout Voltage vs Output Curent for Various Regulators 1's combination of high beta and excellent saturation For comparison, Figure 34 compares the circuit's perfor- ‘mance against some popular monolithic regulators. Drop- out is 10 times better than 138 types, and significantly better than the other types shown. Because of Q1’s high beta, base drive loss is only 1%-2% of output current evenat full A output. This maintains high eficiency under the low Vin ~ Vour conditions the circuit wil typically operateat. As an exercise, the MJE1123 was replaced with a 2N4276, a Germanium device. This combination pro- vided even lower dropout performance, although current limit characterstios cannot be guaranteed. Figure 35 shows a simple way to add shutdown to the regulator. A CMOS inverter or gate biases Q2 to control 11123 bias. When Q2's base is driven, the loop functions ‘normally. With 02 unbiased, the circuit goes into shut- down and pulls no current. Cold Cathode Fluorescent Lamp Power Supply Current generation portable computers utilize back-lt LCD displays. Cold Cathode Fluorescent Lamps (CCFL) provide the highest availabe efficiency for back-lighting the display. These lamps require high voltage AC to operate, mandating an efficient, high voltage DC-AC con- verter. In addition to good efficiency, the converter should deliver the lamp drive in the form of a sine wave. This is desirable to minimize RF emissions. Such emissions can cause interference with other devices, as well as degrad- ing overall operating efticiency. Figure 36 meets these requirements. Efficiency is 78%, with an input voltage range of 4.5V-20V. 82% efficiency is possible ifthe LT1072 is driven from a low voltage (e.9., 3V-5V) source. Additionally, lamp intensity is continu- ously and smoothly variable from zero to full intensity, 8 Vou soo iy 6 Fie 35, shvow rte Lov pot Raptr Cr ma ton Isr ccm ce ana aD ROS Figure 36. Cold Cathode Fluorescent Lamp Power Supply LT WEAR AN45-21Application Note 45 ‘When power is applied the LT1072 switching regulator's ‘feedback pinisbelow the devicesintemal 1.23V reference, causing full duty cycle modulation at the Vey pin (trace A, Figure 37). L2 conducts current (trace B), wich flows Figure 37. Wavetorms forthe Cold Cathode Fluorescent Lamp Power Supply. Note Independent Triggering on Traces A and 8 and C Through F. from L1’s center tap, through the transistors, into L2. L2's ‘current is deposited in switched fashion to ground by the regulator's action. Lt andthe transistors comprise acurrent driven Royer class converter® which oscillates at a frequency primarily set by L'scharacteristics and the0,02uF capacitor. LT1072a i Sa | = PFU SIONS Tana oS CON UR HMR 1 Gactaowics- cso se raw ( BY enn vur120(Sb) em = Figure 9. LT1070 Floating Input Step-Down Switching Regulator Vow PORIDUTAL= 542097 meme Figure 10. LT1070 Floating Input Step-Down Convert Wavetorms Vs pin voltage transitions are different. For the LT1070 circuit the Vey pin voltage swings from the negative terminal of the input supply to a diode drop above the output voltage. In comparison, the LT1074's Vsw pin switches from the positive rail to a diode drop below ‘ground. Figure 11 details the maximum output current for various input voltages and power devices. When the LT1070 operates at a duty cycle greater than $0% its maximum switch current is reduced, which causes the decrease in maximum output current seen at low input voltages. : Figure 11. Viv lou Floating Input Buck Converter ‘The feedback senses the output with respect to the GND pin, so a level shift is required from the SV output. 01 serves this purpose, introducing only ~2mVi°C dri, (see Equation 3). This is normally not objectionable ina logic supply, but can be compensated for with the optional appropriately scaled diode/resistor, (see Equation 4 in Figure 9). Figure 12 shows this circuit's efficiency characteristics. Efficiency at low input voltages is significantly higher than the previous circuit because of lower power switch losses. AT NEA AN46-5Application Note 46 Figure 12. 1070 Negative Buck Converter Eticiency for Various Input Voltages and Load Currents At high input voltages and low output current levels the IC's quiescent current reduces the circuit's efficiency. The diode, filter capacitors, and inductorlossesare comparable to the previous LT1074 buck circuit. Figure 13 shows this cicui’s topology used for negative buck conversion ts operating wavetormsare thesameas shown in Figure 10. The common ground connection between the input and output voltage does not change the ‘operating characteristics of the circuit. Figure 13. 11070 Negati High Efficiency Step-Down Switching Regulator ‘Although more complicated than the previous circuit, the high efficiency circuit in Figure 14 allows a common ‘ground connection between inputand output. Here, circuit complexity is traded off for increased ficiency at low input voltages. The circuit operating characteristics are similar to that of the step-down regulator of Figure 5. In this case, an T1070 common emitter NPN output switch is used to drive the inductor tothe positive rail. Using an NPN switch achieveslower conduction ossestthantte composite PNP used in the LT1074 ‘The operating waveforms for this circuit are shown in Figure 15, When the L11070's switch turns on, itpulls the GND pin to the input voltage. Trace A is the GND pin voltage and trace B is its current. During this period, current flows from the input through the LT1070 and the inductor, and into the oad. Inductor current is shown in ‘race C. When the LT1070 switch turns of, the voltage on the GND pin drops until the clamp diode is forward biased (trace D is clamp diode current), providing a current path for the inductor to transfer its energy to the output. Maximum output current for various input voltages and ower devices is shown in Figure 16, Step-Down Switching Regulator AN46-6 LT LNAApplication Note 46 Slug Saye Tie I aun Fines SHITOONN ES Or oll : (car voyr e280 (uf) RE $200 eon a. A ou or Figure 15. 171070 High Efficiency Step-Down Converter Waveforms Figure 16. Vi ¥é lyr for High Eficiency Buck Converter LT WINER AN46-7Application Note 46 For this circuit to function the Viy pin must be driven above ‘the input voltage (trace E). This is accomplished by bootstrapping C2 off the GND pin of the LT1070. C2 charges up through D1 when the LT1070 switch is off. ‘When the switch turns on, D1 reverse biases allowing the Vy pinto rise above the input votage. The GND pin is pulled to within a few hundred millivolts of the input ‘voltage. The Vin pin voltage is now twice the input voltage. C2's stored charge provides adequate supply current and ‘base drive for the power switch during this interval, The output voltage is controlled by the LT1431, an adjust- able shunt voltage regulator. The output voltage is set by the ratio of Rt and R2, (see Equation 7 in Figure 14). The 111431's error amplifier compares the reference pin volt- age to its internal 2.5V reference. The LT1431's output drivesa shunt transistor, 02, which absorbs current from the Ve pin of the LT1070, adjusting duty cycle, The Ve pin RC network provides sufficient loop compensation. It is offen desirable to put a switching regulator into “shutdown mode", a condition where the switching requ- fatoris turned off and draws micropower current levels, to maximize battery life. One solution is to place a MOSFET ‘switch in series withthe input. This approach requires a large power device and reduces efficiency at high output ‘currents, The LT1070 provides an elegant solution to this problem by integrating @ shutdown feature. When the voltage between the Vo and GND pin is pulled below 150mV, the IC shuts down pulling only 150A. This is implemented by turning on Q1, reducing the circuit's ‘Quiescent current from 6mA to 150uA. When the input voltage is first applied to this circult, the regulator dumps tull shor circuit current into the output ‘capacitor, attempting to bring the output up to its regu- lated value. The output can overshoot its desired value before the control loop is able to ile back the output ‘current. This condition could overdrive G2, forcing it to pull the voltage between the Vo and GND pin below 150m, and putting the LT¥070 in its shutdown mode. The output voltage would momentarily drop to zero and remain there until the Vo pin rises above S00mV. To preventthis condition from occuring the Vepinis clamped by D3 and the 470k resistor is used as a pull up. Figure 17 shows efficienay approaching 90%. Squeezing the utmost efficiency from this circuit requires care. The lor igure 17. LT1070 High Etciene Positive Buck Converter Efficiency ower switch and the catch diode conduction losses are the two main loss elements. These devices forward volt- ‘age drop must be minimized in order to maximize eff- ciency. A Schottky diode is used for its minimum forward voltage drop. The inductor selection is not a trivial task since it can add a couple percent loss. Low core loss material such as Molypermaloy, ‘high flux’, "Kool Mu” (Magnetics, Inc), and ferrite cores should be used. Nor- mal design procedure for wire size may have to be modi- fied to reduce copper loss. ‘The LT1431 and associated control circuitry can be re- placed by an LT1432. Refer to the LT1432 data sheet for further details. Po: ive to Negative Buck Boost Switching Regulator ‘Afrequent switching regulator application isto produce a negative output from a positive supply, usually 5V. One approach sto use atransformerina tlyback topology, but transformers are not off-the-shelf components. They are expensive, especially in low volumes, and can have long delivery times. Alternately, a negative output is easily obtained with a simple inductor. Inductors are more desirable than transformers in many converter designs because they are readily available and economical. The negative output requirementis easily fulfilled by the circuit shown in Figure 18, ‘The operating waveforms are shown in Figure 19. When the LT1074 switch turns on, current flows from the input through the LT1074 and into the inductor. Trace A is the switch pin voltage and trace B is its current. During this AN46-8 AT WEARApplication Note 46 SRS ey Sontag) Figure 18, L11074 Positive to Negative Switch Figure 19. LT1074 Positive to Negative Converter Wavetorms period current ramps up inthe inductor (trace C) as energy isstored in the core. When the LT1074 power switch turns ofthe voltage on the Vsw pin drops until clamp diode D1 forward biases (trace D). This provides a current path for the inductor to transfer its energy tothe output. Figure 20 shows this cirouitcan provide a 1A output fora 4.5Vinput In this architecture the LT1074’s GND pin is tied to the negative output rather than to ground. This technique eliminates a level shitting op amp in the feedback path. Feedback is sensed from circuit ground, and the regulator forces its feedback pin to 2.21V above its GND pin, The ‘output voltage can be varied by changing the R1-R2-R3- 4 divider ratio, (see Equation 10 in Figure 26). The 11074 controls duty, cyete to achieve output voltage regulation. Positive to negative converters have a “right half plane zero" inthe transfer function, which makes them particu- larly hard to frequency stabilize, especially with low input voltage. Ri, R2 and C3 form an AC feedforward path needed for loop compensation at low input voltages. They can be omitted for Viy > 10V, oF VyVoyr > 2. This net- work along with C4 provides stable loop frequency compensation. Efficiency generally exceeds 60% as shown in Figure 21 Efficiency is degraded at low input voltages where the 11074 power switch isresponsible for the majority ofthe efficiency loss. Its 2.0V switch voltage drop cuts the vam Figure 20. Vy vs ut for Positive to Negative Converter rmCeNor Figure 21. LT1074 Positive to Negative Converter Eficiency for Various input Voltages and Load Currents LT NEAR AN46-9Application Note 46 ee _ efficiency by 28% ata SV input; another 10% is contributed by the output diode. Higher input voltages make the fixed LT1074 voltage drop a smaller percentage, improving efficiency. High Efficiency Positive to Negative Switching Regulator The previous circuit has excellent efficiency performance above a 12V input. However, at low input voltages the efficiency tals off dramatically. The LT1074’s internal power switch voltage drop is the major contributor tothe degra~ dation of eficiency. Figure 22 shows an alternative ap- proach to generatea negative output from a positive input. Here, the LT1070 low loss switching transistor achieves remarkable efficiency levels, even with a 5V input This circuit is reminiscent of the high efficiency buck converter of Figure 14. The control circuitry and the manner in which the T1070 power switch is driven are identical. However, the power components route the cur- rent through the same course as the previous positive to negative design; therefore, their switching characteristics are the same. The switching waveforms for this circuit are shown in Figute 23. Trace A isthe LT1070's GND pin voltage and trace Bis its current. Current flows through the LT1070 and the inductor when the power switch is on. When the switch turns off, the voltage on the LT1070's GND pin drops until diode D4 forward biases. Inductor current (trace C) then flows through 04 (trace D). Figure 25 shows this circuits efficiency approaches 70% for a 5V input. The higher efficiency at low input voltage results from the LT1070’s extremely low switch conduc- tiomloss. The effec of switch loss can be seen by compar- ing the efficiency characteristics of Figure 21 and Figure 25. The LT1074-based circuit's efficiency drops dramati- cally at inputs below QV. Figure 22. 171070 High Etilency Positive to Negative Switching Regulator AN46-10 LI MERApplication Note 46 Figure 23. 1070 High Etiiency Positive to Negative Converter Waveforms — ° o ® 0 24. Vy lr for High Etficiency Positive to Negative LT1070 Negative to Positive Switching Regulator This converter topology can maintain a constant output voltage whether the absolute value of the negative input voltage is greater or less than the positive output voltage This is extremely desirable in battery operated electronic equipment. This flexibility reduces the number of battery cells required and provides a constant output voltage over the battery's complete operating range, maximizing bat- tery life. The circuit is shown in Figure 26. Ths technique can be used only i the input and output voltage negative terminals are not connected to each other. This circuit operates similar to the boost regulator of Figure 1, buts intended for buck-boost conversion. Here, ‘the positive terminal ofthe battery is connected to ground Figure 25. L11070 High Eficiency Positive to Negative Converter Efficiency for Various input Voltages and Load Current and the LT1070's GND pin is connected to the negative terminal. The feedback pin senses with respect to GND Pin, $0 Qt provides a level shift from the 5V output Figure 27 shows the circuit operating waveforms. They resemble those of the boost regulator (Figure 2). The primary difference between the two circuits is that the inductor current does not flaw through input capacitor C1 during the switch off time. Ths is noticeable inthe input capacitors ripple current waveform (trace B). The ripple current is significantly higher, compared to the boost circuit, since the current is being pulled from the input capacitor in pulses. This increased ripple current necessi- ‘ates larger input capacitor. Maximum output current for Various input voltages and power devices is shown in Figure 28. Figure 29 shows circuit eficiency in excess of 75%. Once again the main contributors to power loss are the switch- ing diode and LT1070's internal power switch Flyback Converter Many applications require multiple regulated output po- tentials. A popular autput combination is SV and +12V as implemented in the circuit shown in Figure 30. This circuit is a basic flyback regulator. The transformer transfers energy from the 12V input to the SV and 12V ‘outputs. Figure 31 shows the operating waveforms for this circuit. Trace Ais the voltage atthe Vw pin and trace B is its current. During the Vey on-time, the Vew pin is pulled LT NEAR AN46-11Application Note 46 sh wanes +. ssc nesisOns, py MOIOROCA ams 1 mac GPae 22a rata (Houmas nan 9 =o WOAZOUTA 580 Figure 27. L11070 Negative to Positive Converter Wavetorms to ground forcing the input voltage across the primary winding, After the inital jump, the primary current (trace C) rises slowly as the magnetic field builds up. The ‘magnetic field in the core induces a voltage on the second ary windings, which is proportional tothe input voltage times the turns ratio. However, no power is transferred to the outputs because the rectifier diodes are reverse bi- ased, The energy is stored in the transformer’s magnetic field, When the switch is turned off, energy is no longer Figure 28. Vu ¥ lur for Negative to Positive Converter Figure 29. LT1070 Negative to Positive Converter Eticieny fr Various input Voltages and Load Currents transferred to the transformer causing the magnetic field tocollapse, The colapsing magnetic fieldinducesa change involtage across the transformer's windings. During this transition the Vsw pin's voltage flies to a potential above the input voltage, the secondary forward biases the reci- fier diodes, and the transtormer's energy is transferred to the outputs. Trace D isthe voltage seen on the SV second- ary and trace E ists current. This is not an ideal transformer, so not all the energy is coupled into its secondary windings. The energy lettin the primary winding causes the overvottage spike seen on the Vey pin (trace F). This phenomenon is modeled by an inductor term placed in series with the primary winding When the switch is turned off, current continues to flow in the primary winding, causing D1 and D2 to conduct (race 6), This diode network clamps the flyback voltage spike, AN46-12 LIT NeApplication Note 46 |. c8 ‘0 7 ae 7 iF ots Stn mao es ates Ts" a 7 c “ \ Titer 7 eo iy (8 (eo Yoyr=2300 (BS Figure 30. LT1070 Flyback Switching Regulator AT WEA AN46-13Application Note 46 su secow0any Figure 31. Wavetorms forthe LT1070 Fiyback Converter preventing excessive voltage at the LT1070's Vsw pin. When the primary current reaches zero, the Vsw pin’s Voltage settles to a potential related to the turns ratio, output and input voltage How well the unregulated outputs track each other, often ‘eferred to as cross regulation, depends upon how tightly they are magnetically coupled to one another. Post regu- {ators are needed on the unregulated outputs if the cross regulation erroris too great. Such error can be as much as 20% depending upon output loading conditions. ‘The isolated secondariesallowa negative voltageregulator to be used to regulate the +12V output. The advantage of the LT1185 over standard linear regulators is its ability to control current limittotypicaly within 4%, betweenits 1A- 3A range, allowing the use of smaller rectifier diodes, ‘secondary windings wire size, and core size. The isolated secondary windings’ allows the input of the LT1185 to floatbelow ground. TheLT1 185 negative oltageregulators maintain both positive and negative outputs. Figure 32 represents the total available output power for various input voltages and power devices. For simplicity ‘he available output power is summed into the 5V output. It the auxiliary outputs are used, the maximum available current from the 5V output is reduced. This flyback circuit's efficiency approaches 80% (see Figure 33). Power is primarily dissipated in the LT1070, catch diode D3, and zener diode D1. The LT1070and catch diode impose losses in the same manner as they did inthe previous circuits. The zener clamp diode is a power loss element commonly found in flyback designs. t dissipates energy stored in the transformers leakage inductance. To keep leakage inductance losses to a reasonable level, leakage inductance should be kept to less than 1% of the primary inductance. For the flyback topology, the output fitter capacitor takes teal beating at high output currents. This is due to the transformer providing current to the output capacitor in pulses, In many flyback designs the turns ratiois less than AN46-14 AT WRApplication Note 46 Figure 32. Vy vs laut for Flyback Converter ‘one and the secondary currents 1/N times higher than the primary current (see Figure 31). The primary winding peak current (trace C) is 5A, whereas the secondary winding peak current (trace E) is 15A. In this case two capacitors Connected in parallel are needed to handle the RMS ripple current. nev Figure 33. 11070 Flyback Converter Eticiency for Various tnput Voltages and Load Curents References 1. Coittronies 984 S.W. 13th Court Pompano Beach, FL 33069 Phone: (305) 781-8900 Fax: (305) 782-4163, CS APPENDIX A Thermal Considerations for Aluminum Electrolytic Filter Capacitors Aluminum electrolytic capacitors often fail in switching regulators because many designers do not view them as power components. Like any power device, capacitors have thermal limitations which must be observed for acceptable performance and reliability. Excessive capaci- tor temperature can causean open or short circuit, capaci- tance drop, electrolyte leakage, increased leakage current or safety venting, Increased temperature causes a gradual evaporation of the electroytethrough the capacitors seal. As the electro- lyte is lost, the capacitance is reduced and Effective Series Resistance (ESR) rises, causing increased power dssipa- tion. Its regenerative process continues itcan cause the Capacitor to exceed its maximum thermal rating. In poorly designed power Supplies itis not uncommon to have early field failures because the electrolyte ina filter capacitor has dried up Filter capacitors are chosen by physical size rather than capacitance value, since larger size capacitors have higher ripple current ratings, lower ESR and more heat dissipa- tion capability. Selecting the appropriate size for a given application depends upon several factors: = Ripple current rating/ESR = Position on the PC board ~ Maximum ambient temperature = Load life Additional factors include output voltage ripple and loop stability. These secondary considerations are not treated here. The capacitor's operating ripple current sets the minimum acceptable capacitance size, Maximum allowable ripple ‘current is selected to limit temperature rise in the capaci- tor. This internal temperature rise is proportional to the square of the capacitor’s ripple current. Typical core to ambient temperature rise is between 5°C to 10°C. For reliable operation the capacitor must operate below the LT NEAR AN46-15Application Note 46 ‘maximum allowable ripple current. Appendix B explains how to measure operating ripple current. Thereisa tendency for designers to select iter capacitors based on capacitor value instead of ripple current. This approach can be catastrophic because ripple current rat- ings vary widely between capacitor technologies, manu- facturers and voltage ratings Figure At shows how varied the ripple current rating stor similar value capacitors with different voltage ratings. In this example, the 63V part can handle over twice the RMS current of the 6.3V device because the higher voltage capacitor is physically large. Votage Rating Gav 10V 16v 25V abv SOV BBV Tas (8) 01060 T4i0 i680 1989 21202370 Hchican PL series 105, 105° Figure At. Ripple Curent Ratings for Diferent Voltage Ratings High ripple currents require capacitors to have low ESR, greater surtace area, and a high heat transfer constant. Figure A2 shows the relationship between volume and ripple current rating, Tall capacitors of equal volume as short fat ones tend to be able to dissipate more heat since they can transfer the heat tothe case surface more easily ™™ ss vowume acc) Figure A2. Ripple Current vs Volume When the required ripple current is greater than the maximum rated ripple current, it becomes necessary to parallel capacitors. Parallling allows sharing ofthe ripple Current between capacitors. The ESR of each capacitor acts asa current ballasting impedance. In some instances it may be preferable to parallel capacitors even when a single device of higher ripple current rating is available. Thisallows smaller size capacitors o be utilized. Heat ow increases from multiple capacitors when compared to a single device witha higher current rating because the heat is spread over a greater area ‘The ESR of the capacitor is the predominant cause of internal temperature rise above ambient. The power loss in the capacitor is determined by: Prap=(Ins)®* ESR ESR = Effective Series Resistance Jayas = Capacitor Ripple Current Capacitor size versus ESR rating varies widely for diferent capacitor technologies and between manufacturers. Fig- ure A3 shows ESR vs Volume for Different Capacitor Manufacturers. oS oy (LU or : ” Figure AS. ESR vs Volume for Dilferent Capacitor Manufacturers Printed circuit board layout can have a dramatic effect on a capacitor’s operating temperature. For example, one ‘terminal of an output capacitor is often connected to a catch diode, During full load conditions the diode can ‘each junction temperatures in excess of 100°C, dissipat- ing several watts. The diode's leads conduct the heat into the PC board traces, where it can be transferred into the filter capacitor, elevating its internal temperature. Wide PC board traces at the diode will dissipate this heat, reducing ‘capacitor heating. ‘Another frequently overlooked layout consideration is the ‘capacitors location relative to heatsinks. Heatsinks radi- ate heat, increasing an adjacent capacitor’s temperature. AN46-16 LT NEARCapacitor load life includes both parametric and cata- strophic failures. A capacitoris considered failed if capaci- tance, ESR or leakage current exceeds maximum allow- able variation, ESR variation is the parameter of primary concern for switching regulators because, as ESR in- creases, output voltage ripple and thermal dissipation go up. The load life of a capacitor is rated in hours, typically between 1,000 hours and 10,000 hours, with full rated ‘voltage applied across its terminals ata specified tempera- ture, usually 105°C. Load life definitions vary for different type of capacitors. Load lite increases for larger case diameters; refer to Figure Ad. Load lifes primarily limited by electrolyte loss. One reason for the increased load lfe between case sizes is that larger devices hold more electrolyte; it simply takes longer for the electrolyte to dry up. GaseDameter(rm) 05 Oe oad Life (ours) 20003000 Nichicon PL sores T05,F-106°C — Figure Ad. Load Lite Rating for Dit ‘The load life specification of a capacitor can be a little confusing. For example, a Nichicon PL series capacitor with a case diameter of between 8mm-10mm has a load lite of 3,000 hours while being operated at 105°C. This information as stated is not very useful, since most products are designed to last longer than 18 weeks (3,000 hours), and will not be subject to 105°C. nt Case Diameters The relationship between thermal stress and expected life of the capacitor can be predicted by: 10560 - (Ty + aT) Lysly*2 10 Ly: Lite expectancy in actual operation (hrs) Lo:Load fife at maximum operating temperature (hrs) Tx: Ambient temperature in actual operation (°C) Ty: Temperature rise produced by ripple current (°C) (a2) (ay) _W*ESR, aK by: Operating ripple current (A) ESR :Effective Series Resistance (2) Application Note 46 B:Heat transfer constant — determined by case size (W/cm?/°C} ‘A: Case surface area (om?) ra) (9) 4D :Gase diameter LCase length A= Heat transfer constants are not normal data sheet param- eters, but can be obtained from the manufacturer. Figure ‘AS showsthe heat transfer constant for United Chemi-Con electrolytic capacitors. The heat transfer constant is pre- dominately affected by the thermal characteristics of the ccapacitor’s aluminum case and its surface area. Since the aluminum material is the same forallseries capacitors, the heat transfer constant depends only on surface area. These thermal parameters assume that the case is com- pletely filed with the fail winding. Not all capacitors’ cans are ul, and should be checked by disassemblinga sample. Equation At shows that with aluminum electrolytic ca- pacitors, load life doubles for every 10°C drop in operating ‘temperature, The equation includes the effects of operat- ing ripple current, ambient temperature and heat transfer constant of the package Forexample, a United Chemi-Con SXE25VB471M1OX20LL capacitor operating ata ripple current of 860mA and an ambient temperature of 60°C would have an calculated life time of 3.1 years, by =860MA, ESR =0.1402, Lo =2,000nrs, Ty =60°C @DxL=10x20(mm), B=0.0019, A= 7.t0m? oe 0.0019 «7 10m@ 105°0-(60°0 + 706°0) Ly =2,000hrs~2 0 Ly = 27,665 hrs=3.1 yrs The total lifetime and operating duty cycle of a product must first be defined in order to generate a capacitor's actual total operating hours. Then the lifetime equation (At) is used to select a filter capacitor that can meet these ‘operating conditions. Lap top computers, for instance, 7.08°C AT nee AN46-17Application Note 46 “Det A 8 Bea a a « (omsmm) (em?) (wemérc) (wre) (en?) (Whemépc) (Wee) Beit i oot o.0gs0 448 0000e7 —004s5 63x11 “25 0.002081 0.00520 _ 52 ‘2.00000 0.0888 8x ts 350006 ~——=—onego 0x8 0.00085 0.0541 aK 40 00) 0.00800 35x40 000080 00482, ox2s AT .0020t 0.00945 io ‘.o0084 0.0588 10x16 58 0.00798 oonts 35x60 0.00080 0.0805 wox2 Tt 001g 00135 x70 Oooore ——_00esa We5x20 Ot Doig 00166 35x80 “booed ore 12525 110 ooo 00108 x10 ~__ 000070 (0.0887 ~ 1820 35 oor 00173 40x50 ‘0.00080 ‘0.0608 19x25 115 0.00178 ce 40.60 0007 00660 1390 735 —d0orro —_—aaza0 x70 oom oma 85 146 ones ao oo poorest 16x31 78 ‘ooorss 00276 x00 “ooco7) 0.0880 168x355 199 ‘00146 oot 40% 100 ‘00070 0.0867 vera) 72ST OMN 40x 110 00070 0.106 texas 203 dona 00297 0x60 ‘o.o0072 00819 e355 28 ooo 0037 x70 ooo 0nm7 18x40 1 Doo omar 300 Oooo 0.08 88 20 conte ——_—Oatae 50x90 Ooo 018 24x 250 0.00190 ous 50 100 ‘00070 2) ~ aan met ooor2—maeo SOKO ‘oo 0135 24x50 3a ‘00102 003 50x 120 0.00070 0146 vxto 285 Done Ooade _ ~ 5x40 aot 580 42 omy «Oe (Gouresy of United Ghemi-Gon) Figure AS, Heat Transter Constants for Various Ca might be expected to operate no more than four hours @ day on an average, s0@ ten year life is only 15,000 actual operating hours, ‘A capacitors ripple current multiplier can be used to increase the maximum allowable ripple current, allowing smaller size capacitors to be used. However, this method ofincreasing the maximum ripple current rating assumes load ite is kept constant, soit must be used with extreme caution. For example, aNichicon PL series capacitor rated at 1A RMS at 105°C has a load lie of 3,000 hours and a ripple current multiplier of2.2 a 65°. It the ripple current ‘multiplier is used, the capacitors ripple current rating can be increased to 2.2A RMS as long as the operating ‘temperature does not exceed 65°C; however, the load life of the capacitor is still 3,000 hours. Eighteen weeks is a rather short operating lite. References 4. United Chemi-Con inc., "Understanding Aluminum Electrolytic Capacitors.” 2. Nichicon (America) Corp.," Technical Notes on Alumi- num Electrolytic Capacitors.” AN46-18 LT WEARApplication Note 46 Capacitor Manufacturers 1. Nichicon (America) Corporation 927 East State Parkway Schaumburg, IL 60195 (708) 843-7500 2) Sanyo Video Components (USA) Corporation 1201 Sanyo Avenue San Diego, CA 92073 (619) 661-6322 3) United Chemi-Con, inc 9801 West Higgins Road Rosemount, IL 60018 (708) 696-2000 4), Sprague Electric Company ‘Aluminum Electrolytic Div 9800 Kincey Ave. Suite 100 Huntersville, NC 28078 (704) 875-8070 5) Kemet Electronics P.0, Box 5928 Greenville, SC 29606 (803) 675-1760 6) Marcon ‘998 Forest Edge Drive Vernon Hills, IL 60061 (708) 913-9980 7) Wima 2268 Saw Mill River Rd Bldg. 4C P.O. Box 217 Elmsford, NY 10523 (914) 347-2474 ee APPENDIX B ‘Measuring RMS Current in Switching Regulator Filter Capacitors One of the most critical parameters on a capacitor’s data sheetis ts ripple current rating, specified in RMS current, The operating ripple current must be accurately deter- mined in order to select the proper size capacitor. The current waveforms are usually square or triangular and their RMS value can be determined by either measurement ‘or an analytical approach. The preferred method of determining ripple current is to measure it. This can easily be accomplished using a true- RMS voltmeter (HP3400A or Fluke 8920A or equivalent) and a current probe (Tektronix P6021). ‘Thermally based RMS voltmeters provide the high band- ‘width and crest factor capability necessary to accurately measure the RMS current through a filter capacitor. The RMS voltmeter’s bandwidth must exceed 1MHz, since ‘current transients can exceed 100A/us. Do not use aver- age responding or logarithmic based RMS voltmeters. Most hand held voltmeters are average responding and only good for low frequency sinewaves, typically under 10kH2. The logarithmic approach measures true RMS, but bandwidths are limited to well below 1MHz. There are two types of current probes avallabe: the traditional AC only probe and the true DC Hall Effect type. AAC only current probes (P6021) use a transformer to convert current flux into AC signals and have a frequency response from a few hundred hertz to 60MHz. Therefore, donotusea P6021 ifthe ripplecurrent waveform hasa ow ‘frequency component. Hall Effect current probes (P6042) include semiconductors to provide a frequency response from DC to 50MHz. Both types have saturation limitations which, when exceeded, cause erroneous results The following procedure will accurately determine the maximum RMS current for @ capacitor no matter how complex the ripple current waveforms are. The current probe is clipped on the capacitor’s lead and the other end of the probe is connected to the AMS voltmeter. Set the P6021 terminator to its 10mA/mV scale. I is always @ AT WEAR AN46-19Application Note 46 (goodideato view the current waveform on an oscilloscope to verify that the converter is working properly before measuring the RMS voltage. Next, apply maximum load ccurrentto the output of the regulator. The RMS current can be calculated by multiplying the current probe scale factor by the RMS voltmeter reading: lias = Scale Factor * Vayys Reading ‘1OmAmV * 100mV = 1A RMS Vary the switching regulator's input voltage over its entire operating range, The maximum RMS voltage reading wil be the worst case operating condition for the capacitor. Select the capacitor based on this AMS current reading. ita true RMS voltmeter is not available, the RMS current can be estimated by analyzing the capacitor ripple current waveform, Capacitor RMS current waveforms vary for different converter topologies, and between input and output capacitors. Figure B1 shows some common fier capacitor wave~ forms and equations used to derive the values of Irs Current waveforms generally fll into one of four cases. Case 1 is not an actual ripple current waveform, but itis often used to approximate the RMS current since only wo variables are used, Here, worst case ripple occurs at 50% duty cycle, Case 2 is the ripple current waveform for an ows 006) se 1. Rectangular 80 2. Tr Case 3. Tr (ase 4. Saw Tooth Figur 31. Typical Filter Capasitor Ripple Current Waveforms AN46-20 MT WNApplication Note 46 ee input capacitor tor buck, buck-boost, or flyback topology. Case 3s for an output capacitor for boost, buck-boost, or flyback topology. Case 4's waveform is for the input ‘capacitor for boost and output capacitor for buck mode. Figure B2 summarizes these equations and shows equa- tions that can be used to make a quick approximation of ripple current. Here the RMS current is calculated from ‘output current and duty cycle. As long as the ratio of ly cover In is < 2, these equations approximate the RMS current to within 10% of the actual value. There exists a litle confusion about where zero currents located on the capacitor’s current waveform. Figure BS shows an input capacitor’ ripple current for a buck, buck- boost and flyback topology. The zero points always inthe middle since the average current through the capacitor must be 2er0, assuming negligibie leakage current. The two shaded areas are equal because the average current flowing into the capacitor equals the average outgoing current. Figure 83, The Average Current Through the Filter Capacitor is Zero in many switching regulator applications the input supply consists of a 60H single phase step-down transformer followed by rectifier whose outputis smoothed by filter capacitor. Figure B4 shows the fitter capacitor’ ripple ‘current waveform forafull wave bridge rectifier. Theripple current flowing through the input capacitor consists of the high frequency switching ripple current superimposed on the120Hz ripple (trace A). Trace B details the contentof the 400kHz ripple current which is produced by a LT1074 buck switching regulator. To select the proper size input capacitor, the effects of the 4120Hz and the 100ktt2 ripple current waveforms must be considered, Thebest way to determine the nputcapacitor’s Torowoay FLYBACK ow ms* Buck BuCKBOOST Cour Ts" Gu laws" four {00- (00? Cour Tas" al «| Be ca “Refer to que Bt fo deals on and ig Figure 82 Filter Capacitor AMS Curent Equations LT HEAR AN46-21Application Note 46 Figure B4. Input Capacitor’ Ripple Curent Waveform When Input Supply isa 60H2 Full Wave Bridge ripple curtentis to measureit. ADC current probe must be used to measure the 120Hz content of the waveform. An AAG current probe can measure the 10OkH2 ripple but can not accurately measure the 120H2 ripple since its lower Danwidth imitisa few hundred hertz, The HP3400A RMS voltmeter can be used here since its frequency range extends from 10H2 to1OMH2, APPENDIX C Bipolar Power Switch Conduction Losses Power transistor conduction losses limit power conver- sion efficiency. Itcan bea substantial limitation when input voltage is low. Conduction losses include both switch driver and switch on losses. Switch driver losses occur because bipolar devices require base current to turn on and switch on losses are a product of the power transistor saturation characteristic. Figure Ct shows te type and location of the power switch used in the LT1070 step-up (Case 1) and LT1074 step- down (Case 2) converters. These two switching contigu= rations have different power transistor architectures and saturation characteristics. The boost circuit, implemented with an LT1070, uses a ground referred NPN transistor as the switch device, whereas the buck circuit, implemented with an LT1074, uses a supply referred composite PNP high side switch Figure C2 shows the saturation characteristics for each power transistor. The switch voltage drop for the compos- ite PNP in he .T1074 (Case2) is noticeably higher thanthe NPN used in the LT1070 (Case 1) because ofthe way the switch is configured NPN Switeh Figure C2, Case 1 shows Current vs Voltage Characteris- tics of the LT1070 NPN power switch. In saturation, the NPNswitch can be modeled as resistance. Thestope ofthe Curve indicates switch on resistance, which is found by dividing the collector to emitter voltage by the collector ‘current. The on resistance ofthe NPN determines both its voltage drop and power dissipation. The NPN switch conduction loss can be calculated from: Po=(Inws)* * Ron (ct) Another dissipation factor associated with the NPN transistor isthe base drive loss. Driving the base requires current, resulting in power loss ina driver transistor. To optimize efficiency, the LT1070 uses a constant beta drive circuitto control base current. This scheme provides a base drive that is proportional to the collector current. The LT1070 operates with a constant beta drive of 40, ‘which means witha collector current of 5A, the base dive current would be 125mA, but at Ig=1A, Ig is only 25mA. This technique is very efficient over a wide range of collector currents AN46-22 AT Neication Note 46 ‘Case 1. LT1070 Step-Up (Boost) Converter Case 2. LT1074 St Figure C1. Types and Location of Bipolar Power Switches “TTT TTT son sauna LTA 0) (Case 1. T1070 Switeh Current vs Voltage Characteristics me cone Case 2. LT1074 Switeh Current vs Voltage Characteristics Figure C2. Swith Current vs Voltage Characteristics of Bipolar Power Switches ‘The base drive current is drawn from the input pin of the T1070 when the power transistor is on; therefore, driver losses are duty cycle dependent. The LT1070 dissipation because of base drive losses becomes: Porv = Vine lsw/40 * DC (c2) ‘The total LT1070 power dissipation is the sum of the switch conduction and driver losses and is given by. Pror = (las)? Ron + Vin lave/40 (c3) At ow switch currents and high input voltages, driver tosses dominate; switch losses dominate at fow input voltages and high switch currents Composite PNP Switch Conduction Losses Figure C2, Case 2 shows the Current vs Voltage Character- istics of the LT1074 composite PNP power switch. Its power switch can be modeled by a resistance anda series offset voltage, typically 1.8V. The fixed 1.8V drop of the ‘composite switch is made up of 2Vge (=0.75V ea.) drops ross the Darlinaton-connected NPN and a PNP satura- tion drop (~0.3V). The composite PNP power dissipation can be predicted by the following formula: Po tor= 1.8V © lavg + 0.122» (lanss)® (C4) LT NLR AN46-23Application Note 46 —————— {nthis case, both the average and RMS current are needed to calculate power loss. The average current can be used here since the fixed voltage drop is independent of switch current. At low input voltages the switch’s fixed voltage loss degrades efficiency because i makes up a higher percent- age of the available input supply. Higher input voltages make the fixed loss a smaller percentage, improving efficiency The composite PNP high gain configuration needs only ‘5mA of driver current to fully saturate the switch, This ‘small current introduces negligible loss. Determining AMS and Average Switch Currents In order to calculate efficiency, the switch’s average and RMS currents must be determined. Switch current wave- forms generally look lke those of Figure C3. The associ- ated RMS and average current equations are also given Figure C3, Case 1 can be used to make a quick approxima- tion of switch RMS and average current. Figure C3, Case isthe switch current waveform for continuous modeand Figure C3, Case 3 for discontinuous mode Using the thermal RMS voltmeter to measure switch RMS current as discussed in appendix B will work here, but the RMS meter must be able to measure DC. The DC current ‘probe must be properly zeroed! For example, the Fluke 8920A RMS voltmeter will work and the HP 3400A will not because it has an AC-coupled input. Case 1. Rectangular Approximation Case 2, Trapezoid Continuous Mode (Case 3 Trapezoid Discontinuous Mode Figure C3. Typical Switch Current Wavelorms AN46-24 ATERApplication Note 46 —S APPENDIX D Diode Conduction Losses The output diode conduction loss is often the major source of power loss in switching regulators. It exhibits a forward voltage drop (Vj) which limits efficiency. Eff- ciency loss due to Vj is most significant at low output voltages, and should be as low as possible to optimize efficiency. At high output voltages, the forward voltage drop’s effect on efficiency is small, because it makes up a very small percentage of output voltage. For low output voltages, Schottky diodes are recom- mended over silicon diodes because they have a lower forward voltage drop for the same current rating. In a flyback topology with SV output, a Schottky diode with a Vj of 0.6V introduces a loss of 12% of the output power, whereas aslicon diode with a Vj of 1.0V contributes a 20% loss. However, Schottkys are limited to low voltage appli- cations since they have low Peak Inverse Voltage (PIV) limits. Diode conduction loss can be approximated by the follow- {ng formula: Po=loave Jo avg :Average Diode Current \Vj:Diode forward voltage drop at average peak diode current (I; va) (01) Power loss due to diode leakage current is assumed to be negligible. The expression for Pp looks simple, but is deceiving because Vj is a function of the diode’s instantaneous forward current (I), not average diode current (Ip ava) The dependence of Vj on Iris shown in Figure D1 ‘The value to use forty can be determined by examining the diode’s current waveform. Figure D2 showsatypicaldiode ‘current waveform. During the diode on-time, the diode current (\) is not constant; however, it can be approxi- mated by taking the average peak diode current (| ave) NTA FORA ev a2 03 04 05 06 07 08 a9 Figure 01. Typical Forward Vollage wen (t-0 o Figure 02. Typicat Diode Current Wavetorm during this period and is given by Equation 02. This approximation assumes that the diode forward voltage drop is relatively linear for the different peak current values and is reasonably accurate if the ratio of Ip/lais less ‘than three. ‘The average diode curtent (Ip aye) can be determined by using Equation D3. Inthe boost, flyback and buck-boost topology the average diode currents equal to the output current (Iour), since the diode has to conduct the full ‘output current. With the buck topology, the average diode current is only a fraction of the output current; therefore, it has lower conduction losses then the other converter topologies for the same output current level LT NEAR AN46-25Application Note 46 The most stressful condition for the output diode is overload or short circuit conditions. The intemal current limit of the LT1070 is typically 8A at low switch duty cycles. This is almost a factor of 1.6 higher than the 5A rated switch current. If full load output current requires only a fraction of the 5A rated switch current, the ratio of diode shortcircuitcurrent to full load current may be much higher than 2:1. A regulator designed to withstand con- tinuous short conditions must either use diodes rated for {ull short circuit current or it must incorporate some form of external current limiting. The boost topology does not provide short circuit protec- tion, therefore the output diode and inductor can fail the outputs shorted to ground. Ifthe converter must survive a short without blowing a fuse, other circuit techniques must be used, AN46-26 AT WEARApplication Note 46 T1432 High Efficiency Step-down Switching Regulator Controller FEATURES = Accurate preset +5 Volt output Up to 90% efficiency 1 Optional burst mode for light loads = Can be used with many LTC switching ICs = Accurate ultra-lov-loss current limit = Operates with inputs from 6V to 30V = Shutdown mode draws only 15pA = Uses small S0pH inductor APPLICATIONS = Lap-top and palm-top computers = Portable data gathering instruments = DC bus distribution systems = Battery powered digital widgets PRELIMINARY October 1991 DESCRIPTION The LT1432 is a control chip designed to operate with the 1LT1070 family of switching regulators to make a very high efficiency 5V step-down (buck) switching regulator, A minimum of extemal components is needed. Included is an accurate current limit which uses only 60mV sense Vollage and uses “free” pc board trace material for the sense resistor, Logic controlled electronic shutdown mode raves only 15pA battery current. ‘The switching regulator operates dovn to 6 volts input. The LT1432 has a logic controled “burst” mode to achieve high efficiency at very light load currents (0 to 100mA) such as memory keep alive. In normal switching mode, the standby power loss is about 60mW, limiting efficiency at light loads. In burst mode, standby loss is reduced to approximately 15mW. Output current in this mode is ‘typically in the 5-100mA range. ‘The 11432 is avalable in 8-pin surface mount and DIP packages. The LT1070 family will also be available in a surface mount version of the 5-pin 70-220 package. Efficiency NORMAL Move (Se AMPS Sealey ft Bunt MaDe (st na ea | 905A GA 18K 20K 254 30k 9. oma Zona Sma dim ad ink TYPICAL APPLICATION sigh eiciny sv suet comeror i i Sls | pe) song BT | ee | ee “agBsiaoe once wer ba “prime trae OF TToFAN SCRoPATON seca, LITER AN46-27Application Note 46 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION ha be v Pin. t mew mA Vine and Vout Pins. “ vw OF Fa) woe b __] Vim and Vous Pin Differential Votan ne 5V i“ Hoe Diode Pin Voltage . 30V tn ot ax | Mode Pin Current (Note 2) ...onnu0n * a] fs oboe LT1agz0ne Operating Ambient Temperature Range .....0°C to 70°C | LT432cse ‘Storage Temperature RaNge 0... “65°C t0 150°C Pini Lead Temperature (Soldering, 10 $€0,) eon... 300°C since | ELECTRICAL CHARACTERISTICS Ve=6V Vv BV, Vo 100 Vvoe = Y= 220A Vu = Vou, Vuaoe= Device isin standard test ioop unless otherwise noted. PARAMETER eoNoTioNs a os Regul spat otane e419 50 ss v put votage iw egeton eo; sa Ww input sup cant ot 1) e 030s A Avett ogo nd caret ° ag 12 mA ode pn eaent Toca art ot of in ° 080 A __| Move = 5¥ (shutdown) _ ° 16 0 1A uA tof pin ooo 45 |v Vout = 550 tere e075 045 v ‘ein dma si cr Tear = 550 fore @| ass 0815 mm ‘ein soucs eure Vout 4.5 fred le [0 60 100 ” Curent sense votioe Deen caret mop 60 nv wine “Doesnt int Comat tony | @ | 3045 70, uk Sap cern how Vode, vn 6 a Burst ode oo pe : ve nut et iw the Burst mode average output voltage Device in burst test circuit @| 48 5 52 Pv ‘lamp code forvard voltage “= Ima _ 05085 v Star ve eat [our 450 fore enaVt0 2 ca ry ‘Thee denotes specicaonswhichapplyovertheoperstingtemperature Note2Brskdown votage onthe modepinls7V.Exterralcurrentmustbe range. limitedtovalue shown. Note :Does notincude current drawnby he T10701C. See operating parametersinstandardceut. AN46-28 LT WeeTECHNOLOGY Application Note 47 August 1991 High Speed Amplifier Techniques ‘A Designer's Companion for Wideband Circuitry ir Wiliams PREFACE This publication represents the largest LTC commitment to an application note to date. No other application note absorbed as much effort, took so long or cost so much. This evel ofactvityis justified by our belie that high speed monolithic amplifiers greatly interest users. Historically, monolithic amplifiers have represented pack- ets of inexpensive, precise and controllable gain. They have partially freed engineers from the constraints and. frustrations of device level design. Monolithic operational amplifiers have been the key to practical implementation ‘of high level analog functions. As good as they are, one missing element in these devices has been speed. Devices presently coming to market are addressing mono- lithic amplifiers’ lack of speed. They bring with them the ease of use and inherent flexibility of op amps. When Philbrick Researches introduced the first mass produced ‘op amp in the 1950's (K2-W) they knew it would be used. What they couldnt possibly know was just how widely, ‘and how many different types of applications there were ‘As good a deal as the K2-W was (I paid $24.00 for mine - or rather, my father did), monolithic devices are far better. The combination of ease of use, economy, precision and versatility makes modern op amps lust to0 good to be believed. Considering allthis, adding speed to op amps’ attractions ‘seems almost certain to open up new application areas. ‘We intend to supply useful high speed products and the level of support necessary for their successful application (such high minded community spirit is, of course, capitalism's deputy). We hope you are pleased with our intial efforts and look forward to working together. ATER AN47-1Application Note 47 TABLE OF CONTENTS PREFACE so “ -ANST-1 INTRODUCTION oon. ANAT-5 PERSPECTIVES ON HIGH SPEED DESIGN ....oconnsnsn ANAT-5 MR, MURPHY’S GALLERY OF HIGH SPEED AMPLIFIER PROBLEMS Unterminated Pulse Generator... ssn soocnnsessANATT Poorly Terminated Line . seo coon ANAT-B Poor Probe Grounding sosnntnnenn so soon ANAT-8 Undercompensated Probe ANAT-8 Overcompensated Probe : coven ANAT Mismatched Delay in Probes... ses ANAT-9 Overdriven FET Probe ANAT-9 Probe at Amplifier Summing Point - ce ANATAD Poor Quilty POD ..nnronnnsnnnnn ANA7-10 Oscilloscope Overdriven sonninintnnnnannnnnisnsnenncnnnneANGTA Poor or No Ground Plane coon ANATAY No Bypass Capacitors, Heavy Load a sone ANAT AT No Bypass Capacitors, No Load - ANAT-A1 Poor Quality Bypass CapacttOrS ruin ANAT-12 Paralleled Bypass Capacitors Ring - coon ANATA Almost Good Enough Bypass CapacitOrs non ANA7-12 2pF at Amplifier Summing Junction... soon ANATAZ Noise Due to Coupling Into Critical NodeS ANA7-13 ‘pF Coupling Path’s Etect....... nen cos ANST AB Decompensated Amplifier at Too Low a Gain... ANA7-13 Excessive Capacitive Load... a coon ANAT AB Common Mode Overdrive . ee so ANAT-14 Booster Stage with Local OSCatIONS nnn ANAT-14 Booster Stage with Loop Oscillations. — soe ANST AE Excessive Source Impedance ..nruiunsrvnnssnsnnnsnnnsnn ANAT-14 TUTORIAL SECTION ‘About Cables, Connectors and Terminations... ANATAS Aut Probes an Probing Teengues - soon ANAT AB About OSCiOSCOPES ...esnnnninnnannnsnnin sevens ANAT-20 AbouL Ground PIAMES «oe snnnnnnnnsnnn - - ANAT-24 ‘About Bypass Capacitors seo ANAT-25 Breadboarding Techniques - ANA7-26 Oscillation a - ANAT-29 AN47-2 LT WeeApplication Note 47 APPLICATIONS SECTION | - AMPLIFIERS Fast 12-Bit DAC Amplifier. 2-Channel Video Amplifier Simple Video Amplifier Loop Through Cable Receivers DC Stabilization ~ Summing Point Technique DC Stabilization ~ Differentially Sensed Technique OC Stabilization ~ Servo Controlled FET Input Stage DC Stabilization - Full Diferental Inputs with Parallel Paths C Stabilization - Full Differential Inputs, Gain-of-1000 with Parallel Paths . High Speed Differential Line Receiver... a Transformer Coupled Amplifier Ditferential Comparator Amplifier with Adjustable Offset. Differential Comparator Amplifier with Settable Automatic Limiting and Offset Photodiode Amplifier Fast Photo Integrator Fier Optic Receiver... 40MHz Fiber Optic Receiver with Adaptive Trigger. S0MHHz High Acouracy Analog Multiplier Power Booster Stage. High Power Booster Stage Ceramic Bandpass Filters Crystal Filter APPLICATIONS SECTION I! - OSCILLATORS Sine Wave Output Quartz Stabilized Oscillator Sine Wave Output Quartz Stabilized Oscillator with Electronic Gain Control DC Tuned 1MHz-10MHz Wien Bridge Oscillator... o Complete AM Radio Station APPLICATIONS SECTION I!l- DATA CONVERSION ‘1H2-1MHz Voltage-Controlled Sine Wave Oscillator. 1He-10MH2 V > F Converter 8-Bit, 100ns Sample-Hold ‘ns Current Summing Comparator S0MH2 Adaptive Threshold Trigger Circuit... Fast Time-to-Height (Pulsewidth-to-Voltage) Converter. True RMS Wideband Voltmeter APPLICATIONS SECTION IV - MISCELLANEOUS CIRCUITS RF Leveling Loop Voltage Controlled Current Source High Power Voltage Controlled Current Source 16ns Circuit Breaker so ANGT-32 ANA7-32 vs ANAT-B2 ANA7-32 AN47-33 ‘ANA7-34 ANA7-34 ANA7-35, ANA7-35 ANA7-37 ANA7-38 \AN47-39 ANA7-40 AANAT-41 ANAT-41 ANAT-43 ANA7-43 ANAT-44 ANAT-45 wo ANAT-A7. ANS7-48 ANGT-48 ANA7-48 ANa7-49 AN47-49 .ANA7-50 ANAT-51 ANA7-54 ANG7-56 ANG7-57 ANA7-58 ANAT-58 ANA7-61 AN7-63 ANGT-63 ANA7-63 ANA7-63 ee AT Ne AN47-3Application Note 47 REFERENCES APPENDICES ‘ABC's of Probes ~ Contributed by Tektronix, Inc. Measuring Amplifier Seting Time - The Oscilation Problem — Frequency Compensation Without Tears Measuring Probe-Oscilloscope Response.. An Ultra Fast High Impedance Probe Additional Comments on Breadboarding ... FCC Licensing and Construction Permit Applications for Commercial AM Broadcasting Stations About Current Mode Feedback oe sn High Frequency Amplifier Evaluation Board The Contribution of Edsel Murphy tothe Understanding of the Behavior of Inanimate Objects, D.L. Kiipstein (with permission of Cahners Publishing Co.) sen eee peal lesa ANA7-67 ANAT-69 ANA7-82 ANA7-86 ANA7-93 ANGT-96 AN7-98 AN47-123 AN47-124 ANa?-127, AN7-130 AN47-4 AT eeApplication Note 4/ INTRODUCTION Most monolithic amplifiers have been relatively slow devices. Wideband operation has been the province of ciscrete and hybrid technologies. Some fast monolithic amplifiers have been availabe, butthe exoticandexpensive processing required has inflated costs, precluding widespread acceptance. Additionally, many ofthe previous ‘monolithic designs were incapable of high precision and prone to oscillation or untoward dynamics, making them unattractive. Recent processing and design advances have made inex- pensive, precision wideband amplifiers practical Figure 1 lists some amplifiers, along with a summary of their characteristics. Reviewing this information reveals ex- traordinarily wideband devices, with surprisingly good DC characteristics. All of these amplifiers utilize standard op amp architecture, except the LT1223 and LT1228, which are so-called current mode feedback types (see Appendix H, "About Current Mode Feedback’). Iti clear thatthe raw speed capabilites of these devices, combined with their inherent flexibility as op amps, permit a wide range of applications. What is required of the user isa familiarity with the devices and respect for the requirements of high speed circuitry This etfor'sinita sections are devoted to familiarizing the reader with the realities and difficulties of high speed circuit work. The mechanics and subtleties of achieving precision circuit operation at DC and low frequency have been welldacumented. Relatively ite has appeared which discusses, in practical terms, how to get fast circuitry to work. In developing such circuits, even veteran designers sometimes fee! that nature is conspiring against them. In ‘some measure this is true. Likeall engineering endeavors, high speed circuits can only work if negotiated compra~ mises with natureare arranged. Ignorance of, or contempt for, physical law is a direct route to frustration, Mother Nature laughs at dilettantism and crushes arrogance ith- out even knowing she did it Even without Einstein's revelations, the word of high speed is full of surprises. ‘Working with events measured in nanoseconds requires the greatest caution, prudence and respect for Mother Nature. Absolutly nothing should be taken for granted, because nothing is. Circuit design is very much the art ot compromise with parasitic effects. The “hidden schematic” (this descriptive was originated by Charly Gullettof Inte! Corporation) usually dominates the circuit's form, particularly at high speed. In this regard, much of the text and appendices are directed at developing awareness of, and respect for, circuit parasitics and fundamental limitations. This ap- proach is maintainedinthe applications section, wherethe Notion of negotiated compromises is expressed in terms Of resistor values and compensation techniques. Many of the application circuits use the amplifie’s speed to im- Drove on a standard circuit. Some utilize the speed to implement a traditional function in a non-traditional way, with attendant advantages. A (very) few operate ator near the state-of-the-art for a given circuit type, regardless of approach. Substantial effort has been expended in devel- oping these examples and documenting their operation. The resultant level of detali justitied inthe nope tatit will becatalytic. The circuits should stimulate new ideasto suit particular needs, while demonstrating fast amplifiers’ Capabilities in an instructive manner. PERSPECTIVES ON HIGH SPEED DESIGN substantial amount of design effort has made Figure 1's amplifiers relatively easy to use. They are less prone to oscillation and other vagaries than some much slower amplifiers, Unfortunately, laws of physics dictate that the circuit's environment must be property prepared. The performance limits of high speed circuitry are often determined by parasitcs suchas stray capacitance, ground impedance and layout. Some of these considerations are presentin digital systems where designers are comfortable describing bit patterns, delays and memory access times in terms of nanoseconds. Figure 2's test circuit provides valuable perspective on just how fast these amplifiers are Here, the pulse generator (Trace A, Figure 3) drives a 774804 Schottky TTL inverter (Trace), an LT1223 opamp Connected as an inverter (Trace C), and a 74HCO4 high speed CMOS inverter (Trace D). The L123 doesn't fare toobadly.Itsdelay and flltimes areabout 2ns slower than the 74804, but significantly faster than the 74HCO4, In fact, the L123 has completely finished its transition before the 74HC04 even begins to move! Linear circuits ‘operating with this kind of speed make many engineers justifiably wary. Nanosecond domain linear circuits are widely associated with oscillations, mysterious shifts in AT WER AN47-5Application Note 47 slayydwy 917884 waey1q awOS jo SaNSwE}DEENY “| anbLy 96] ee 8 many [oxy 0008 0002 ~ 008 wis Dante ‘nw ure Sr 0-SuGL | HL O-SUO6 re] svgaus [Hwose[ srimogos_[s¥ing07 weer | ecu) aay | “Wwiunau3i | SST AT Wee AN47-6Jo so oureur 2o=s00] rscurrur oeraton >aveue co OUTPUT Figure 2. A Race Between the LT1223 Amplt Logie inverters egw Figure 3. The Amplifier (Trace C) is Sns Slower than 748 Logie (Trace B), but Sns Faster than High Speed HCMOS (Trace 0)! circuit characteristics, unintended modes of operation and outright failure to function. Other common problems include different measurement results using various pieces of test equipment, inability to make measurement connections to the circuit without inducing spurious responses, and dissimilar operation between two identical circuits. f the components used in ‘the circuit are good and the design is sound, all of the above problems can usually be traced to failure to provide a proper circuit environment, To learn how to do this Application Note 47 requires studying the causes of the aforementioned difficulties. The following segments, "Mr. Murphy's Gallery of High Speed Ampifier Problems” and the “Tutorial Section”, address this, The “Problems” section alerts the reader to trouble areas, while the “Tutorial” highlights theory and techniques which may be applied towards solving the problems shown, The tutorialsare arranged in roughly the same order as the problems are presented MR. MURPHY’S GALLERY OF HIGH SPEED AMPLIFIER PROBLEMS It sometimes seems that Murphy's Law dominates all physical law. Fora complete treatise on Murphy's Law, see Appendix J, "The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects”, by DLL. Klpstein. The law's consequences weigh heavily in high speed design. As such, a number of examples are iven in the following discussion. The average number of phone cals we receive per month due to each “Murphy” example appears atthe end of each figure caption. Problems can start even before power is applied to the amplifier. Figure 4 shows severe ringing on the pulse edges at the output of an unterminated pulse generator cable, Ths is due to reflections and may be eliminated by terminating the cable. Always terminate the source in its characteristic impedance when looking into cable or long ‘An Unterminated Puse Generator Cable Produces ‘Due to Reflections ~3 {nFigures the cableis terminated, butrippleand aberration arestill noticeable following the high speed edge transition. Inthisinstance the terminating resistors leads arelengthy (-3/4"), preventing a high integrity wideband termination. LT NEAR AN47-7Application Note 47 Figure 5. Poor Quality Termination Results” in Pulse Corer At The best termination for 5002 cables the BNC coaxial type. These devices should not simply be resistors in an enclosure. Good grade 502 terminators maintain true coaxial form. They use a carefully designed 500 resistor with significant effort devoted to connections to the actual resistive element. in particular, the largest possible connection surface areas utilized to minimize high speed losses. While these type terminators are practical on the testbene, they are rarely usedas board level components. in general, the best termination resistors for PC board use are carbon ar metal film types with the shortest possible leadlengths. These resistor'send-cap connections provide better high speed characteristics than the rod-connected composition types, Wirewound resistors, because of their inherent and pronounced inductive characteristics, are ‘completely unsuitable for high speed work, This includes so-called non-inductive types. ‘Another termination consideration is disposal ofthe cur- rent flowing through the terminator. The terminating resistor's grounded end should be placed so thatthe high speed currents flowing from it do not disrupt circuit operation. For example, it would be unwise to return terminator current to ground near the grounded positive input ofan inverting op amp. The high speed, high density (BV pulses through a 5082 termination generates 100mA current spikes) current flow could cause serious corrup- tion of the desired zero volt op amp reterence. This is another reason why, for bench testing, the coaxial BNC terminators are far preferable to discrete, breadboard mounted resistors, With BNC types in use the termination current returns directly to the source generator and never flows in the breadboard. (For more information see the Tutorial section.) Select terminations carefully and evalu- ate the effects of their placement in the test set-up. Figure 6 shows an amplifier output which rings and distorts badly after rapid movement. In this case, the probe ground tead is too long. For general purpose work, ‘most probes come with ground leads about 6 inches long. At low frequencies this is fine. At high speed, the long {ground lead looks inductive, causing the ringing shown. High quality probes are always supplied with some short ‘ground straps to deal with this problem. Some come with very short spring clips which fix directly to the probe tp to facilitate a low impedance ground connection. For fast work, the ground connection to the probe should not ‘exceed {inch infength (Probesare coveredin the Tutorial section; also see Appendix A, “ABC's of Probes”, guest written by the engineering staff of Tektronix, Inc.). Keep the probe ground connection as short as possible. The ideal probe ground connection is purely coaxial. This is why probes mated directly to board mounted coaxial ‘connectors give the best result. In Figure 7 the probe is property grounded, but a new problem pops up. This photo shows an amplifier output Figure 6. Poor Probe Grounding Badly Corts the Observed Waveform ~ 53 Figure 7. improper Probe Compensation Causes Seemingly Unexplainable Amplitude Error ~ 12: AN47-8 ATEexcursion of 11V—quitea rick from an amplifier running from #5V cals, This is a commonly reported problem in high speed circuits and can be quite confusing, It is not due to suspension of natural law, but is traceable to a grossly miscompensated or improperly selected oscilo- scope probe. Use probes which match your osciloscope’s input characteristics and compensate them properly. For discussions on probes, see AppendixA, “ABC's of Probes”, ‘guest written by the engineering staff of Tektronix, Inc. and the Tutorial section) Figure 8 shows another probe- induced problem. Here the amplitude seems correct but the amplifier appears slow with pronounced edge round- ing. In this case, the probe used is too heavily compen- sated or slow or the oscilloscope. Never use 1X orstraight probes. Their bandwidth is 20MHz or less and capacitive loading is high. Check probe bandwidth to ensure itis adequate for the measurement. Similarly, use an ascilo- scope with adequate bandwidth, Figure 8. Ovecompensated or Slow Probes Make Edges Look Too Slow -2 ‘Mismatched probes account for the apparent excessive amplifier delay in Figure 9, Delay of almost t2ns (Trace A is the input, Trace B the output) is displayed for an amplifier specified at 6ns. Always keep in mind that various types of prabes have different signal transit delay times. Athigh sweep speeds, this eect shows up in mutt trace displays as time skewing between individual chan- ‘els. Using similar probes will eliminate this problem, but measurement requirements otten dictate dissimilar probes. ‘n such cases the differentia! delay should be measured and then mentaly factored in to reduce error when inter- preting the display. itis worth noting that active probes, Application Note 47 Figure 9. Probes with Mismatched Delays Produce Apparent Time Skewing inthe Display ~ 4 Figure 10. Overdriven FET Probe Produces Excessive Waveform Distortion an Tiling, Saturation iets can Also Cause Delayed Response 1 such as FET and current probes, have signal transit times as Jong as 25ns. A fast 10X or 500 probe delay can be inside 3ns, Account for probe delays in interpreting osci- loscope displays. The difficulty shown in Figure 10 is a wildly distorted amplifier output. The output slews quickly, but the pulse topand bottom recoveries have lengthy, taling responses. Additionally, te amplifier output seems to clip wel below its nominal rated output swing. A common oversight is Fesponsible for these conditions. A FET probe monitors the amplifier output in this example, The probe's com= mon-made input range has been exceeded, causing it to overload, clip and distort badly. When the pulse rises, the probe is driven deeply into saturation, forcing internal Circuitry away from normal operating points, Under these Sonditions the displayed pulse top is ilegitimate. When the output falls, the probe's overload recovery is lengthy ‘and uneven, causing the tailing. More subtle forms of FET AT WE AN47-9Application Note 47 probe overdrive may show up as extended delays with no obvious signal distortion. Know your FET probe. Account forthe delay ofits active circuitry. Avoid saturation effects due to common-mode input limitations (typically +1¥). Use 10X and 100X attenuator heads when required. Figure 11’s probe-caused problem results in amplifier ‘output peaking and ringing. In other respects the display isacceptable. This output peaking charactersticis caused by a second 10X probe connected to the amplifier's ‘summing junction. Because the summing point is so central to analyzing op amp operation, it is often mani- tored. At high speed the 10pF probe input capacitance causes a significant lag in feedback action, forcing the amplifier to overshoot and hunt a it seeks the null point. [Minimizing this effect calls forthe lowest possible probe input capacitance, mandating FET types or special passive probes. (Probes are covered in the Tutorial section; also see Appendix A, “ABC's of Probes’, guest written by the engineering staff of Tektronix, Inc.). Account for the effects of probe capacitance, which often dominates its impedance characteristics at high speeds. A standard 1OpF 10X probe forms a 10ns lag with a 1K82 source resistance. igure 11 ec of 210K, 19F ‘Scope Probe a the Sonming Pome? ge A peaked, taling response is Figure 12's characteristic The photo shows the final 40mV of a 2.5V amplifier excursion, Instead ofa sharp comer which sts cleanly, peaking occurs, followed bya lena taling decay. This waveform was recorded with an inexpensive of-brand 410% probe. Such probes are often poorly designed, and constructed from materials inappropriate for high speed work. The selection and integration of materials for wideband probes isa specialized and dificult art. Sub- stantial design effortis required to get good fidelity at high speeds. Never use probes unless they are fully specified for wideband operation. Obtain probes from a vendor you trust. Figure 13 shows the final movements of an amplifier output excursion. Atonly 1mV per division the objective is to view the settling residue to high resolution. This re- ‘sponse is characterized by multiple time constants, non- linear slew recovery and tailing. Note also the high speed event just before the waveform begins its negative going transition. What is actually being seen isthe oscilloscope recovering from excessive overdrive. Any observation that requires off-screen positioning of parts of the waveform should be approached with the greatest caution. Oscillo- scopes vary widely intheirresponse to overdrive, bringing displayed results into question. Complete treatment of high resolution setting time measurements and oscillo- scope overload characteristics is given in the Tutorial section, “About Oscilloscopes” and Appendix. "Measur- ing Amplifier Setting Time”. Approach all oscilloscope Figure 12. Poor Quality 10X Probe introduces T Figur 12. OverrivenOsilascoo Display Says More Abou! the Osutoscope than the Circuit i's Comectedto 8 AN47-10 AT WEARApplication Note 47 Figure 14. instabilities Due to No Ground Plane Produce a Display Simitar toa Poorly Grounded Probe - 62 ‘measurements which require off-screen activity with cau- tion. Know your instrument's capabilities and limitations. ‘Sharp eyed readers wil observe that Figure 14 is a dupli- cate of Figure 6. Such lazy authorship is excusable be- cause almost precisely the same waveform results when ‘no ground plane is in use. A ground plane is formed by Using a continuous conductive plane over the surtace of the circuit board, (The theory behind ground planes is aiscussed in the Tutorial section). The only breaks inthis plane are for the circuit's necessary current paths. The ‘ground plane serves two functions. Because itis flat (AC Currents travel along the surface of a conductor) and Covers the entire area of the board, it provides a way to access a low inductance ground from anywhere on the board. Also, it minimizes the effects of stray capacitance in the circuit by referring them to ground. This breaks up potential unintended and harmful feedback paths. Always Use a ground plane with high speed circuitry. By far the most common error involves power supply bypassing. Bypassing is necessary to maintain low supply impedance. OC resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels. This allows the supaly line to move as internal current levels of the devices connected to it change. This will almost always cause unruly operation Inaddtion, several devices connected toan unbypassed supply can ‘commu ricate” through the finite supply impedances, causing erratic mades. Bypass capacitors furnish a simple way to eliminate this problem by providing a local reservoir of energy at the device. The bypass capacitor acts as an electrical flywheel to keep supply impedance low at high frequencies. The choice of what type of capacitors to use for bypassing is actitical issue and should be approached carefully (se@ Tutorial, “About Bypass Capacitors”). An unbypassed amplifier witha 10022 load is shown in Figure 415. The power supply the amplifier sees at its terminals has high impedance at high frequenoy. This impedance forms a voltage divider with the amplifier and its load, allowing the supply to move as internal conditions in the Comparator change. This causes local feedback and oscil- lation occurs. Always use bypass capacitors. InFigure 16 the 10002 loadis remaved, and a pulse output is displayed. The unbypassed ampliier responds surpris- ingly well, but overshoot and ringing dominate. Always use bypass capacitors. Figure 17's settling is noticeably better, but some ringing remains. This response is typical of lossy bypass capaci tors, or ood ones placed too far away from the amplifier Use good quality, low loss bypass capacitors, and place them as close to the amplifier as possible didi I bi nstbtatdsaussiuaeiiaP 4 iia A) ikl Figure 15. Output ofan Unbypassed Amplifier Driving 2 10002 Load Withot Bypass Capacitors ~ 58 9p Figure 16. An Unbypassed Amplifor Driving No Load is Surprisingly Stable..at he Moment ~ 49 ATW AN47-11Application Note 47 The multiple time constant ringing in Figure 18 often indicates poor grade paralleled bypassing capacitors or excessive trave length between the capacitors. While paralleling capacitors of diferent characteristics isa good way 10 get wideband bypassing, it should be carefully considered. Resonant interaction between the capacitors can cause a waveform like this after a step. This type response is often aggravated by heavy amplifier loading. When paralleling bypass capacitors, plan the layout and breadboard with the units you plan to use in production. ‘SOR = 1600 Figue 17. ining 28 vality Bypass Capacitor Allows Some Figure 19 addresses a more subtle bypassing problem, The trace shows the last 40mV excursion of a SV step almost setting cleanly in 300ns. The slight overshoot is ‘due to a loaded (5000) amplifier without quite enough bypassing. Increasing the total supply bypassing from O.1uF to TuF cured this problem. Use large value paral- leled bypass capacitors when very fast settling is required, particularly ifthe amplifier is heavily loaded or sees fast load steps. Flgue 19. AMre Subtle Bypassing Probl. No-duite- Gand Enough Bypassing Causes a Few Milivol of Peaking =1 Bt Figure 20. 2pF Stray Capacitance atthe Summing Point Introduces Peaking ~4 The problem shown in Figure 20, peaking on the leading and trailing corners, is typical of poor layout practice (see Tutorial section on “Breadboarding Techniques"). This unity gain inverter suffers from excessive trace area atthe ‘summing point. Only 2oF of stray capacitance caused the peaking and ring shown. Minimize trace area and stray capacitance at critical nodes. Consider layout as an inte- gral part of the circuit and plan it accordingly. Figure 21's low level square wave output appears to suffer from some form of parasitic oscilation. In actuality, the disturbance istypical that caused by fast cigital clocking (or switching regulator originated noise getting into critical circuit nodes. Plan for parasitic radiative or conductive paths and eliminate them with appropriate layout and shielding. Figure 22 underscores the previous statement. This out- put was taken from a gain-of-ten inverter with 1kQ input AN47-12 AT WERWORE Figure 21. Clock or Switching Regulator Noise Corrupt Output Due to Poor Layout 3 Figure 22. Output of an X10 Amplifier with 1pF Coupling from the ‘Summing Point to the input. Careful Shielding of the Input Russo Wl Emote he Peed Edges and Ringing 2 BP resistance. it shows severe peaking induced by only 1pF of parasitic capacitance across the 1k resistor. The 502 terminated input source provides only 20mvV of drive viaa divider, but that's more than enough to cause problems, even with only 1pF stray coupling. In this case the solution Was a ground referred shield at a right angle to, and encircling, the 1kQ resistor. Plan for parasitic radiative paths and eliminate them with appropriate shielding. ‘A decompensated amplifier running at too low a gain produced Figure 23's trace. The price for decompensated ‘amplifiers’ increased speed is restrictions on minimum allowable gain, Decompensated amplifiers are simply not stable below some (specified) minimum gain, and no amount of ignorance or wishing will change this. This isa Application Note 47 common applications oversight with these devices, al- though the amplifier neve failstoremind the user. Observe gain restrictions when using decompensated amplifiers. Oscillations also the problem in Figure 24, anditis due to excessive capacitive loading (see Tutorial section on “Oscillation”). Capacitive loading to ground introduces lag inthe feedback signal's return tothe input. f enough lag is introduced (¢.g., a large capacitive load) the amplifier may oscillate. Even fa capactively oadedamplifier doesn't oscilat, is always a good idea to checks response with step testing, I's amazing how close to the edge ofthe cliff you can get without falling off, except when you build 10,000 production units. Avoid capacitive loading. Ifsuch loading is necessary, check performance margins and isolate or buter the load if necessary. Figure 25 appears to contain one cycle of oscillation, The output waveform initially responds, but abruptly reverses direction, overshootsand then heads positive again. Some Figure 23. Decompensated Amplifier Running at Too Law aGain-22 Pm won = sos 00 Figura 24. Excessive Capacitive Load Upsets the ‘Amplifier 185 HH ATER AN47-13Application Note 47 overshoot again occurs, with along tal and a small dip well beforeanon-linear slew returns the waveformto 2eo. Ugly overshoot and tailing completes the cycle, This is certainly strange behavior. What is going on here? The input pulse is responsible for all these anomalies. Its amplitude takes the amplifier outside its common-mode limits, inducing the bizarre effects shown. Keep inputs inside specified common-mode limits at all times. Figure 26 shows an oscillation laden output (Trace B) trying to unity gain invert the input (Trace A). The input's form is distinguishable in the output, but corrupted with very high frequency oscillation and overshoot. In this case the amplifier includes a booster within its loop to provide increased output current. The disturbances noted are traceable to local instabilities within the booster circuit. (See Appendix C, “The Oscillation Problem — Frequency Compensation WithoutTears"). When using output booster stages, insure they are inherently stable before placing theminsidean ampiffr’s feedback loop. Wideband booster stages are particularly prone to device level parasitic high frequency oscilation. Figure 25. input Gammon Mode Ovesrive Geneaies’ 088 Outputs 3 Figure 26 Local Osilaton ina Booster Stage. Frequency is Telly High 172 suo my uf Figure 27. Loop Oslations ina Booster Stage. Note Lower Frequency than Local Oscillations in Previous Example ~ 28 Figure 28. Excessive Souee Impedance Gives Serene But Undesired Response - 6 Figure 27's booster augmented unity gain inverting op amp also oscillates, but at a much lower frequency. Additionally, overshoot and non-linear recovery dominate the waveform’s envelope. Unlike the previous example, this benavior is not due to local oscillations within the booster stage. Instead, the booster is simply too slow to be included in the op amp's feedback loop. It introduces, enough lag to force oscillation, even as it hopelessly tries to maintain loop closure. Insure booster stages are fast enough to maintain stability when placed in the amplifier's feedback loop. The serene rise and fal of Figure 28's pulse isa welcome relief from the oscillatory screaming ofthe previous pho- tos. Unfortunately, such tranquilzed behavior is simply too slow. This waveform, reminiscent of Figure 8's bandlimited response, is due to excessive source imped ange, The high source impedance combines with amplifier input capacitance to band limit the input and the output reflects this action. Minimize source impedance to levels AN47-14 LT WARApplication Note 47 which maintain desired bandwidth. Keep stray capaci- tance at inputs down. TUTORIAL SECTION {An implied responsibility in raising the aforementioned issues is ther solution or elimination. What good sal the rabbe-rousing without suggestions for fixes? Itis in this, spirit that this tutorial section is presented. Theory, tech- niques, prejudice and just plain gossip are offered as tools ‘hich may help avoid or deal with difficuties. As previ ously mentioned, the tutorials appear in roughly the same order as the problems were presented. About Cables, Connectors and Terminations Routing of high speed signals to and fromthe circuit board shouldalways be done with good quality coaxial cable. The cable should be driven and terminated in the system's characteristic impedance at the drive and load points. The driven end is usually an instrument (e.,, pulse or signal (generator), presumably endowed with proper characteris- tics by its manufacturer. tis the cable and its termination, selected by the experimenter, that often cause problems. All coaxial cable isnot the same, Use cable appropriate to the system's characteristic impedance and of good qual- ity. Poorly chosen cable materials or construction meth- ods can introduce odd effects a very high speeds, result- ing in observed waveform distortion. A poor cable choice ‘can adversely effect 0.01% setting in the 100ns-200ns region. Similarly, poor cable can preclude maintenance of even the cleanest pulse generator’s Ins rise timer purity. Typically, inappropriate cable can introduce tailing, rise time degradation, aberrations following transitions, non- linear impedance and other undesirable characteristics, Termination choice is equally important. Good quality BNC coaxial type terminators are usually the best choice for breadboarding. Their impedance vs frequency is flat inthe Herange Adtionaly, heiconststonostes that the (often substantial) drive current returns directly to the source, instead of being dumped into the breadboard's Sens aces cape tee ground system. As previously discussed, BNC coaxial terminators are not simply resistors in a can. Special construction techniques insure optimum wideband response. Figures 29 and 30 demonstrate this nicely. In Figure 29 a tns pulse with 350ps rise and fall times! is ‘monitored ona 1GHzsampling’scope (Tektronix 556 with 1$1 sampling plug-in and P6032 probe). The waveform is, clean, with only a sight hint of ring after the falling edge. This photo was taken with a high grade BNC coaxial type terminator inuse. Figure 30 doesnot share theseatributes. Here, the generator is terminated with a 50 carbon composition resistor with lead lengths of about 1/8 inch. The waveform rings and tails badly on turn-off before finally seting. Note thatthe sweep speed required a 25x reduction to capture these unwanted events HORZ= 25601 Figure 29. 350ps Rise and Fall Times are Preserved by a Good ‘Quality Termination Figure 30 Poor Grade Termination Produces Pronounced ging and Talling inthe GHz Range LT WHER AN47-15Application Note 47 Connectors, such as BNC barrel extensions and tee-type adaptors, are convenient and frequently employed. Re- member that these devices representa discontinuity inthe cable, and can introduce small but undesirable effects. In general itis best to employ them as close as possible to a terminated pointin tesystem. Usein the middle of acable run provides minimal absorption of their mismatch and reflections. The worst offenders among connectors are adapters. This is unfortunate as these devices are neces- sitated by the lack of connection standardization in Wideband instrumentation. The mismatch caused by @ BNC-o-GR874adaptortransitionattheinputofa wideband sampling ‘scope is small, but clearly discernible in the display, Similarly, mismatches in almost al adaptors, and even in “identical” adaptors of different manufacture, are readily measured on a high-frequency network analyzer such as the Hewlett-Packard 4195A2 (for additional wis- dom and terror along these lines see Reference 1). BNC connections are easily the most common, but not necessarily the most desirable, wideband connection mechanism. The ingenious GR874 connector has notably superior high frequency characteristics, as does the type N. Unfortunately, it's a BNC world out there. About Probes and Probing Techniques The choice of which oscilloscope probe to use in a mea- surement is absolutely crucial. The probe must be consid- ered as an inherent part of the circuit under test. Rise time, bandwidth, resistive and capacitive loading, delay and other limitations must be kept in mind. Sometimes, the best probe is no probe at al. In some circumstances it is possible and preferable to connect critical breadboard points direclyto the oscilloscope (see Figure 31). This arrangement provides the highest pos- sible grounding integrity, eliminates probe attenuation, and maintains bandwidth. [n most cases this is mechani- cally inconvenient, and often the oscilloscope's electrical characteristics (particularly input capacitance) will not permitit. Thisis why oscilloscope probes were developed, ‘and why so much effort has been put into their develop- ment (Reference 42 is excellent. In addition to the mate- Nate 2: Amst noone bees nyo this ut hey Set for terse Photos ofthe ntock analyzers splay are’ included in he text sna one wauld lee tem. wouldnt. rial presented here, an in-depth treatment of probes ap- pears in Appendix A, “ABC's of Probes”, guest written by the engineering staf of Tektronix, Inc. Probes are the most overlooked cause of oscilloscope mismeasurement. All probes have some effect on the point they are measuring. The most obvious is input resistance, but input capacitance usually dominates in a high speed measurement. Much time can be lost chasing circuit events which are actually due to improperly se~ lected or applied probes. An 8pF probe looking at a tks2 source impedance forms an 8ns lag — substantially longer than a fast amplifer's delay time! Pay particular attentionto the probe's input capacitance. Standard 10M2, 40X probes typically have 8pF-10pF of input capacitance, with 1X types being much higher. In general, 1X probes are not suitable for fast work because their bandwidth is limited to about 20MHz. Remember that all 10X probes cannot be used with al oscilloscopes; the probe's com- pensation range must match the oscilloscope’s input capacitance. Low impedance probes (with 50092 to 1k®2 resistance) designed for 50 inputs, usually have Input capacitance of 1pF or 2pF. They are a very good choice it you can stand the low resistance. FET probes maintain high input resistance and keep capacitance atthe 1pF level but have substantially more delay than passive probes. FET probes also have limitations on input common-mode range which must be adhered to or serious measurement errors ill result. Contrary to popular belief, FET probes do ‘not have extremely high input resistance — some types areas owas 100kQ. Itis possible to constructa wideband FET probe with very high input impedance, although input ‘capacitance is somewhat higher than standard FET probes. For measurements requiring these characteristics, sucha probe is useful. See Appendix E, “An Ultra Fast High Impedance Probe’. Regardless of which type probe is selected remember that they all have bandwidth and rise time restrictions. The displayed rise time on the oscilloscope is the vector sum of source, probe and ‘scope rise times. ise = Vase SOUTGE)?+ Cage Poe)? + Trase Osciossope)2 ‘This equation warns that some rise time degradation must occur in a cascaded system. In particular, if probe and oscilloscope are rated at the same rise time, the system response will be slower than either. AN47-16 ATHFigure 31. Sometimes the st Probe is No Probe. Direct Connection tothe Osillascope Eliminates a 10X Probe's tenuate Application Note 47 OE eco Arp icia ecten / Possible Grounding Problems in a Sample-Hold (Figure 124 Setting Time Measurement Current probes are useful and convenient.3 The passive transformer-based types are fast and have less delay than the Hall effect-based versions. The Hall types, however, respond at DC and low frequency and the transformer ‘types typically rol off around 100Hz to 1kHz. Both types have saturation limitations which, when exceeded, cause odd results on the CRT which will confuse the unwary. The Tektronix type CT-1 current probe, although not nearly as versatile as the clip-on probes, bears mention. Although this isnot a clip-on device, it may be the least electrically intrusive way of extracting wideband signal information. Rated at 1GHz bandwidth, it produces SmV/mA output with only 0.6pF loading. Decay time constant of this AC current probe is =194/50n, resulting in alow frequency limit of 35kHz Nate 3: A more thorough escusio a curent probes is gven a LTC ‘Aopleation Note 35, “Step Dow Swtchng Regulators, See Reerence 2 Avery special probe i the differential probe. A differential robe may be thought of as two matched FET probes Contained within a common probe housing. This probe literally brings theadvantage of differential input oscillo- ‘scope to the circuit board. The probes matched, active Circuitry provides greatly improved high frequency com- ‘mon mode rejection over single ended probing or even ‘matched passive probes used with a clferential ample. The resultant ability to reject common-mode signals and ‘ground noise at high frequency allows this probe to deliver exceptionally clean results when monitoring small, fast signals, Figure 32 shows a differential probe being used to verify the waveshape of a2.5mV input toa wideband, high gain amplifier (Figure 76 of the Applications section). ‘When using dtferent probes, remember that they all have different delay times, meaning that apparent timing errors ——————— LT NEAR AN47-17Application Note 47 will occur on the CRT. Know what the individual probe delays are and account for them in interpreting the CRT display. By farthe greatest source of errrin probe useis grounding. oor probe grounding cancauseripples and discontinuities inthe waveform observed, In some cases the choice and placement of probe's ground strap wil affect waveforms ‘on another channel. In the worst case, connecting the probe's ground wire wil virtually disable te circuit being measured. The cause of these problemsis due to parasitic inductance in the probe's ground connection. In most oscilloscope measurements this is nota problem, but at nanosecond speeds it becomes critical. Fast probes are always supplied with a variety of spring clips and accessories designed to aidin making the lowest possible inductive connection to ground, Most of heseattachments Figure 32, Using a Ditlerental Probe to Ver assume a ground plane is in use, which it should be. ‘Always try to make the shortest possible connection to ‘ground — anything longer than 1 inch may cause trouble. Sometimes it's dificult to determine if probe grounding is the cause of observed waveform aberrations, One good tests to disturb the grounding set-up and see if changes occur. Nominally, touching the ground plane or jiggling probe ground connectors or wires should have no effect. Ifa ground strap wire isin use try changing its orientation or simply squeezing it together to change and minimize its loop area, any waveform change occurs while doing this the probe grounding is unacceptable, rendering the oscilloscope display unreliable ‘The simple network of Figure 33 shows just how easy it is for poorty chosen or used probes to cause bad results, ‘A9pF input capacitance probe with a4 inch long ground the Integrity ofa 2.5m High Speed Input Pulse (Figure 76's X1000 Amplifier) AN47-18 LT WEARHOR Ou Figure 4. Test Circuit Output with 9pF Probe and 4 Inch Ground Strap etwas Figure 35. Test Circuit Output with 9pF Probe and 0.25 tach Ground Strap strap monitors the output (Trace B, Figure 34). Although the input (Trace A) is clean, the output contains ringing, Using the same probe with a 1/4 inch spring tip ground Connection accessory seemingly cleans up everything (Figure 35), However, substituting a 1pf FET probe (Fig- Ure 36) reveals a 50% output amplitude error in Figure 35! The FET probe's low input capacitance allows a more accurate version of circuit action. The FET probe does, however, contribute its own form of error. Note that the probe's response is tardy by Sns due to delay ints active circuitry. Hence, separate measurements with each probe are required to determine the output’s amplitude and timing parameters. Application Note 47 AA final form of probe is the human finger. Probing the circuit with a finger can accentuate desired or undesired effects, giving clues that may be useful. The finger can be used to introduce stray capacitance toa suspected circuit ‘node while observing results on the CRT. Two fingers, lightly moistened, can be used to provide an experimental ‘esistance path. Some high speed engineers are particu- larly adeot at these techniques and can estimate the capacitive and resistive effects created with surprising accuracy. Examples of some of the probes discussed, along with different forms of grounding implements, are shown in Figure 37. Probes A, B, E, and F are standard types equipped with various forms of low impedance grounding, attachments. The conventional ground lead used on G is ‘more convenient to work with but will cause ringing and PORE one Figure 36. Test Cireut Outpt with FET Probe [1 A 8 oe nn wee Figure 37. Various Probe-Ground Strap Configurations AT WEAR AN47-19Application Note 47 other effects at high frequencies, rendering it useless. H has a very short ground lead. This is better, but can still cause trouble at high speeds. 0 isa FET probe. The active circuitry in the probe and a very short ground connector ensure low parasitic capacitance and inductance, C is a separated FET probe attenuator head. Such heads allow the probe to be usedat higher voltage levels (e.g,+10V or #100V). The miniature coaxial connector shown can be mounted on the circuit board and the probe mated with it This technique provides the lowest possible parasitic inductance in the ground path and is especially recom- mended, lisa current probe. A ground connection is not usually required. However, at high speeds the ground ‘connection may result in a cleaner CRT presentation Because no current flows in the ground lead of these probes, along strap is usually permissible. J's typical of the finger probes described in the text. Note the ground strap on the third finger. The low inductance ground connectors shown are avail able from probe manufacturers and are always supplied with good quality, high frequency probes. Because most oscilloscope measurements do not require them, they invariably become lost. There is no substitute for these devices when they are needed, so itis prudent to take care of them, This is especialy applicable to the ground strap on the finger probe. ‘About Oscilloscopes The modern oscilloscope is one of the most remarkable instruments ever constructed. The protracted and intense development eort put toward these machines is perhaps equaled only by the fanaticism devoted to timekeeping it is a tribute to oscilloscope designers that instruments manufactured over 25 years ago stil surfice for over 90% of today's measurements. The osclloscope-probe combi- ration used in high speed work is the most important equipment decision the designer must make. Ideally, the oscilloscope should have at least 150MH2 bandwidth, but Note 4 In pric, the marine cronomeer recived feroous and Abundant aut of atetin, See References 4, 5, and 6, Foran tol tol rough te history of oscllscope vertical apis, ee Pefeence 3, See also Reeronce 41 Nate: See RppendsD, “Measuring Probe -Osiloscope Response" for complete ets on this use generator. Note 6: This sequen of ahatos was stn my ome lb. sry, but ‘Gia is the fasts ‘ope in my slower instruments are acceptable if their limitations are Well understood. Be certain of the characteristics of the probe-oscilloscope combination. Rise time, bandwidth, resistive and capacitive loading, delay, noise, channel-to- channel feedthrough, overdrive recovery, sweep nonlinearity, triggering, accuracy and other limitations must be keptin mind. High speed linear circuitry demands ‘a great deal from test equipment and countiess hours can be saved if the characteristics of te instruments used are well known, Obscene amounts of time have been lost pursuing “circuit problems” which inrealityare caused by misunderstood, misapplied oF out-of-speo equipment Intimate familiarity with your oscilloscope is invaluable in getting the best possible results with it. In fact, it is Possible to use seemingly inadequate equipment to get (good results ifthe equipment's limitations are well known and respected, All of the circuits in the Applications section involve rise times and delays well above the 10OMH2-200MHz region, but 90% of the development ‘work was done with a SOMHz oscilloscope. Familiarity with equipment and thoughtful measurement technique permit useful measurements seemingly beyond instru- rent specifications. ASOMH2 oscilloscope cannot track a Sns rise time pulse, but it can measure a 2ns delay between two such events. Using such techniques, itis otten possible to deduce the desired information. There are situations where no amount of cleverness will work and the right equipment (e.g, a faster oscilloscope) must be used. Sometimes, “sanity-checking” a limited band- width instrument with a higher bandwidth oscilloscope is all that is required. For high speed work, brute force bandwith is indispensable when needed, and no amount of features or computational sophistication willsubsttute. Most high speed circuitry does not require more than two traces to get where you are going. Versatility and many channels are desirable, but if the budgetis limited, spend for bandwidth! Dramatic ctferences in displayed results are produced by probe-oscilloscope combinations of varying bandwidths. Figure 38 shows the output ofa very fast pulse® monitored with a 1GHz sampling ‘scope (Tektronix 556 with 1S1 sampling plug-in). At this bandwidth the 10V amplitude appears clean, with just a small hint of ringing after the falling edge. The rise and fall times of 350ps are suspi- cious, as the sampling oscilloscope’s rise time is also specified at 350ps.° AN47-20 LT WEARApplication Note 47 Figure 38. A 350ps Rise/FallTime 10V Pulse Monitored on 1GH2 Sampling Oscilloscope. Direct 50: Input Connection is Used Figute 39. The Test Pulse Appears Smaller and Slower On a <350MHz Instrument (te = Ins). Deliberate Poor Grounding Creates Rippling Alter the Pulse Falls. Direct 50:2 Connection Is Used Figure 39 shows the same pulse observed on a 350MHz instrument with a direct connection tothe input (Tektronix 485/500 input). Indicated rise time balloons to tns, while displayed amplitude shrinks to 6V, reflecting this instrument's lesser bandwidth. To underscore earlier dis- cussion, poor grounding technique (1 1/2" of ground lead to the ground plane) created the prolonged rippling after the pulse fal Figure 40 shows the same 350MHz (502 input) ostitlo- scope with a 3GHz 10X probe (Tektronix P6056). Dis played results are nearly identical, as the probe's high bandwidth contributes no degradation. Again, deliberate poor grounding causes overshoot and rippling on the pulse fal Figure 41 equips the same oscilloscope with a 10X probe specified at 290MHz bandwidth (Tektronix P6047). Addi- tionally, the oscilloscope has been switched to its 1MQ input mode, reducing bandwidth to a specified 250MHz. Amplitude degrades to less than 4V and edge times similarly increase. The deliberate poor grounding conti utes the undershoot and underdamped recovery on pulse fall InFigure 42a 100MHz 10X probe (Hewlett-Packard Mode! 10040A) has been substituted for the 200MHz unit. The ‘oscilloscope and its set-up remain the same. Amplitude shrinks below 2V, with commensurate rise and fal times. Cleaned up grounding eiminates aberrations. Figure 40. Test Pulse on the Same 350MH2 Oscilloscope Using a ‘3GHz 10x Probe. Deliberate Poor Grounding Maintains Rippling Residue HOR eat Figure 41. Test Pulse Measures Only 3V High on a 2502 *Seape with Significant Wavetorm Distortion, 250MHz 10X Probe Used LT WEAR AN47-21Application Note 47 Figure 42. Test Pulse Measures Under 2 High Using 250MH2 "Scope and a 100MHz Probe Figure 43. 1S0MHz Oscilloscope (tse = 2.4ns) with Direct Connection Responds tothe Test Pulse HOR Figure 44. ASOMHz Instrument Barely Grunts. 10V, 350ps Test Pulse Measures Only 0.5V High wih Tos ise and Fall Times! A Tektronix 454A (150MHz) produced Figure 43's trace. ‘The pulse generator was directly connected to the input Displayed amplitude is about 2V, with appropriate 2ns edges. Finally, a SOMHz instrument (Tektronix 556 with ‘1A4 plug-in) just barely grunts in response to the pulse (Figure 44). indicated amplitude is 0.5V, with edges read- ing about 7ns. That's a long way from the 10V and 350ps that's realy there! A final oscilloscope characteristic is overload perfor- mance. itis often desirable to view a small amplitude portion of a large waveform. In many cases the oscllo- scope is required to supply an accurate waveform after the display has been driven off screen. How long must one wait after an overload before the display can be taken seriously? The answer to this question is quite complex. Factors involved include the degree of overload, its duty cycle, its magnitude in time and amplitude, and other considerations, Oscilloscope response to overload varies widely between types and markedly different behavior can be observed inany individual instrument. For example, the recovery time fora 100X overload at 0.005V/division may be very different than at 0.1V/division. The recovery char- acteristic may also vary with waveform shape, DC content ‘and repetition rate. With so many variables, itis clea that measurements involving oscilloscope overload must be approacted wit caution. Nevertheless, a simpletest can indicate when the oscilloscope is being deleteriously af- fected by overdrive The waveform to be expanded placed on the screen ata vertical sensitivity which eliminates all off-screen activity Figure 45 shows the display. The lower right hand portion is to be expanded. Increasing the vertical sensitivity by a factor of two (Figure 46) drives the waveform off-screen, but the remaining display appears reasonable. Amplitude has doubled and waveshape is consistent with the original display. Looking carefully, it is possible to see small amplitude information presented asa dip in the waveform at about the third vertical division. Some small disturb- ances ate also visible. This observed expansion of the original waveform is believable, In Figure 47, gain has been further increased and al the features of Figure 46 are amplifiedaccordingly. The basic waveshape appears clearer and the dip and small disturbances are also easier to see. ‘No new waveform characteristics are observed. Figure 48 borings some unpleasant surprises. This increase in gain AN47-22 AT WERApplication Note 47 ‘causes definite distortion, The initial negative-going peak, although farger, has. different shape. Its bottom appears less broad than in Figure 47. Additionally, the peak’s positive recovery is shaped slightly differently. A new Tipoling disturbance is visible in the center of the screen This kind of change indicates that the oscilloscope is having trouble. A further test can confirm that this wave- form is being influenced by overloading In Figure 49 the ‘gain remains the same, but the vertical position knob has Figure 45 Figure 46 Figure 47 been used to reposition the display at the screen's bottom. This shits the oscilloscope's DC operating point which, under normal circumstances, should not affect the dis- played waveform. Instead, a marked shift in waveform amplitude and outline occurs. Repositioning the wave- form to the screen's top produces a differently distorted waveform (Figure 50. It's obvious that fortis particular waveform, accurate results cannot be obtained at this ain Figure 48 Figure 49 Figure 50 Figures 4550. The Overdrive Limit is Determined by Progressively increasing Oscilloscope Gain and Watching for Wavelorm Aberrations AT WEAR AN47-23Application Note 47 Differential plug-ins can address some of the issues associated with excessive overdrive although they cannot solve all problems. Two differential plug-in types merit special mention, At low level, ahigh sensitivity differential plug-in is indispensable. The Tektronix 147, 1A7A and 7A22 feature 10uV sensitivity, although bandwidth is limited to MHz. The units also have selectable high and low pass filters and good high frequency common-mode rejection. Tektronix type 1A5, W and 7A13 are differential comparators. They have calibrated DC nulling(slideback) sources, allowing observation of small, slowly moving events on top of common-mode DC or fast events riding ‘on a waveform, A special case is the sampling oscilloscope. By nature of its operation, a sampling ‘scope in proper working order is inherently immune to input overload, providing essen- tially instantaneous recovery between samples. Appendix 8, "Measuring Amplifier Setting Time”, utilizes this capa- bility. See Reference 8 for additional details, The best approach to measuring small portions of large waveforms, however, is to eliminate the large signal swing ‘seen by the oscilloscope. Appendix B, “Measuring Ampli- fier Settling Time” shows ways to do this when measuring DAC-amplitir settling time to very high accuracy at high speed. In summary, while the oscilloscope provides remarkable capability its imitations must be well understood when interpreting results.” ‘About Ground Planes Many times in high frequency circuit layout, the term “ground plane” is used, most often as a mystical and il defined cure to spurious circuit operation. Infact, there is little mystery to the usefulness and operation of ground planes, and like many phenomena, their fundamental ‘operating principle is surprisingly simple Ground planes are primarily useful for minimizing circuit inductance. They dothisby utilizing basic magnetictheory. Currentflowing ina wire producesan associated magnetic field. The field's strenath is proportional to the current and inversely related tothe distance from the conductor. Thus, ote 7: Adoioraldscouse an osciloscopes wil be found in References 1 and7teough 1 we can visualize a wire carrying current (Figure 51) sur- rounded by radii of magnetic field. The unbounded field becomes smaller with distance, A wire's inductance is defined as the energy stored in the fieldet up by the wie's current. To compute the wire’s inductance requires inte- Grating the field over the wire's length and the total radial areaof the field. This implies integrating on the radiusfrom R= Ry toinfinity,a very large number. However, consider the case where we have two wires in space carrying the same current in either direction (Figure 52). The fields produced cancel. Figure $2. Two Wire Case In this case, the inductance is much smaller than in the simple wire case and can be made arbitrarily smaller by reducing the oistance between the two wires. This reduc- tion of inductance between current carrying conductorsis the underlying reason for ground planes. In a normal circuit, the current path from the signal source through its conductor and back to ground includes a large loop area. This producesalarge inductance fr this conductor which can cause ringing duetoLRCeeffects tisworth noting that 10nH at 1OOMHz has an impedance of 6. At 10mA a 6OmV drop results. ground plane provides a return path directly under the signal cartying conductor through which return current canflow. The conductor's smaliphysical separation means the inductance is low. Return current has a direct path to (ground, regardless of the numberof branches associated with the conductor. Currents will always flow through the return path of lowest impedance. Ina property designed AN47-24 AT WEARApplication Note 47 ground plane, this pathis directly under the signal conduc tor. Ina practical circuit, itis desirable to ground plane one Whole side of the PC card (usually the component side for wave solder considerations) and run the signal conduc tors on the other side. This wil give low inductance path for all the return currents, ‘Aside from minimizing parasticinductance, ground planes have additional benefits. Their flat surface minimizes resistive losses due to AC skin effect (AC currents travel along a conductor's surface). Additionaly, they aid the circuit's high frequency stability by referring stray capaci- tances to ground. ‘Some practical hints for ground planes are: 4. Ground plane as much area as possible on the compo- nent side of the board, especially under traces that operate at high frequency. 2, Mount components that conduct substantial fast rise currents (termination resistors, ICs, transistors, «decoupling capacitors) as closeto the boardas possible. 3. Where common ground potential is important (ie. at ‘comparator inputs), try to single point the critical ‘components into the ground plane to avoid voltage drops. For example, in Figure 53's common A/D circuit, good practice would dictate that grounds 2, 3, 4 and 6 be as close to single point as possible. Fast, large currents ‘must flow through R1, R2, D1 and D2 during the DAC settle time. Therefore, 01, 02, Rt and R2 should be ‘mounted close to the ground plane to minimize their Inductance. R3.and C1 don’t carry any current, so their inductance is less important; they could be vertically Figure $3. Typ inserted to save space and to allow point 4 to be single point common with 2, 3 and 6. In critical circuits, the designer must often trade off the beneficial effects of lowered inductance versus the loss of single point ground. 4, Keep trace length short. Inductance varies directly with length and no ground plane will achieve perfect cancellation About Bypass Capacitors Bypass capacitors are used to maintain low power supply impedance at the point of load. Parasitic resistance and inductance in supply fines mean that the power supply impedance can be quite high. As frequency goes up, the inductive parasitic becomes particularly troublesome. Even if these parasitic terms did not exist, or if local regulation is used, bypassing is stil necessary because no power supply or regulator haszero outputimpedanceat 100MHz. ‘What type of bypass capacitor to use is determined by the application, frequency domain ofthe circuit, cost, board space and many other considerations. Some useful gen- eralzations can be made, ‘A capacitors contain parasitic terms, some of which appear in Figure 54. In bypass applications, leakage and ielectric absorption are second order terms but series R andLare not. These latter terms limitthe capacito’sabilty to damp transients and maintain low supply impedance. Bypass capacitors must often be large values so they can absorb long transients, necessitating electrolytic types which have large series R and L Figure 4, Parasitic Terms of 2 Capacitor LINEA AN47-25Application Note 47 Ditterent types of electrotytics and electroiytic-non-polar combinations have markedly different characteristics. Which type(s) to use is @ matter of passionate debate in some circles and the test circuit (Figure 55) and accom panying photosare useful, The photos show the response of 5 bypassing methods tothe transient generated by the test circuit. Figure 56 shows an unbypassed tine which sags.nd ripples badly atlarge amplitudes. Figure 7 uses an aluminum 10uF electrolytic to considerably cut the disturbance, but there is stl plenty of potential trouble. Atantalum 10uF unit offers cleaner response in Figure 58 and the 10yF aluminum combined with a0.01F ceramic type is even better in Figure 59. Combining electrolytics with non-polarized capacitors is a popular way to get (good response but beware of picking the wrong duo. The right (wrong) combination of supply line parasitics and paralleled dissimilar capacitors can produce a resonant, ringing response, as in Figure 60. Caveat! Breadboarding Techniques The breadboard is both the designer's playground and proving ground. itis there that Realty resides, and paper {or computer) designs meet their ruler. More than any- thing else, breadboarding isan iterative procedure, an odd amalgam of experience guiding an innocent, ignorant, Figure $5. Bypass Capacitor Test Circuit Figure 86, Response of Unbypassed Line Figure $7. Response of 10)F Aluminum Capacitor Figure $8. Response of 10, Tantalum Capacitor, Figure 59, Response of 10.F Aluminum Paralleled by 0.01pF Ceramie ‘Try before Speciying! AN47-26 AT UIAApplication Note 47 explorative spirit. A key is to be willing to try things out, sometimes for not very good reasons. Invent problems and solutions, guess carefully and willy, throw rocks and see what comes loose. Invent and design experiments, and follow them wherever they lead. Reticence to try things is probably the number one cause of breadboards that “don't work’.* implementing the above approach to life begins withthe physical construction methods used to build the breadboard, ‘Anigh speed breadboard must start with a ground plane. Adgitionally, bypassing, component layout and connec- tions should be consistent with high speed operations. Because of these considerations there is a common mis~ conception that breadboarding high speed circuits is time consuming and difficult. This is simply not true. For high speed circuits of moderate complexity a complete and electrically correct breadboard can be assembled in 10 minutes ifall necessary components are on hand. The Key to rapid breadboardingis to identity critica circuit nodes and design the layout to suit them. This permits most of ‘the breadboard's construction to be fairly sloppy, saving timeand effort. Additionally, use all degrees of freedom in raking connections and mounting components. Don't be bashful about bending |.C. pins to suit desired low capaci- tance connections, or air wiring components to achieve sapid or electrically optimum layout. Save time by using components, such as bypass capacitors, as mechanical Note &: A much more doquenty stated version ofthis approzrh is ound In eterone 12 supports for other components, such as amplifiers, It is true that eventual printed circuit construction is required, but when initially breadboarding forget about PC and production constraints. Later, when the circuit works, and is well understood, PC adaptations can be taken care of, Figure 61's amplifier circult is a good working example. ‘This circuit, excerpted from the Applications section (where its electrical operation is more fully explained) isa high impedance, wideband amplifier with low input capaci- tance. 01 and At form the high frequency path, with the 90002-10002 feedback divider setting gain. A2 and 02 close a DC stabilization loop, minimizing OC offset be- ‘ween the circuit's input and output. Critical nodes inthis circuit inolude Q1's gate (because ofthe desired iow input ‘capacitance) and At'sinput related connections (because of their high speed operation). Note that the connections associated with A2 serveat DC and are much ess sensitive tolayout. These determinations dominatethebreadboard's construction, Figure 62 shows initial breadboard construction. The copper clad board is equipped with banana type connec- tors. The connector's mounting nuts are simply soldered tothe clad board, securing the connectors. Figure 63 adds At and the bypass capacitors. Observe that At's leads have been bent out, permitting the amplifier to sit down an the ground plane, minimizing parasitic capacitance. Also, the bypass capacitors are soldered to the amplifier power pins right at the capacitor's body. The capacitor’s lead lengths are returned to the banana power jacks. This connection method provides good amplifier bypassing Figure 61. The Stabilized FET laput Amplifier (Aplications Figure 73) o be Breadboarded LI WEAR AN47-27Application Note 47 Figure 62. The Banana Jacks are Soldered tothe Copper Clad Board whtle mechanically supporting the amplifier. Italsoeimi- nates separate wire runs tothe power pins Figure 64 adds the discrete componentsin the high speed path. A's gate is connected directly to the input BNC, as is the 10MQ resistor associated with A2's negative input Note thatthe end ofthis resistor that sees high frequency is cut very short, while the other end is left uncut. The 90002-1000 divider is installed at At, with very short ‘connections to At’s negative input. At's 10MQ resistor receives similar treatment to the BNC connected 10M unit; the high frequency end is cut short, while the end destined for connection to A2 remains uncut. 02's collec- tor and Q1's source, high speed points, are tied closely together with At’s postive input. Finally, DCamplifier A2andits associated componentsare air wired into the breadboard (Figure 65}. Their DC opera- tion permits ths, while the construction technique makes connections to the previously wited nodes easy. The previously uncommitted ends ofthe 10MG2 resistors may be bent in any way necessary to make connections, All ‘other components associated with A2 receive similar treatment and the circuit is ready for experimentation. Despite the breadboard's seemingly haphazard construc- tion, the circuit worked well. Input capacitance measured a few pF (including BNC connector) with bias current of about 100pA. Slew rate was 1000V/us, with bandwiath approaching 100MHz. Output, even with 50mA loading, \was clean, with no sign of oscillation or other instabilities. Full details on this circuit appear in the Applications section. Additional examples of breadboard construction techniques appear in Appendix F, “Additional Comments on Breadboarding”, AN47-28 AT UNeABConnections and Minimizes Distance to the Ground Plane Once the breadboard seems to work, i's useful to begin ‘thinking about PC layout and component choice for pro- duction. Experiment with the existing layout to determine just how sensitive nominally critical points are. Add con- ‘rolled parasitic terms (e.9., resistors, capacitors and physical layout changes) to test for sensitivity. Gentle touching of suspect points with a finger can yield prelimi- nary indication of sensitivity giving clues that can be quite valuable. In conclusion, when breadboarding, design the bread- board to be quick and easy to build, work with and modity Observe te circuitand istento what tis telling youbefore trying to get itto some desired state Finally, don't hesitate to try just about anything; that’s what the breadboard is for. Almost anything you do will cause some result — 1 is Connected ta Power. Bypass Capacitors Provide Support Application Note 47 ding Ampliter Pins Eases ‘whether it's good orbadisalmostirelevant. Anything you do that enhances your ability to correlate events occurring on the breadboard can only be beneficial Oscillation The rte ofthe operational amplifiers negative feedback Itisfeedback which stabilizes the operating pointand fixes the gain. However, postive feedback or delayed negative feedback can cause oscillation. Thus, a properly function- ing amplifier constantly lives in the shadow of oscillation, When oscillation occurs, several major candidates for blame are present. Power supply impedance must be low. If the supply is unbypassed, the impedance the amplifier sees at its power terminals is high, particularly at high LT WEAR AN47-29Application Note 47 Figure 64. Adcitional High Speed Discrete Companents and Connectors are Added. Note Short Connections at Amplifier Input Pins (Left Side of frequency. This impedance forms a voltage divider with the amplifier, allowing the supply to move as internal Conditions in the amplifier change. This can cause local feedback and oscillation occurs. The obvious cure is to bypass the amplifier. AA second common cause of oscillation is positive feed- back. In most amplifier circuits feedback is negative, although controlled amounts of positive feedback may be used, Inacircuitthat nominally has only negative feedback unintended positive feedback may occur with poor layout. Check or possible parasitic feedback paths and unwanted or overlooked feedback action. Always minimize (to the extent possible) impedances seen by amplifier inputs This helps attenuate the effects of parasitic feedback paths totheinputs, Similarly, minimize exposed inputtrace area Route amplifier outputs and other signals well away from kage). 10M Resistors Uncommitted Ends ae Just Visible sensitive nodes. Sometimes no amount of layout finesse will work and shielding is required. Use shielding only when required — extensive shielding isa sloppy substi- tute for good layout practice, A Tinal cause of oscillation is negative feedback arriving well delayed in time. Under these conditions the amplifier hopelessly tries to servo a feedback signal which consis- tently arrives too late. The servo action takes the form at an electronic tall chase, with oscilation centered around the ideal servo point. The most common causes of this problemare reactive oading ofthe ampifier (most notably capacitive loads such as cable) and circuitry, such as power amplifiers, laced within the amplifiers feedback path. Reactive loads should be isolated from theamplifier’s output (and feedback path) with a resistor or power amplifier. Sometimes rolling of the ampli’ frequency AN47-30 AT LINEARApplication Note 47 Figure 65. D¢ Servo Amplifier is Wired In an Connections to 10M Resistors Complete. This Part ofthe Circuit {is Not Layout Sensitive response wil fix the problem, but in high speed circuits this may not be an option. Placing power gain or other type stages within the amplifier’s feedback path adds time delay tothe stabilizing feedback. Ifthe delay is significant, oscilation commences, Stages operating within the amplifier’ loop must contrib- ute minimum time lag compared to the ampltir’s speed capability. At lower speeds this is not too difficult, but something destined for operation within a 100MHz amplifiers loop must be fast As mentioned before, rolling off the amplifiers frequency response eases the job, butis usually undesirable in a wideband circuit. Every effort should be expended to maximize the added stages band- width before resorting to roll-off ofthe amplifier. In this way the fastest overall bandividth is achieved while main- taining stability. Appendix C, “The Oscillation Problem ~ Frequency Compensation Without Tears", discusses con- siderations surrounding operating power gain and other type stages within amplifier loops. This completes the tutorial section. Hopefully, several notions have been imparted. First, in any measurement situation, test equipment characteristics are an integral part of the circuit. At high speed and high precision this is particularly the case. As such, itis imperative toknow your equipment and how it works, There is no substitute for intimate familiarity with your tool's capabilities and limitations.® {In general, use equipment you trust and measurement techniques you understand. Keep asking questions and Nate: Further expston an A Reference 13. i90n hs points given LT NE AN47-31Application Note 47 don't be satisfied until everything you see on the oscillo- scope is accounted for and makes sense. Fast monolithic amplifiers, combined with the precaution- ary notes listed above, permit fast linear circuit functions hich are dificult or impractical using other approactes. Some ofthe applications presented representthe state-of- the-art for a particular circuit function. Others show simplified and/or improved ways to implement standard functions by utlizing theamplfier'seasily accessed speed. All have been carefully (and paintlly) worked out and should serve as good idea sources for potential users of the device, Have fun. | did APPLICATIONS SECTION | - AMPLIFIERS Fast 12-Bit Digital-to-Analog Converter (DAC) Amplifier One of the most common applications for a high speed amplifier, transforming a 12-bit DAC’s current output into a voltage, is also one of the most difficult. Although an op amp can easily do this, care is required to obtain good dynamic performance. A fast DAC can settle to 0.01% in 200ns or less, but its output also includes a parasitic capacitance term, making the amplifier’s job more difficult. Normally, the DAC's current output is, unloaded directly into the amplifer’s summing junction, placing the parasitic capacitance from ground to the amplifiers input. The capacitance introduces feedback phase shift at high frequencies, forcing the amplifier to hhuntand ring about the final value before setting. Ditfer- ent DACs have different values of output capacitance. CMOS DACs have the highest output capacitance, in the 1009F-150pF range, anditvaries with code. Bipolar DACS typically have 20pF-30pF of capacitance, stable overall Codes. As such, bipolar DACs are almost always used where high speed is required. Figure 66 shows the popular ADSESA 12-bit DAC with an 11220 output op amp. Figure 67 shows clean 0.01% setting in 280ns (Trace B) to an allbits-on input step (Trace A). The requirements for obtaining Trace B's display are not {tivial, and are fully detailed in Appendix 8, "Measuring Ampliier Setting Time”, 2-Channel Video Amplifier Figure 68 shows a simple way to multiplex two video amplifiers onto single 75Q.cable, The appropriate ampli- wes ws} soseek Figure 66, Typical Output Amplifier Coniguration fora | 12-Bi O-to-A Converter A-svon Figure 67. Setting Residue (Trace B for Al Bits Switched On (Trace A) Output is Fully Setied in 280ns, fier is activated in accordance with the truth table in the figure. Amplifier performance includes 0.02% difteren- tial gain error and 0.1° differential phase error. The 750 back termination looking into the cable means the ampli- fiers must swing 2Vp-p to produce 1Vp-p at the cable output, but this is easily handled Simple Video Amplifier Figure 69is a simpler version of Figure 68. Ths a single channel video amplifier, arranged (inthis case) for again of ten, The double cable termination is retained and the circuit delivers a bandwidth of SSMHz Loop Through Cable Receivers Figure 70is another cable related circuit Here, the LT1193 differential amplifier simply hangs across a distribution cable, extracting the signal. Theamplifir's trueditferental inputs reject common-mode signals. As in the previous Hote 1: Auth ein an opamp cru Ett LICH AN47-32 LT WEARApplication Note 47 wos omseeer (ara [eer] our actve Tae Figure 68. 2-Channel Multiplexed Video Ampiiier circuit, dtferental gain and phase errors measure 0.02% and 0.1°, respectively. A separate input permits OC level adjustment DC Stabilization - Summing Point Technique Often itis desirable to obtain the precision offset of a DC amplifier with the bandwidth of a fast device. There are a variety of techniques for doing this, Which method is best is heavily application dependent, so several configura- tions are presented. Figure 71 shows a composite made up of an LT1097 low rift device and an LT1191 high speed amplifier. The overall circuit is a unity gain inverter with the summing ‘node located at the junction of the two tk resistors. The LT1097 monitors this summing node, compares it to ‘ground and drives the LT1191°s positive input, complet- ing aC stabilizing loop around the LT1191. The 100k02- 0.01pF time constant at the LT1097 limits its response to low frequency signals. The LT1191 handles high fre~ quency inputs while the L11097 stabilizes the DC operat- ing point. The 4.7k-2200 divider at the LT1191 prevents excessive input overdrive during start-up. This circuit ‘combines the LT1097’s 35,V offset and 1.5V/°C drift with the LT1191's 450V/us slew rate and 9OMH2 bandwidth, Bias current, dominated by the LT1191, is about 500nA. Figure 69. Double Terminated Cable Driver Figure 70. Cable Sense Amplilir for Loop Through Connections with OC Adjust wea Figure 71. At DC Stailizes A2 by Forcing the Summing Point o Zero AT WEAR AN47-33Application Note 47 DC Stabilization - Differentially Sensed Technique Figure 72s similar o Figure 71, except that the sensing is done differentially, preserving access to both fast ampli- fier inputs. The LT1097 measures the OC error at the L11220'sinputterminals and biasesits offset pinst force offset within SO,V. The offset pin biasing at the LT1220 is arranged so the LT1097 wil always be able to find the ‘ervo point. The 0.01. capacitor rolls off the LT1097 at Yow frequency and the 111220 handles high frequency signals. The combined characteristics ofthese amplifiers yield the following performance: Oftset Voltage ......-50nV Oftset Drift, AuWePe SEW Rate enone 250VIBS Gain-Bandwidth ....a5MHz OC Stabilization - Servo Controlled FET Input Stage Figure 73 shows a wideband, highly stable gain-of-ten with high input impedance. Input capacitance is about 3pF. Q1 and Q2 constitute a simple, high speed FET input buffer. 01 functions as a source follower, with the 02 ‘current source load setting the drain-source channel cur- rent. The LT1223 provides a 100MHz bandwidth gain of ten. Normally, this open loop configuration would be quite drifty because there is no DC feedback. The LT1097 contributes this function to stabilize the circuit. Itdoes this by comparing the fitered circuit output to a similarly filtered version of the input signal. The ampltiedcltfer- ence between these signals is Used to set 02's bias, and hence Q1's channel current. This forces Qt’s Veg to Whatever voltage is required to match the circuit's input and output potentials. The capacitor at A1 provides stable loop compensation. The RC network in A1's output pre- vents it from seeing high speed edges coupled through (2's collector-base junction. This circuit constitutes an extremely wideband (01 does not degrade A2’s 1OOMH2 performance), high input im- pedance amplifier. With an input capacitance of 3pF and 1 —y Figure 72. At DC Stabilizes A2 by Forcing the Otfset Pins to Jace a OV Difference at A2's Inputs Figure 73. At DC Stabilizes the Circll by Controlling Q's Channel Current AN47-34 MT WIRApplication Note 47 bias current of 100A, itis well suited for probing oras an ATE pin amplifier. As shown, gain is ten, but other gains are possible by varying the feedback rato. OC Stabilization - Fult Differential Inputs with Parallel Paths Figure 74 showsa way to getfull differential inputs with DC stabilized operation. Ths circuit combines the output of two differential input amplifies for overall DC corrected wideband operation. At and A2 both differentially sense the input at gains of ten. Wideband AT feeds output amplifier A3 via a highpass network, while the slower A2 contributes DC and low frequency information to A3. A2 does not see high frequency inputs, because they are filtered by the 2k-200pF lowpass networks at its inputs. If the gain and bandwidth of the high and low frequency paths complement each other, A2's output should be an undistorted, amplified version (inthis case x 10) ofthe input. Figure 75 shows this to be the case. Trace A is one side of a differential input applied tothe circuit. Trace Bis AAt's output taken 2t the 5002 potentiometer - 0.001uF junction. Trace C is A2's output. With the AC gain and DC gain match trims property adjusted, the two paths’ contr- butions match up and Trace Dis singularly clean, with no residue, The adjustments are optimized by trimming the AC gain forthe squarest comers and the DC gain match for a flat top. Bandwidth fr this circuit exceeds 36MHz, slew rate is 450V/us and DC offset about 200,V. Note tt: For assistance ‘his deve is ncluded in wing Crcult signal ow, the schema ot igure Figure 75. Waveforms forthe Parallel Path Differential “Amplifier. Trace A isthe Input; B, C and D are the High Pass, Low Pass and Output Nodes, Respectively OC Stabilization - Full Differential Inputs, Gain-of- 1000 with Parallel Paths Figure 76 is a very powerful extension of the previous circuit. Operation is similar, but gain is increased to 1000. Bandwidth is about 35M, rise time equals 7ns and delay isinside 7.5ns. Full power responseis available to 1MHz, with input noise about 15uV broadband. This kind of speed, coupled with full diferentia inputs, the gain of 1000, DC stability, and low cost make the circuit broadly applicable in wideband instrumentation. As before, two differential amplifiers, A1 and A2, simultaneously sense the inputs. In this case A1 isthe popular and economical 592-733 type, operating ata gain of 100.'" A1's differen tial outputs feed output amplifier A3 via 4yF-1kO high ass networks which strip off At’s DC content. A2, a precision DC differential type, operates in similar fashion to the previous circuit, supplying OC and low frequency Figure 74. A Parallel Path DC Stabilized Diferentiat Amplifier. High Frequency Signals Go through At, while A2 Handles OC and Low Frequency. A3 Sums Both Paths LT WEAR AN47-35Application Note 47 ISECTBC wo | E>. “T m AARESSTOR 2 sete Figure 76. A Full Diterental,Paralle! Path Amplifier. Gain is 1000, with 38MHz Bandwidth. Delay is Inside 7.5ns and Rise Time Under ns information to A3 at a trimmed gain of 100. In this case output amplifier A3 is a differential gain block with a ‘nominal committed gain of 10. This change is necessi- tated by At's differential output, which must be single- ended to obtain the circuit's output. As such A2 does not directly apply its low trequency information to A3 as it did before. Instead, Ad measures the difference between A2's output and a divided down portion of A3's output. Ad's output, biasing A3's positive input via the 1k0 resistor, closes a loop around the circuits DC-low frequency path. The divider feeding Ad's negative input is adjusted so that the circuit's DC gain is known and equal to its AC gain. Figure 77 shows the circuit's response to a 60ns, 2.5mV amplitude pulse (Trace A). The X1000 output (Trace B) responds cleanly, with delay and rise time in the Sns-7ns ‘ange. Some small amount of peaking i evident, although itmay betrimmed withthe peaking adjustmentatA1. Figure 78 plots the circuit's gain vs frequency. Gain is flat within 41/248 to 20M, with the~3dB pointat 38M Figure 7's edge peaking shows up here as avery slight gain increase starting around 1MHzand continuing out toabout 15MHz ‘The peaking trim will eliminate this effect. To use this circuit, put in a ow frequency or DC signal of known amplitude and adjust the low frequency gain fora AN47-36 AT WEARApplication Note 47 1000 output after the output has settled. Next, adjust the high frequency gain so that the signat’s front and rear Corners have amplitudes identical to the settled portion Finally trim the peaking adjustment for best setting ofthe | *=0avow output pulse’s front and rear corners. Figure 79 shows input (Trace A) and output (Trace 8) wavelorms with all adjustments properly set. Fidelity is excellent, with no aberrations or other artifacts of the parale! path operation evident. Figure 80 shows the ef- fects of too much AC gain; excessive peaking on the edges with proper amplitude indicated only after the AC channel Figure 79. Response of X1000 Amplifier with Bandwidth transitions through its highpass cut off. Similarly, exces- _Grassover Points Properly Adjusted. A= Input; B= Output sive DC gain produces Figure 81's traces. The AC gain path oR = oY ‘oon re 80. Response of X1000 Amplifier with Excessive AC Gain. = Input; 8 = Output Figure 77. Pulse Response forthe X1000 Differential Amplifier. Fidelity is Quite Good, with Only Sligh Output Peaking (Trace B) ype 1 08e x Figure 81. Response of X1000 Amplifier with Too Much DC Gain, ‘A= Input; B= Output provides proper initial response, but too much DC gain forces along, taling response to an incorrect amplitude. High Speed Ditterential Line Receiver High speed analog signals transmitted on allne often pick Figure 78. Gain vs Bandwidth or the X1000 Diterential Amplitier. Peaking Noted in Figure 77 Shows up as 0.2548 Peak UP Substantial common-mode noise. Figure 82 shows a al SM, Which Could be Trimmed Out simple, fast diferential line receiver using the LT1194 LT WER AN47-37Application Note 47 ‘ee rscio 0} a Figure €2. Simple, Full Differential Line Receiver gain-of-tenitferental ampliter. The diferent lines fed to At. The resistor-diode networks prevent overload and insure input bias for At under all conditions. A's output represents the difference ofthe two line inputtimes again of ten. In theory, all common-mode noise should be rejected. The test circuit shown inthe figure confirms ths. The sinewave oscilator drives T1 (Trace A, Figure 83), producing a differential ine output at its secondary, T1’s secondary is returned to ground through a broadband noise generator, flooding the line inputs with common- mode noise traces Band Care A1's inputs). Trace D, 1's X10 version ofthe differential signal atts inputs, is clean with no visible noise or disturbances. This circuit will easily provide a clean output with DC-5MH2 noise domi- nating signal by @ 100:1 rato. Transformer Coupled Amplifier Figure 84 shows another way to achieve high common- mode rejection, Additionally, this cirouithas the advantage of true 3 port isolation. The input, gain stage, and output are all galvanically isolated from each other. As such, this configuration is useful where large common-mode ditfer- ences are encountered or where ground integrity is Uncertain, At is set up ina simple gain of 11.11 feeds its input, and the output is taken from T2. Figure 85 shows ‘esults for a MHZ input, with all “e" designated trans- former leads referred to ground. The input (Trace A Figure £85) is applied to T1, whose output (Trace B) feeds AT. At takes gain, and its output (Trace C) feeds T2. T2's output Figure 83. Differential Line Receiver Easily Pulls Out a Signal Buried in Common-Mode Noise. Output is Clean, Despite 1001 Noise-to-Signal Ratio AN47-38 LT WEARApplication Note 47 (Trace D) is the circuit's output. Phase shift is evident, although tolerable, T1 and'T2 are very wideband devices, with low phase shift Note the negligible phase diference between the A-B and C-D trace pairs. A1 contributes essentially the entire phase error. Using the transformers specified, the circuits low frequency cut-off is about 10kHz rest cncurs UBT Figure 84, Transformer Coupled Amplifier. Note That At is Galvanicaiy Isolated From Input and Output Nodes 0 Figure 85. Transformer Coupled Amplifier Responds to an Input (Trace A) with A Slightly Phase Shifted Output (Trace O). Traces B and are T1 Secondary and T2 Primary, Respectively Zs our uo S AU RESsTOR Differential Comparator Amplifier with Adjustable Oftset itis often desirable to examine or amplify one particular portion ofa signal while rejectingall other portions. Athigh speed this can be dificult, because the amplifier may see fast, large common-mode swings. Recovery from such activity usually is dominated by saturation effects, making the ampifier’s output questionable. The LT1193's difer- ential ampiiier’s fast overload recovery permits this function, maintaining output fidelity to the input signal ‘Additionally, the input level amplitude at which amplifica- tion begins is settable, allowing any amplitude defined pointto be selected. n Figure 86,A1, the LT1019 reference ‘and associated components form an adjustable, bipolar voltage source which is coupled to differential amplifier 2's negative input. The input signal biases A2’s positive input with 2s gain set by R and R2, in accordance with the equation given, Input signals below A2's negative input levels maintain 2's output in saturation, and no signal is seen at the output. When the positive input rises above the negative input's bias point A2 becomes active, providing an ampli- fied version of the instantaneous difference between its inputs. Figure 87 shows what happens when the output of atriangle wave generator (Trace A) isappliedto the circu. ‘Setting the bias level just below the triangle peak permits high gain, detailed operation ofthe turnaround at the peak. Switching residue in the generator’s output is clearly ‘observable in Trace B. Appropriate variations in the volt- age source setting would permit more of the triangle Figure 86. Fast Diferential Comparator Amplifier wih Setable Offset LI WEA AN47-39Application Note 47 e-o1uow AL 200 ros > Figure 87. The Ditteentil Comparator Signal Detail From a Triangle Waveform’ Generators Switehing Attacts are Clearly Evident slopes to be observed, with attendant loss of resolution due to oscilloscope overload limitations. Similarly, in- creasing A2’s gain allows more amplitude detail while placing restrictions on how much ofthe waveform can be displayed. itis worth noting that ths circuit performs the same function as differential plug-in units for oscllo- soopes. This circuit's output is accurate and settled to 0.1% 100ns after it enters its linear region, Differential Comparator Amplifier with Settable ‘Automatic Limiting and Oftset Figure 88 extends the previous circuit's operation allow- ing amplified observation of information between two settable, amplitude defined points. The amplitude setpoints are settable in both magnitude and sign. In this cirout the polarity of the offset applied to A2's negative input is outer Figure 88. Diterential Comparator Ampliier with Settable Automatic Limiting and Ottset AN47-40 LT WERApplication Note 47 determined by comparator At's output state. A1 com- pares the circuit's input to ground, generating polarity information atts outputs. Level shifters Q1-Q3 and 02-04 bias followers 05 and 06. Positive circuit inputs result in 5 supplying the “Vcompane.” potential to A2, while negative inputs route “VeowpaRe-” to A2. This eliminates the previous circuit's manual polarity switch, permitting automatic selection ofthe diferencing polarity and ampli- tude. Additionally, this circuit takes advantage of A2's input clamp feature. This feature (See LT1194 Data Sheet) limits the dynamic range of the input, clamping the amplifier’s input operating range. Signals inside the clamp limit are processed normally, while signals outside the limit are precluded from influencing the amplifier. This combination of circuit controls allows very tightly defined windows on a waveform to be selected for accurate amplification without overload restrictions. Figure 89 shows the circuit output for a sine input (Trace A) from the same function generator used to test the previous circuit. The V* and V- compare voltages are set just below the sinewave peaks, with “Veigmp" programmed to restrict amplification to the peak's excursion. Trace B, the circuit's output, simultaneously shows amplitude de- tail of both sine peaks. The observed distortion is directly traceable to this generator’s imperfect internal triangle waveform (see Figure 87), as well as its sine shaper characteristics. Ae twev WORE 550" Figure 89, The Automatic Ditferential Comparator Amplifier Finds Triangle Wave and Switching Residuals (Trace in Trace As Peaks Photodiode Amp! Amplification of fast photodiode signals over a wide range of intensity isacommon requirement, Figure 90's fast FET amplifier serves well, giving wideband operation with § er decades of photocurrent. The photodiode is set up in the conventional manner. Photocurrent is fed directly to A1's summing point, using ATs output to move to the level required to maintain virtual ground at the negative input ‘The -15V diode bias aids diode response. The table in the figure details circuit operating characteristics with the diode specified. ‘Some care in frequency compensating this configuration is required. The diode has about 2pF of parasitic capaci- tance, forming a significant lag at A1's summing point. tf No feedback capacitor is used, high speed dynamics are oor. Figure 91 shows circuit response to a photo input (Trace A) with the indicated 3pF feedback capacitor re- moved. A1’s output overshoots and saturates before finally ringing down to final value. In contrast, replacing the 3pf capacitor provides Figure 92's results. The same inputpulse TraceA, Figure 92) producesacleanly damped output (Trace B). The capacitor imposes a 50% speed penalty (nate faster horizontal scale for Figure 92), This is unavoidable because suppressing the parasitic ringing’s relatively low frequency mandates significant roll-off. Fast Photo Integrator Arelated circuit tothe photodiode ampitier is Figure 93's photo integrator. Here, the output represents the integral ofthe diode’s photocurrent over some period of ime. This we g Fy -tewernncnann sonaeoe [reer eon Tone curren “raw asta 700, Suh To. 35 TS Figure 90. A Simple Photodiode Amplifier ATW AN47-41Application Note 47 Circuit is particularly applicable in situations where the total energy ina light pulse (or pulses) must be measured. The circuits a very fast integrator, with $1 used asa reset switch, $2, switched simultaneously with S1, compen- sates S1's charge injection error. With the control input (Trace A, Figure 94) low and no photocurrent, $1 isclosed and At looks like a grounded follower. Under these condi- tions A1’s output (Trace C) sits at OV. When the control input goes high, A1 becomes an integrator as soon as S1 ‘opens. Due to switch delay, this occurs about 150ns after the control input goes high. When $1 opens it delivers some parasitic chargeto A1's summing pont. $2 provides compensatory charge based pulse at A1's positive terminal to cancel the effects of S1's charge error. This action shows up asa fast, small amplitude event in At's ‘output wich settles rapidly back to OV. Figure 92. Figure 90 Respanding witha Feedback Capacitor Lcurrur ca arse pee Figure $3. A Very Fast Photo Integrator. $2 Compensates Reset Switch S1's Small Charge Injection Figure 94. The Photo Integrator Acquires (Trace C) an Input Light Putse (Trace B) with the Control Line (Trace A) inthe Run Mode. Charge Cancellation Action is Evident at Trace C's 400ns Point AN47-42 AT HEAApplication Note 47 At this point in time the integrator is ready to receive and record a photo pulse. When light falls on the photodiode (Trace B triggers alight pulse seen by the photodiode) At responds by integrating. Inthis case At's outputintegrates rapidly until the light pulse ceases. At's voltage afer the light event is overs related to the total energy seen by the diode during the event. A monitoring A-D converter can acquire A1’s output. In typical operation the control line returns low, resetting A1 unti the next event is to be integrated. With only 10pF ot integration capacitor, the circuit has an ‘output droop rate of about 0.2V/qs. This can be increased, although integration speed will suffer accordingly. Inte- gration times of nanoseconds to milliseconds and Dphotocurrents ranging from nanoamperes to hundreds of rmicroamperes are accommodated by the citcuitas shown, Thus, light intensities spanning microwatts to milliwatts over wide ranges of duration are practical inputs. The primary accuracy restrictions are A1's 75pA bias current, its 12V output swing and the effectiveness of the charge cancellation network. Typically, full-scale accuracy of sev- eralpercentis achievableifthe charge cancelation network is trimmed. To do this, assur thatthe diode sees no light while repetitively pulsing the contro line. Adjust the trim- mer capacitor for OV output at At immediately after the disturbance associated with the S1-S2 switching settles. Fiber Optic Receiver simple high speed fiber optic receiver appears in Figure 95. At, a photocurrent-to-voltage converter similar to Figure 90, feeds comparator A2. 2 compares At’ output g ior = 250h5008 S ovreur $f -Hreowcut ‘iaesH4o Figure 95. A Simple Fiber Optic Receiver WOR 20 Figure 96. Wavetorms forthe Simple Fiber Optic Receiver. At (Trace B) Lags the Input (Trace A), but Output (Trace C) i Cle to aDC level established by the threshold adjust setting, producing a logic compatible output. Figure 96 shows typical waveforms. Trace A is a pulse associated with a photo input. Trace B is A1's response and Trace C is A2's ‘output. The phase shift between the photo input and A2's utputis due to A1’s delay in reaching the threshold evel. Reducing the threshold level will help, but moves opera- tion closerto the noise floor. Additionally, the fixed thresh- old level cannot account for response changes in the emitter and detector diodes and fiber optic line over time and temperature. 40MHiz Fiber Optic Receiver with Adaptive Trigger Receiving high speed fiber optic data with wide input ‘amplitude variations is not easy. The high speed data and uncertain intensity ofthe light level can cause erroneous results unless the receiver is carefully designed. Figure 97 addresses the previous circuit's limitations, offering sig- nificant performance advantages. This receiver wil reli- ably condition fiber optic inputs of up to 4OMHz with input amplitude varying by >40d8. Its digital output features an adaptive threshold trigger which accommodates varying signal intensities due to component aging and other causes. An analog output is also avalable to monitor the ‘detector cutput. The optical signal is detected by the PIN photodiode and amplified by A1. second stage, A2, gives further amplification. The output ofthis stage biases a 2- way peak detector (@1-04). The maximum peaks stored in 02's emitter capacitor, while the minimum excursion is retained in Q4's emitter capacitor. The DC value of A2's ‘output signal's mid-point appears at the junction of the 5000F capacitor and the 22MQ units. This point will always sit midway between the signal's excursions, re- LT NEA AN47-43Application Note 47 resronour con | $00 yeseureon ae F Converter The LT1016 and the LT1122 high speed FET amplifier combine to form a high speed V ~> F converter in Figure 121. A variety of circuit techniques are used to achieve a ‘Hz to 10MHz output. Overrange to 12MHZ (Vy = 12) is provided. This circuit has a wider dynamic range (1400B ‘or 7 decades) than any commercially available unt. The JOMH full-scale frequency is 10 times faster than cur- rently available monolithic V —*Fs. The theory of operation is based on the identity Q = CV. sesenonce YO MENAL Fue ier Figure 121. 1H2-10MHzV-to-F Converter. Linearity is 0.09% with SOppmi-C Drift AN47-54 AT MEREach time the circuit produces an output pulse, it feeds backs fixed quantity of charge (Q) toa summing node (3) The circut’s input furnishes a comparison current at the summing node. The difference signal at the node is integrated in a monitoring amplifier’ feedback capacitor. Theamplifer controls he circuit's output pulse generator, completing a feedback loop around the integrating ampli- fies. To maintain the summing node at 2e70, the pulse generator runs at a frequency which permits enough ‘charge pumping 0 offsetthe input signal. Thus, the output frequency will befnearly related tothe input votage. At is the integrating amplifier 0.05uV/°C offset drift pertormance is obtained by stabiliz- ing At with A2,a chopper stabilized op amp. AZ measures the DC value ofthe negative input, compares it to ground, ‘and forces the positive input to maintain offset balance in At. Note that A2 is configured as an integrator and cannot see high frequency signals It functions only at DC and low frequency. ‘At is arranged as an integrator with a 68pF feedback ‘capacitor. When a positive voltage is applied to the input, A1’s output integrates in a negative direction (Trace A, Figure 122). During this period, C1's inverting output is low. The paralleled HCMOS inverters form a reference voltage switch. The reference voltage is established by the LM134 current source driven .T1034's and the 03-4 ‘combination. Additionally, a small input voltage related term is summed into the reference, improving overall circuit linearity. A3-A4 provides low drift buffering, pre- senting a low impedance reference to the paralleled inverter’s supply pin. The HCMOS outputs give low resis- tance, essentially errorless switching, The reference witch's output charges the 15pF capacitor via Q1’s path. When A1's output crosses 2e°0, Ct’s inverting output goes high and the reference switch (Trace B) goes to ground. This causes the 15pF unit to dispense charge into the summing node via 02's Vee. The amount of charge dispensed is a direct function ofthe voltage the 18pF unit was charged to (Q = CV). Qt and Q2 are temperature compensated by 03 and O4 in the reference string. The currentthrough the 15pF unit (Trace C) reflects the charge pumping action. The removal of current from A's sum ming junction (Trace D) causes the junction to be driven very quickly negative. The initial negative-going 15ns Application Note 47 A-osv0w cezonaow Figure 122. 1OMH2 V-to-F's Operating Wavetorms. LT1122 Integrator is Completely Reset in 60ns. transient at A1's output is due to amplifier delay. The input signal feeds directly through the feedback capacitor and appears at the output. When the amplifier finally responds, its output (Trace A) slew limits as it attempts to regain control ofthe summing nade. The class A 1.2kG2 pull-up and the RC damper at A1's output minimizes erroneous output movement, enhancing this slew recovery. The amount of time the reference switch remains at ground ‘depends on how long it takes At to recover and the SpF- 10002 hysteresis network at C1. This 6Ons interval is long ‘enough for the 15pF unit to fully discharge. After this, C1 changes state, the reference switch swings positive, the Capacitor is recharged and the entire cycle repeats. The ‘frequency at which this oscillation occurs is directly re- lated to the voltage-input-derived current into the sum- ming junction. Any input current will require a corre- ‘sponding oscillation frequency to hold the summing point at an average value of OV. Maintaining this relationship at megahertz frequencies places severe restrictions on circuit timing. The key to achieving 10MHz full-scale operating frequency is the abilty to transmit information around the loop as quickly as possible, The discharge-reset sequence is particularly critical and is detailed in Figure 123. Trace A is the At integrator output. Its ramp output crosses OV at the first left vertical graticule division. A few nanoseconds later, 1's inverting outout begins to rise (Trace B), switching the reference switch to ground (Trace C). The reference switch begins to head towards ground about t6ns after AAt's output crosses OV. 2ns later, the summing point (Trace D) begins to go negative as current is pulled from it through the 15pF capacitor. At 25ns, C's inverting ee AT WEAR AN47-55Application Note 47 uncaienne = 0svoww Figura 123, Detail of 60ns Reset Sequence (Whoosh!) outputis fully up thereference switohisat ground, andthe summing point has been pulled to its negative extreme, Now, At begins to take control. Its output (Trace A) slews rapidly in the positive direction, restoring the summing point. At 60ns, A1 isin control ofthe summing node and the integration ramp begins again. Start-up and overdrive conditions could force At's output to go to the negative rail and stay there. The AC-coupled nature ofthe charge dispensing loop can preclude normal operation and the circult may latch. The remaining HCMOS inverter provides a watchdog function for tis condition If AA's output ails negative the reference switch ties to stay af ground. The remaining inverter goes high, liting A's positive input. This causes AT's output to slew positive initiating normal circuit action. The 1k-1 uF combination and the 10M-inverter input capacitance limit start-up loop bandwidth, preventing unwanted outputs. ‘The LM134 current source driving the reference string has a built in 0.33%)°C thermal coefficient, causing slight voltage modulation in the 03-04 pair over temperature. This small change (~ +120 ppnv°C) opposes the—120ppm/ °C drift in the 15pF polystyrene capacitor, aiding overall circuit tempco. Totrim this circuit, apply exactly 6V atthe input and adjust the 2k2 potentiometer for 6.000MH2 output. Next, putin exactly 10V and trim the 20k unit for 10.000MHz output. Repeat these adjustments until both points are fixed. A2’s low drift eliminates a zero adjustment. If operation below 600H2 is not required, A2 and its associated components may be deleted Linearity of this circuit is 0.03% with full-scale drit of ‘50ppmi°C. Zero point error, controled by A2, is 0.05Hz/°C. 8-Bit, 100ns Sample-Hold Figure 124 shows a simple, very fast sample-hold circuit. ‘This circuit will acquire a +5V input to 8-bit accuracy in 400ns. Hold stepisinside 1/4 LSB with hold settling inside 25ns. Aperture timeis ns and droop rate about 1/2LSB/us. ‘The inputis ed toa Schottky switching bridge viainverting buffer At. The Schottky bridge, similar to types used in sampling oscilloscopes'®, gives ins switching and elimi- nates the charge pump-through that a FET switch would contribute. The switching bridge's output feeds output amplifier A2.A2, configured as an integrator, i the actual hold amplifier. its output is fed back to the switching bridge's input, forming a summing point with At’s output resistor. This feedback loop places the bridge within a loop, enhancing accuracy. ‘The bridge is switched by driving the sample-hold input line. Q1 and Q2 drive L1's primary. L1's secondaries provide complementary drive to the bridge with almost no time skewing, Figure 125 shows the circuit acquiring a full scale ste. Trace Ais the input command while Trace Bis A2’s output. The aberration visible in A2's output when switching into hold (hold step) is due to minute residual AG imbalances in the bridge. Figure 126 studies this effect in high resolu- tion detail, with the hold step trim deliberately discon- nected. After A2's output nominally settles at final value, the circuit is switched into hold. The bridge imbalance allows a small parasitic charge to be displaced into A2’s summing point, causing A2 to step 10mV higher (in this case). Ifthe trim is connected and propery adjusted, it supplies a small compensatory charge during switching, Figure 127 shows the effect of this on the output. The settled hold output is the same as the acquired value. To ‘rimthis circuit, groundthe input while pulsing the sample- hold control ine. Next, adjust the trim for minimal ampli- tude step between the sample and hold states, In contrast to low frequency sample-hold circuits this design cannot pass signal if eft in the sample mode. The ‘transformer’ inherent AC coupling precludes such opera~ tion, Similarly, extended sample mode duration (.9., >500ns) will cause transformer saturation, resulting in erroneous outputs and excessive Q1-02 dissipation. If Note 16: See Reece 7, 8 ano 28 AN47-56 LT UINEARPf nor wares0 2 HOR =a Figure 125. Fast Sample-Hold Acquiring a Full-Scale Input extended logic high durations are possible at the control input, it should be AC coupled, 16ns Current Summing Comparator Figure 128 shows a way to build a high speed current ‘comparator with resolution in the 12-bit range. Current comparison, the fastest way to compare D — A outputs and analog values, is commonly used in hgh speed A— D Converters and instrumentation. A1 is set up as a Schottky bounded amplifier. The bound diodes prevent AY from Application Note 47 Figure 126. Hold Step with Mis-Adjusted Compensation saturating due to excessive summing point overdrive, aiding response time. The 3pF capacitor, atypical value, compensates DAC output capacitance and is selected for best amplifier damping. The 10k feedback resistor, also typical, is chosen for best gain-bandwidth performance. Voltage gains of 4 to 10 are common. Figure 129 shows performance. Trace A, a test input, causes A1's output (Trace B) to slew through zero (screen center horizontal line). When At crosses zero, C1's input biases negative and it responds (C1’s output is Trace C) 10ns later with a AT NEA AN47-57Application Note 47 Figure 127. Hold Sip with Property Adjusted Compensation $e -neso.20 el Figure 128, Fast Summing Comparator TTL output. Total elapsed time from the test input arriving ata TTL high until the comparator output achieves @ TTL high is inside 15ns. ‘SOMHz Adaptive Threshold Trigger Circuit Figure 130isan extremely versatiletrigger circuit. Design- ing a fast, stable trigger is not easy and often entails a considerable amount of discrete circuitry. This circuit reliably triggers from DC-S0MHz overa2mV-300mV input range with no level adjustment required A, a gain of ten preamplifier, feeds an adaptive trigger comtiguration identical tothe one described in Figure 97's. fiber optic receiver. The adaptive trigger maintains the AS ‘output comparators trip point at 1/2 input signal ampli- tude, regardless ofits magnitude. This insures reliable automatic triggering over a wide input amplitude range, even for very low level inputs. As an option, the network shown in dashed lines permits changing the trip thresh- ‘ld. This allows any point onthe input waveform edge to be selected as the actual trigger point."” Figure 131 shows performance for a 40MHz input sine wave (Trace A). A's output (Trace B) takes gain and the AA3 comparator gives a clean logic output (Trace C).Atthe highest frequencies, any bandwidth limiting in At isirel- evant; the adaptive trigger threshold will simply vary ratiometrically to maintain circuit output Fast Time-to-Height (Pulsewidth-to-Voltage) Converter The circuit of Figure 132 allows very short pulsewidth (in this case 250ns full-scale) to be determined to a typical accuracy of 1%, Digital methods of achieving similar results dictate clock speeds of 1GHz, which is cumber- some, In addition, processor based approaches using averaging techniques require repetitive pulses which this circuit does not. Circuits of this type are frequently re- 4uired in automatic test equipment and nuclear and high energy physics work where determination of short pulsewidths is a common requirement. The circuit functions by charging a capacitor during the period of a pulsewidth. When the pulse ends, charging ceases and the voltage across the capacitoris proportional to the width of the pulse. Figure 129, Fast Summing Comparator's Wavetorms. Total Delay is 151s. ote 17; Ths tetniqu i crowed rom osiloscopetigner eres. See Reference 29 AN47-58 ATERApplication Note 47 ose Tr csv WOR oN Figure 131, The Trigger Responds fo a 40M Input. Input ‘Amplitude Variations from 2mV-300mV Have No Effect The input pulse to be measured (Trace A, Figure 133) simultaneously biases the 74C221 dual one shot and 3, 3, aided by Baker"® clamping, capacitive feedforward and optimized DC base biasing, turns off in afew nanosec- (onds, Current source Q2's emitter forward biases and 2 Note 18: See Reterence 45 supplies constant currentto the 100pF integrating capaci- tor. Q1 supplies temperature compensation for 02, with the 2.5V LT1009 referencing the current source. 02's collector (e.9., the 100pE capacitor) charges in ramp fashion (Trace 8). At supplies buffered output (Trace C). When the input pulse ends, 03 rapidly turns on, reverse biasing 02's emitter and turing off the current source. AAt’s voltage is directly proportional to the input pulse width. A monitoring A —> D converter can acquire this data After atime set by the 746221's RC programmed delay, a pulse appears a its 02 output (Trace D). This pulse turns on 04, discharging the 100pF capacitor to zero and readying the circuit for the next input pulse This circuit's accuracy and resolution are crucially depen dent on minimizing delay in switching the Q1-02 current source. Figure 134 provides amplitude and time expanded versions of critical circuit waveforms. Trace Ais the input pulse and Trace B is A1's input, showing the beginning of ‘theramp'sascent. Trace C,A1'soutput, showsabout 13ns delay from At's input. Traces O and E, At's input and ee LT NEAR AN47-59Application Note 47 f= mus « Fez einen 7 pura fe fe woe] yeas Figure 192, Fast Time-o-Height Converter HOR 700 Figure 133, Time-to Converter Acquires a 250ns Pulse ‘output respectively, record similar At delays for ramp turn-off. The photo reflects the extremely fast current ‘source switching; the vast majority of delay is due to A's delay. At’s delay is far less critical than current source switching delays; At willaways settle to the correct value well before the one shot resets the circuit. In practice, a ‘monitoring A ~> D converter should not be triggered until about 50ns after the circuit's input pulse has ceased. This ives At plenty oftime to catch upto the 100pF capacitor’s settied value. unc e HOR 0600 Figure 134. Detail of Time-to-Height Converte's Ramp Switching ‘Asmentioned, current source switching speedis essential for good results. Figure 135 details current source turn oft. Trace Ais the circuit's input pulse rising edge and Trace B shows the top of the ramp. Turn off occurs in a few nanoseconds. Similarspeedis characteristic ofthe input's falling edge (current source turn on). Additionally, itis oteworthy that circuit accuracy and resolution limits are set by the difference in current source turn on and off delays. As such, the effective overall delay is extremely small AN47-60 AT NeeAs2v0v (wala Figure 135. Current Source Turn-OM Detail fo the Time-to- Height Converter Tocalibratettis circuit, putina250ns width pulse and trim the 1k potentiometer for 10V output. The circuit will convert pulse widths from 20ns to 250ns to a typical accuracy of 1%. The 20ns minimum measurable width is due to inability to fully discharge the 1009F capacitor. If this is objectionable, 4 can be replaced with a lower saturation device or At's output can be offset True RMS Wideband Voltmeter Most AC RMS measurements use logarithmic techniques tocompute the waveform’s RMS value. This method limits bandwidth to below 1MHz and crest factor performanceto about 10:1. Practically speaking, a waveform's AMS value is defined as its heating value in the load. Specialized instruments employ thermally based assemblies that com pute the RMS value of the input. The thermal method provides substantially improved bandwidth and crest fac- torcapabilty comparedtologarithmically based converters. Thermal RMS-DC converters are direct acting, thermo- electronic analog computers. The thermal technique is explicit, relying on first principles. The simple operation permits wideband performance unattainable with implicit, indirect methods based on logarithmic computing. Figute 136 shows a classic scheme for implementing a thermally based RMS-DC converter. Here, the DC ampli- fier forces a second, identical, heater-sensor par to the same thermal conditions as the input driven pair. This differentially sensed, feedback enforced loop makes am- bient temperature shifts a common-mode term, eliminat- ing their effect. Also, although the vottage and thermal Application Note 47 interactionis non-linear, the input-output voltage relation ship is linear with unity gain. The ability of this arrange- ment to reject ambient temperature shifts depends on the heater-sensor pairs being isothermal. Ths is achievable by thermally insulating them with a time constant well below that of ambient shifts. If the time constants to the hheater-sensor pairs are matched, ambient temperature terms will affect the pairs equally in phase and amplitude. The DCamplifer will reject this common-mode term. Note that, although the pairs are isothermal, they are insulated from each other. Any thermal interaction between the pairs reduces the system’s thermally based gain terms. This would cause unfavorable signal-to-noise pertormance, limiting dynamic operating range. Figure 136's output is linear because the matched thermal pair's non-linear voltage-temperature relationships cancel each other. Figure 136. Conceptual Thermal RMS-DC Converter ‘The advantages of this approach have made its use popu- lar in thermally based RMS-DC measurements. Typically, the assembly is composed of matched heater resistors, sensors and thermal insulation. These assemblies are relatively large and expensive to produce. Figure 137’s economical wideband thermally based voltmeter is based on a monolithic thermal converter. The LT1223 provides gain, and drives the LT1 088 RMS-DC thermal converter,'9 ‘TheLT1088's temperature sensing diodes are biased from the supply. A1, set up as a diferential servo amplifier with ‘again of 9000, extracts the diode’s difference signal and biases 01. 01 drives one of the LT1088's heaters, com- Dleting aloop, The 3300pF capacitor givesastable roll-off. Note 18: Complete detas on his device anda ascusion on thermal fonverson considerations ae found in Relerence 40 LT nee AN47-61Application Note 47 rut 7 ses ys WSU FORSDA RANGE Figure 137. Wideband True RMS Voltmeter ‘The 1.5M-0.022uF combination improves setting by re- ducing gain during output slew. The LT1088's square-law thermal gain means overall loop gain is lower for small inputs. Normally, this would result in slow settling for values below about 10%-20% of scale. The LT1004 1k-3k networks a simple breakpoint, boosting amplifier gain in this region to improve setting. A2, a gain trimmable output stage, serves to compensate for gain variatons in the two sides of the LT1088, To trim the circuit, putin abouta 10% scale DC signal (e9.,0.05V), Adjust the zero trim so that Vor = Vin. Next, apply a full-scale OC input and set the fullscale trim to that value at the output Repeat the trims unl both are fied well within 1% of fll scale, An alternate trim scheme involves applying no input, grounding Q1's base and setting the ero trim uni AA's outputs active, Then, unground Qt's base, apply a full-scale input and trim the full-scale adjustment for that value atthe output Figure 138 is a plot of error vs input frequency. The LT1088is specified at 2% to 10OMHz (5002 heater) or 1% to 20MHz (25002 heater). As such, most of the error showin is due to bandwidth restrictions in A3, but perfor- mance is stil impressive, The plots include data taken at various input levels into both heaters. ASOOmV input into 2500 dips to 1% at 8MHz and 2.5% at 14MHz before peaking badly beyond 17MHz. Thisinput level forces a9.5 Vaws Output at A3, introducing large signal bandwidth limitations. The 400mV input to the 25082 heater shows essentially flat results to 20MHz, the LT1086's 2500 heater specication limit The 500 heater provides significantly wider bandwidth, although A3's SOMA output limits maximum input to about 100mVays (1.76Vaus atthe LT1088). AN47-62 AT WER= lightest g pete Eo} "sane PIC hecaee SEEERRRR Figure 198, Accuracy Plot forthe RMS Voltmeter APPLICATIONS SECTION IV - MISCELLANEOUS CIRCUITS RF Leveling Loop Figure 137’s wideband AC conversion can be applied in other areas, A common RF requirement to stabilize the amplitude of a waveform against variations in input, time ‘and temperature. Instruments and transmitters requentiy require this function, which isnot easy if waveform purity ‘must be maintained. Figure 139A shows a 25MHz RF leveling loop. The RF input is applied to the ADS39 wideband multiplier. The multilier’s output drives At t's outputis converted to DC by the LT1088 based RMS- OC converter (see previous circuit). A servo amplifier compares this output with a settable DC reference and biases the multiplier’s control channel, completing aloop. The 0.33uF capacitor provides frequency compensation by rolling off gain ata frequency well below the response of the LT1088 servo, The loop maintains the output's, ‘25MHzRMSamplitude atthe DC reterence’s value. Changes in load, input, power supply and other variables are rejected. Figure 1398, a similar circuit, offers significantly lower ‘cost although performance is not quite as good. The RF input is applied to LT1228 At, an operational transconductance amplifier. A's output feeds LT1228 AA2, acurrent feedback amplifier. A2's output, the circuit's output, is sampled by the A3 based gain control configu- ration. This arrangement, similar to the gain control loops described in Figures 112 and 114, closes a gain control loop back at A1. The 4pF capacitor compensates rectifier Application Note 47 diode capacitance, enhancing outputflatness vs frequency. A'S Iser input current controls its gan, allowing overall ‘outputlevel control. This approach to RF leveling is simple and inexpensive, although output drift, distortion and regulation ae somewhat higher than in the previous circuit. Voltage Controlled Current Source Figure 140 shows a voltage controlled current source with ‘oad and control voltage referred to ground. This simple, powerful circuit produces output current in accordance with the sign and magnitude of the control voltage. The circuit's scale factoris st by resistor R. At, biased by Viy, Arives current through R (in this case 100) and the load AA2, sensing ctferentially across R, closes a loop back to AA1. The load current is constant because A1’s loop forces a fixed voltage across R. The 2k-100pF combination sets roll off and the configuration is stable. Figure 141 shows, dynamic response. Trace A is the voltage control input while Trace Bis the output current, Response is quick and clean, with delay of Sns and no slew residue or aberration, High Power Voltage Controtied Current Source Figure 142s identical to the basic current source, except that it adds a 1A booster stage (adapted from Figure 104) for increased output power. Including the booster inside AAt’s feedback loop eliminates its DC errors. Note thatthe booster's current limiting features have been removed, because of this circuits inherent current imiting nature ot operation. Figure 143 shows this circuit's response to be as clean as the lower power version, although delay is about 20ns slower. It is worth mentioning that the loop stablty considerations involved in placing A2 and the ‘booster in At's feedback path are significant. This circuit receives treatment in Appendix C, “The Oscillation Prob- lem - Frequency Compensation Without Tears”. 18ns Circuit Breake Figure 144 shows a simple circuit which will turn off current ina load 18ns after it exceeds a preset value. This circuit has been used to protect integrated circuits during developmental probing and is also useful for protecting expensive loads during trimming and calibration. The ircuit's versatility is enhanced because one side of the load is grounded. Under normal conditions, Q1's emitter (Trace A, Figure 145, is Q1’s current, and Trace C is its ————————— AT NEAR AN47-63Application Note 47 —tefeorraa, si Figure 1398. Simple RF Leveling Loop ANA7-64 AT WNELRApplication Note 47 vod Aeasvaw Figure 141. Dynamic Response of the Current Source. Delay is Figure 140. Fast, Precise, Voltage Controlled Curent Souree 4 4s, with Clean Setting with Grounded Loa Figure 142. High Power, Wideband Voltage Controlled Current Source AT WEAR AN47-65Application Note 47 voltage) is biased on, supplying power to the load via the 4092 current shunt, Differential amplifier A1's output re- sides below comparator A2's voltage programmed trip pointand Q2is off. When an overload occurs, 01's emitter current begins to increase (Trace A, just prior to the third vertical division). At’s output (Trace B) begins to rise as it tracks the increase in the 100 shunts voltage. The 9k-1k dividers keep At inputs inside their common-mode range. ‘Simultaneously, 03's emitter voltage (Trace C) begins to dropasit betalimits. When A1'sversion oftheload current exceeds A2's trip point, A2 (Trace D) goes high, turning on 02. 02'sturn on steals Q1'sbase drive, turning off theload 1+ pu Reston Figure 143. 1A Pulse Response ofthe High Power Current Source \yrou me per saUheS ls Figure 14, 18ns Circuit Breaker with Voltage Programmable Trip Point Figure 145. Operating Wavetorms forthe 18ns Circuit Breaker. Cireuit Output (Trace 6) Is Shut Down 18ns After Output Current (Trace A) Begins to Rise current. Local positive feedback at A2’s latch pin causes it to latch in this off state. When the load fault has been Cleared, the pushbutton can be used to reset the circu The delay from the onset of excessive load current 10 ‘complete shutdown isinside 18ns. The 4ns delay of Trace A's current probe should be factored in when interpreting waveforms, To calibrate this circuit, round Q2's base and install a 250mA load, Adjust the 2000 trim for a 2.5V output at A1. Next, remove the load, unground Q2's base and press the reset button. Finally, put in the desired trip set voltage and the circuit is ready for use. AN47-66 ATWREFERENCES 1 10, 1" 12 13, Orwiler, Bob, “Oscilloscope Vertical Amplifiers”, Tektronix, Inc., Concept Series. (1969) Williams, Jim, “Techniques and Equipment for Cur- rent Measurement”, AppendixC, in°Step Down Switch- ing Regulators”, Linear Technology Corporation, Ap- plication Note 35. (August 1989) Addis, John, “Fast Vertical Amplifiers and Good Engi- neering”, in Analog Circuit Design: Art, Science and Personalities, Butterworths, (1991) Brown, Lloyd A., “The Story of Maps” pp. 226-240. Little, Brown. Boston, Massachusetts. (1949) Willsberger, Johann, “Clocksand Watches”, Dial ress. (1975) Mercer, Vaudrey, "John Arnold and Son —Chronom- eter Makers 1762-1843", Antiquarian Horological Society, London. (1972) Tektronix, Inc., “Type 181 Sampling Plug-In Operat- ing and Service Manual”, Tektronix, inc. (1965) Mulvey, J., “Sampling Oscilloscope Circuits”, Tektronix, Inc., Concept Series. (1970) Williams, Jim, “About Probes and Oscilloscopes", Appendix, in “High Speed Comparator Techniques”, Linear Technology Corporation, Application Note 13 (April 1985) Williams, Jim, “Evaluating Oscilloscope Overload Per- formance”, Box Section A in “Methods for Measuring Op Amp Settling Time", Linear Technology Corpora- tion, Application Note 10. (July 1985) Wiliams, Jim and Huffman, Brian, “Instrumentation {for Converter Design”, Appendix. in "Some Thoughts on 0C-DC Converters”, Linear Tectinology Corpora- tion, Application Note 29, (October 1988) Gilbert, Barrie, “Where Do Little Circuits Come From” in Analog Gircuit Design; Art, Science and Personali- ties, Butterworths. (1991) Wiliams, Jim, “Should Ohm's Law Be Repealed?”, in Analog Circuit Design; Art, Science and Personaites, Butterworths. (1991) Application Note 47 14. Wiliams, Jim, “Methods for Measuring Op Amp Set- ting Time”, Linear Technology Corporation, Applica- tion Note 10. (July 1985) 15. Demerow, R., “Setting Time of Operational Amplif- ers", Analag Dialogue, Volume 4-1, Analog Devices, Inc. (1970) 16, Pease, R.A., “The Sublleties of Setting Time", The ‘New Lightning Empiricist, Teledyne Philbrick. (June 1971) 17. Harvey, Barty, “Take the Guesswork Out of Setting ‘Time Measurements”, EDN. (September 19, 1985) 18. Addis, John, “Sampling Oscilloscopes", Private Com- munication. February, 1991) 19. Williams, Jim, “Bridge Circuits ~ Marrying Gain and Balance”, Linear Technology Corporation, Application Note 43. (June 1990) 20, Meacham, LA., “The Bridge Stabilized Oscillator’, Bell System Technical Journal, Vol. 17, p.574. (cto ber 1938) 21, Hewiett, Wiliam R., "ANewType Resistance-Capacity Oscillator’, M.S. Thesis, Stanford University, Palo Ato, California, (1939) 22, Hewlett, Wiliam R., U.S, Patent No. 2,768,872. Janu- ary 6, 1942) 23, Bauer, Brunton, “Design Notes on the Resistance- Capacity Oscillator Circuit”, Parts | and Il, Hewlett Packard Journal, Hewlett-Packard. (November, De- cember 1949} 24. Black, H.S., “Stabilized Feedback Amplifier”, Bell Sys- tem Technical Journal, Vol. 13, p.1. (January 1934) 25. Tektronix, Inc., Type 111 Pretrigger Pulse Generator Operating and Service Manual, Tektronix, nc, (1960) 26. Analog Devices, Inc., “Linear Products Databook", AD834 Datasheet, pp. 6-43 to 6-48. (1988) 27. Analog Devices, Inc., “Multiplier Application Guide", Analog Devices, Inc. (1978) AT ee AN47-67Application Note 47 28. Hewlett-Packard, “Schottky Diodes for High-Volume, LowGost Applications”, Application Note 942, Hewlett- Packard Company. (1973) 29, Tektronix, Inc., “Trigger Circuit ~ Peak-Peak Auto- matic Operation", Model 2235 Oscilloscope Service Manual, Tektronix, Inc. (1983) 30. Wien, Max, “Measung der induction constanten mit dern Optischen Telephon’, Ann. der Phys., Vol.44, pp. 704-707. (1891) 31. Dostal,J., “Operational Amplifiers", Elsevier. (1981) 32. Philbrick Researches, “Applications Manual for Op- erational Amplifiers”, Philbrick Researches. (1965) 33. Sheingold, D.H., “Analog-Digital Conversion Hand- book’, Prentice-Hall. (1986) 34, Bunze, V., "Matching Oscilloscope and Probe for Better Measurements", Electronics, pp. 88-93. (March 1, 1973) 36, Williams, Jim, "High Speed Comparator Techniques”, Linear Technology Corporation, Application Note 13, (April 1985) 36. Morrison, Ralph, “Grounding and Shielding Tech- niques in Instrumentation”, 2nd Edition, Wiley Interscience. (1977) 37. Hewlett-Packard, “Threshold Detection of Visible and Infra-Red Radiation with PIN Photodiodes”, Applica- tion Note 915, Hewlett-Packard Company. Note: This application note was derived froma manuscript ‘originally prepared for publication in EDN Magazine. 38. Roberge, J.K., “Operational Amplifiers: Theory and Practice”, Wiley Interscience. (1975) 39. Ott, Henry W., “Noise Reduction Techniques in Elec- tronic Systems”, Wiley Interscience. (1976) 40. Wiliams, Jim, “A Monolithic 1C for 10MHz RMS-DC Conversion”. Linear Technology Corporation, Appli- cation Note 22. (September 1987) 41, Lee, Marshall M.,“Winning With People: The First 40, Years of Tektronix’, Tektronix, Inc, (1986) 42, Weber, Joe, “Oscilloscope Probe Circuits”, Tektronix, Inc., Concept Series. (1969) 43. Chessman, M, and Sokol, N., “Prevent Emitter-Follower Oscillation’, Electronic Design 13, pp. 110-113, (21 June 1978) 44, DeBella, G.B., “Stability of Capacitively-Loaded Emit- ter Followers ~ a Simplified Approach”, Hewlett- Packard Journal 17, pp. 15-16. (April 1966) 45, Baker, RLH., “Boosting Transistor Switching Speed”, Electronics, Vol. 31, pp. 190-193. (1957) 46. Williams, Jim, "Max Wien, Mr, Hewlett and a Rainy Sunday Afternoon”, in Analog Circuit Design: Art, Science and Personalities, Butterworths. (1991) AN47-68 AT WERApplication Note 47 APPENDIX A ‘ABC's of Probes ~ Tektronix, inc. This appendix, quest written by the engineering staff of through any Tektronix sales office or call 800-835-9433 Tektronix, Inc, isa distillation oftheir booklet, “ABC's of ext. 170. For excellent technical background on probe Probes”. The complete booklet is available, at no charge, theory see Relerence 42. PART |: UNDERSTANDING PROBES The vital fink in your Fisk of Equipment Damage: the scape-prabe systems 300MHe measurement system oundenitedosnpwes,ene Observed reste so isee signa load and one ground, ne mr could cause havoc in ine-operated Probes connect the measurement . testpomntsina DUT Govice ones fequipment. i the "ground" wire fs tesifiothe nousot snosciioscope. __alachedoany elevated signalin g line-operated equipment, various “Achieving opimized system per. formance depends on selecting ine gFees of damage wil result simply Dope probe oryourinessucmet because bath he Scapa andthe equipment are (or shouldbe) on he same three-wire cullel system, ana short-circul continuity is completed Though you could connect a scope and DUT with usta wire, this ‘simplest of connections would not let trough one common ground, youroalze he full canabiites ofyour _, Performance Considerations: Hee By esame ken, spre AES the ae te aes peer an mean agate eee ce. ancelitatons assocted wih Sstemertresit,puscostydoays eng oa weesto tartar tho es signal othe scope. croutioadng ue 1-2 shows what happen Sngsusceptby ogo pup. the samo ign hers aceossos i Gircuit Loading: This suoject wi ‘wo 2meler angi o hookup Why not use a piece of wire? be tectane ih aera ine’ eacing tMohm tne scope cuitloading by te test equipment input eeistanee) and about 20 pe Good question: There are lagi (Bcope-probe} is a combination of (hotsope ht cantare Bus mate reasons for using a pecs o Tesstance andeapactiance Without the say capactanee ol fre mes) wie of, More correctly, two pieces of the bene Observed risetime has slowed to 10 wre, Some ln bandvwid Scopes "See and the tansiot response of and special purpose pug-n Vico under fet (OU) wa ‘heayslemnas become unusable, amples ony evowde badna post fe stope nut resanes) and ‘Susceptibility to External Pick- inputteminals, so hey oferacon. mare ran tp ploslara up: An unshielded piace of wie venentmeans(otatactingwresol chs hey seage pt stisasananernala nope of va enh. late capacitance plus the stray external fields, such as ne frequency DC levels associated wit battery Capacitance ofthe nookap Wie ererenee, electrical noise tan operated equpment coud be mea ° furesson lampa: ao gators and ‘ured. Low frequen) (audi) eignals from the same equipment could leo be examined. Some high output traneducers could also be mon tored, However this ype af cannec- tion should be kept away from line= ‘operated equipment fortwo basic reasons, safely and risk of equip= ment damage Safety: Altachrnent of hookup wires to Ine-operated equipment ‘could impose a health nazard, ether ‘because the "hot side of the ine itself could be accessed, 0 because internally generated hgh voltages Could be contacted, Inboth cases, signal rom nearby equipment ‘These signals are pot any ryectes mothe seope along vth the wanted Signal but can also be jected into ‘nedevice under tet (OUT tsa “Ihe source mpedance of the OUT has ainajer elles on he tvel of interference egnals developed in the wre A very lw soures impedance vouldiondtoshumt any Wchiced vollages fo groune, but high fe query signals could st appear atthe scope input and mask ne wanted signal The answer, of Course, ito use a praae whic in Figure tt the hookup wie offers virtually No Figure 11 shows what areal adaiton tots other features, o- operator poteston, ether al the worl” signal fom a 500 oFmm vides coal teldng of he center eeuipront source orate scopes mpedancecoutcalooks me when Sonductor and vital mination binding posts. joaded by a 10M chm, 10 pF probe: Pickup. AT WEAR AN47-69Application Note 47 Figures Figure 1-3 shows what alow level ignal from ahigh impedance Source (100m ram TOOK ahr) oaks like when accessed by a 300MH2 sscape-probe system. Loading is. YOMchm and 10 pF Thisisaitue representation of he signal, except that probe resisive loading has 1e- duced the ampitude by about 1%: the observed high frequency noise is. ppartof he sgnai at ne high impe- dance test point and would notmaly be removed by using the BW (bandwicth rit button on the scape (See Figure 1-4) Piguet Ut we fook atthe sare test point wih our pieces of wie, two things happen. The ampitude drops due to the ncteased resisive and capac: te loaaing, and nase s added to the signal Because the hookup we is completely unshielded. (See Figure -5) Most the observed noise is tine frequency interterence from fuores- centlamps inthe test area Probably he most anngying effect cof using hookup ware to observe high frequency signals is its unpredicta billy Any touching or rearrangement ol the leads can produce cifferent Snd nonrepeatable elfects on the observed display igus Benefits of using probes [Nota probes are alike and, for any spectic appiicabon, there is no ‘one ideal probe; but they share Common features and functions that areciten taken for granted Probes are convenient. They bringa scopes vertical amplifier toa ‘rout, Without a probe, you would tether need fo pick up a Scope and attach tte a crcut. or pickup the rout and attach iio the scope. Properly used, probes are conver lent flexible and safe extensions Probes providea solid ‘mechanical connection. § probe fp, whether tsa ctp ora tine sold pin, makes contac at ust the place you want io examine. Probes help minimize loading. Yo aceftainextent, al probes load the ce othe signal you Sul, probes offer the Best means of mak ine connec: lions needed. A simple prece of wie, as we have ust seen, would severely toad the OUT infact, he DUT might Stop functioning altogether. Probes are designed to minirize loading. Passive, nor-attenuating 1K probes offer the highest capactive fading of any probe ype—even these, Rowever, are designed (0 kegp loading as low as possible Probes protect a signal rom external interference. Avire Con ection, as described earlier. in ‘dion fo loading the circu, would act as an antenna and pick up stray sighals Such as 60H2 power, CBers, radio and TV stations. The scope would display these stray signal well as the signal of interest rom the our Probes extend a: signal amplitude-handling ability. Bo Sides reducing capaciive and resis tive loading. a standard passive 10X (ten times attenvation) probe ex tends the on-screen iewabalty of signal amplitudes by a factor of fen ‘Atypical scope minimum sens: tity 8 8Vidivsion. Assuming an sight-cvision vertical gratcule, a % probe (or adirect connection) would allow on-screen viewing of 40V p-p tum. The standard {0X passive probe provides 400V p-p viewing. Folowing te sameline, a 100X probe should allow 4kVon-screer ‘iewng. However, most 100X prot fara rated at 1 5KV Tolimit power issipation inthe probe set, ‘Check the specs. Bandiwicth is the probe spectication most users look a frst, but plenty of other fea tures also help to determine which (Obs ight for your application Grreut ioacing, signal aberrations probe dynamic range, probe dime Sions, environmental degradation land greund: path effects wil alm. ine probe selection probe characteristics that your ap Blication requires. you wil achieve Successtul measurements and de- five ful benetit from the instrument apabiines youhave at hand, How probes affect your measurements robes affect your measurements by loading te creult you are exam: ining. The loading etfect is generally Slated in terms of impedance at Some spect frequency, andis made up of a combination of esie: tange and capactance ‘Source impedance. Obviously sourea impedance wil have alarge impact anithe nat affect of any Speciic probe loaaing. For example, 2 device under test wth ana’ 260 utput impedance would not be affected in txmns of amplitude or Fsetime to any significant degree by the use ofa typical 10x passve probe. However tne same probe Connected fo ahigh impedance test pin, such as the collector of a {ransstoy, could affect the signal in terms of fisetime (= 0}, the output of the generator would be limted by the AN47-70 AT NERApplication Note 47 associated resistance and copa Glance dt genet The inlegation network produces an cuiputrse tme equ t922FC Tis imtaton dered tom the uve taltime-contiant cure oa apantor Figur -6 shows ne lect of ior soute esstance ans Capsotancs on he esate rbot Arno tme cen thectput Teeima bo aster han SoC org ensee ifatypcal prope susestomes uretn signal the probes specien inputeapastaree and esetance aided the croutes shown Figure 7 Because he probes toM orm restance a nscn grater nant generat: Sovm caput es ree can be gnored figure ta snows couhalert cites othe generatr ans probe, Spping nes SMC forma aga 3 actual ete has slow om 22nSec (034 nec Percentage change Inrisetime yy 228101 223 me due to the added probe tip. ‘capacitance: Another way of estimating the affect of probe tip capacitance ona Source is to take the rato of probe tip capacitance (marked on ine probe: ‘Compensation box) othe known or estimated source capactance, Jang the same values: “To summarize, any added capacitance sions the source rise- time when using high impedance passive probes In geneval the (greater the attenuation ratio, the Tower the tip capacitance Here are TekronaPBIOGA TekronaPotosa X10 Tekrora:P600? 100, 2a Capacitive Loading: Sinewave. When probing continuous wave (CW) signa’s the probes capactive reac- tance a the operating frequency ‘ust be taxon into account “The total impedance, as seen at the probe tip, s designated Bp and 's a function of frequency, In adition {othe capaciive and resistive ele- ments, designed.in inductive 8 iments serve to offset he pure Ccapacive loading to some degree Pewee fae ewes g co a pe Powe Curvas showing typcainputim edance vs aquenGy. pica Xp Sd Fp requeney are nuded nh ‘ros erone probe suction ‘ranuais gure 9A shows the {ypeal naut mpedance and pace ‘elabonship vs feauancy of te Tek tron P6200 Active Probe. Note hat the 0 AA inex mpedance sare taeda alos 1h by care dasign ofthe sociated ese Capactwo and naucive errors Figure 138 shows a pot Xp anc pve requoney or atyoea 10 la Bacowe probe Te dated Ie 06) Srows capactive reactance vote, qr: Tot cag © sean Sisot by cael denn atthe as80- Gated AC and Celornots It you do not have ready acces the information and need worst. ‘case guide to probe loading, use the following formula: 2" Faro 197 apace reactance chi) er cempeneaton bax) For exampie, a standard passive toM ohm probe wih a tip capac. tance of 11 pF wil have a capaciive reactance (Xp) of about 280 0hm at Sov Depending, of course o souree impedance, this loading Could have a major eltecton Pe LT NEAR AN47-71Figure +98. Typical nput impedence erequene forthe Ystrons P08 Fre 98. Xpand Ro ve Frequency fora ‘ype Passive Probe signal ampitude (by simple dvi action), and even onthe operation of the orca fot Resistive Loading. Fo al prac tical purposes, a 10% 10M orn, passwe probe as ite effect on to- Sayscrcuiry interns ofresisive toading.nonever they 30 carry 8 trade-off i ors of relative gh ‘capactve leading as we have prewously discussed Low Z Passive Probes. Low passive probe ofers very low tip apace ate epence ote. thyely high resistvo loading. A‘ypical 40x 's0 oh? probe nas aninput © of about pF and aresisive leading 91800 obvn: Figure 1-10 snows the Sout and equivalent mode of ts ype ot probe “This Configuration forrns a high frequency 10X votage sige Cause, rom transmission ine they, aithat the 450 ohn tp resistor “Soes' locking into tne cables pate 80 ohm resistance, oC ork Eomponent No ow frequoney co pensation is necessary Decals is fete capacte due tow Z pres fare ypealy nan bandaigt (Up 108 8GHz and reetimes to 100 pS) land ae best suted or making roe lime and vensi-time measurements. ‘They can, Fowevoralfectine pulse amplitude by sispo esstve divcer action between fre source andthe icad (probe). Because of is resistive Ioading eects, hetype o! pote AN47-72 performs best on 50 ohn or lower Impedance circus under test ‘Note also that hese probes oper ateinto 50 ohm scope inputs ony, ‘They are typically teamed up with jas (600M to 1GH2) real ime ‘Scopes oF with scopes employing the sampling pine pie. Blas-Offset Probes. 4 Bias (Offset probe is @ special ind of Low Z design with the capabilty of pro viding ayarabie bas or oft vo tage atthe probe tip. Bias/Offset probes like the Tok svonix P6230 oF P6231 are use for probing high speed ECL cieuity, ‘where resistive loading could upset the operating pomt, These special 1008s are uly described in Bares: under Advanced Probing “The Best of Both Worlds. For the loregonng,itcan be seen that the totally “non-invasive” probe does nat ‘exist However, one type of probe comes close —the ace probe. ‘Aciive probes are discussed in the Tutorial section, butin (General, they provide low resistance jaading (10M ofr) ath very Tow capactveloaaing (1 to 2 pF). ‘They do have trade-offs mterms of limted dynam range, bur under the rgnt conditions, do indeed offer the best of Both words Bandwidth. Sandwich is the pointon an anpltude versus fre ‘quency curve where the measure ment system's down 38 from a starting (reference) level. gure 1-11 ‘shows a lypical response curve of an ‘osclloscope system, ‘Scope vertical ampiiiers are de. signed fora Gaussian rol-af at the high end fa ciscusson ol Gaussian response s beyond the scope of tis, primar, With is type of response, fisetime is approxtmatey related to bandwidth by tne folowing equation: aetin (nanceeconas) a Bano OE) Itisimportant to note that he measurement system 6 ~ 308 (30%) {ow in armpitude athe spectied Sancwatn it Figure 1-12 shows an expanded portonet tne ~d9 area, he hos Fontal scale shows the input re tuency deraing factor necessary to Sbtainacouracie bettar han 0% fora specie bandwith scope For ‘xarale, wath no derating, 00M" scope wil have up toa 0% ampitude ere at 100M (10 nthe graph). Irth scope sto have Sn amplitude accuracy batter than 38. he put requency must be inten to Sbout SOMME (TOON X 3). Coos reose re bi bf) ee a Powe 10 ure ee LT LNEARApplication Note 47 Fo making ampltude measure ments wit ataspecicre. quency, choose a Scope wih a least ‘Bur ites the spectieg banowidth aga general ue of thumb Probe Bandwidth Al probes are ranted by BandwethIn ns tespect thay aro ke scopes or other arp thet are rankedby band- wil Inthese cases we appy the Scquae 001 fhe sum of the squares {oimula to obian the system se time This forma sates tat Passive probes donot olow this ‘ule and should not be included in the square foot ofthe sum ofthe Sauaros formula Tettorx rome @ prabe band wicth ranking system that specties the bandwieth (equency Tange) in wich the probe perlorms wins Spectiog mis. These mts nets ‘Beal aboeratons, seme and ‘Swept bandwalh ath the souroe and he measurement system shall be Spectiod whes Gheckng probe Speatations (see Tet Metnods, Tispage). i geet Ten scoMa probe provides 100M perform nce "3d8) when used on 2 corn. patible j00MH2 scope inohe ‘Wotds, provides fl scope band width atthe probe tip. However not all prose/scope systems car folow ts general rule blero he sdeber, "Scape Bandwidth atthe Probe Tp Figure V9 shows exaripes of Tektenix Scopes and tne recom. mmanded passive probes “Test Methods: wih all speci calons, matching est methods must Beempoveso obtan spectiod perlornare Inthe case of band twdh and risetme measurements. ISessertal to connect the probe toa propery terminated source. Tektronx Species a 50 on source term Ratedin S0.ohm, malong Bs 425 Gin soutoe mpedance Further. More the probe mut oe connected {othe souroe vas proper probe tp {BNC adaptor igure 1-6) Fue 18 shows an equrvalent creat atypical setup. The as” played nselime shoud be a.35 See Srtaser Pique 16 shows an equivalent ci culo ypical passive probe con nected to 2 source fe — Application Note 47 1V.32. After an instrument has ben uly assembled «tra somponents wl be foun onthe Bench W232. Hermete yal wil leak be exceeded V2. Any safety factor wt a a result of practical V3. Manufacturers sc sets wil be incorrect by sfactorof0.5 oF 20, depending on which multiplier pves the most optimistic value. For salesmen’ claims these factors willbe 0.1 oF 100, V4. Ina instrument of device characterized by 3 ‘number of pus-or-minuseror the otal ero wil be the Sum ofall errors adding i he eam ditecton 'V.S. In any given price estimate, com of equipment wil exceed estimate bya factor of 32" V.6. In specications, Murphy's Law supersedes ons. mental sonlions wail always Retenencest {11H Cohen Roun Anessa communica. {EP Sian, eyen paises, {alk ‘Sucker, WeringhossSomondct pve comm 1) ee Totes 19) A Rotel, Wir Pove priate commnaion U0] P Mach oes {aS Froud, inca Comm (1s) LeVine Tet Irments pre sommuniaion, UUs) Toner Sena, private communes {19} A. de ta Lasta, SBD Sytem private commumestion tao) * bu AN47-131Application Note 47 | a (= WISH This App Kote Went As Fast &S Ute AmphPevs) IS AN47-132 LT HEAR| { | \R Application Note 48 TECHNOLOGY November 1991 Using the LIC Op Amp Macromodels Getting the Most from SPICE and the LTC Library Watt Jung INTRODUCTION This application note is an overview discussion of the Linear Technology SPICE macromodel library. Itassumes litte if any prior knowledge of this software library or its history. However, itdoes assume familiarity with both the analog simulation program SPICE (or one of its many derivatives), and modem day op amps, including bipolar, JFET, and MOSFET amplifier technologies. ‘Some Preliminary SPICE Facts of Lite Inthe past few years, SPICE simulations have realy begun to capture a high level of attention on the part of analog circuit designers. Perhaps this is due to more affordable high performance computers, or perhaps the time for simulation is now upon us. In any event, the bottom lines that IC vendors are now making macromadels for opamps available to their customers. Forthe analog circuit designer, there can be no better fate {or simulations, viewing this situation in terms of which model to use. Designers no longer need worry about whether the third party supplier’s model can really cutit. Speaking in terms of the ultimate potential, no one can know an actual part better than the people who designed and produced it, thats the original source IG vendor. The only possible caveat to this scenario is that the vendor supplying an op amp model needs to fully understand not only the real part, but they must also understand SPICE and modeling issues. Without both types of understand ing firmly in place, the user can end up with areal partthat ‘works well and a model which doesn't. For such a case, simulation will be of little value; simulation runs to verity circuit performance won't match the actual part's bench performance, Fortunately, this type of problem seems to be diminishing, Ifthis werenot so, the rapid increase in ttention to models ‘would not be taking place. However, alls not necessarily peacetul bliss for analog designs, and yes, we sil need to actually build breadboards to check out circut designs in the lab. The go-go project managers may say “Simulateit, vwe don't have time to fool withthe breadboard and hand- bul prototypes.” Rarely willhisramrodapproach beatruly wise move, now or in the future, except in specialized circumstances. ‘While it is certainly true that we are in the age of comput- ers, andthat they really doaid our tasks in many ways, that is simply not enough for all cases. SPICE (or any simula- tion tool) can only act upon the information fed into it to analyze a circuit. Model quality issues set aside for the moment, can you honestly say that you have fully suffi- cient characterization data for every single relevant con- nection point/load that your circuit will ever see? Do you understand al/of the parasitic issues it will face? Ifyou can say yes toa ofthese, then maybe all that you needis just 4 good op amp model, and SPICE. More likely, there will alvays be some uncertainties, so breadboarding wil re- main the only advisable choice for relatively complex circuits, particularly those never built before. This then leaves a question of model quality and degree of functionality to be answered. Are the presently available models enough? Just how far can they be trusted for the types of simulations that are to be performed? Hopefully, ‘most ofthese answers will be more apparent by the end of this note, as it contains many different examples. Never- theless, no IC vendor (or other model supplier) is likely to ever stand up and say, “We guarantee this model when used with simulator ABC, and the simulated performance will be within X% of the actual part connected within a corresponding circuit.” Jan EEE LT WEAR AN48-1Application Note 48 Forget it, SPICE simply doesn’t work that way, and likely never will, What SPICE is good for is predictive analysis, worst case limit testing, design feasibilities, etc. But even then it will always have limitations; it wil never be any better than the information fed to it, and obviously this impacts macromodelsas wells allother circuit elements. Thismay soundat first likea questionable reward, but bear in mind just how you can do a worst case design perfor- ‘mance limit for a board with several dozen components. Traditionally, this has been not only dificult, it very often didn’t get done at all (except by production line “hot patches"), Logically then, IC manufacturers offering macramodels place caveats and performance limitations on them, which should be understood by the user. These ‘caveats don't make the models at all useless, but they do define the nature and extent of what they can achieve. The following model disclaimer is typical, and is excerpted ‘rom the LTC model library “This library of macromodels is being supplied to LTC usersas an aid to circuit designs. While the models reflect reasonably close similarity to corresponding devices in performance terms, their use is not suggested as a re- placement for breadboarding. Simulation should be used ‘asa forerunner or a supplement to traditional lab testing. Users should very carefully note the following factors regarding these models: Model performance in general wil reflect typical baseline specs for a given device, and certain aspects of performance may not be modeled fully. While reasonable care has been taken i their preparation, we cannot be responsible for correct application on any andallcomputer systems. Modelusersare hereby notified that these models are supplied as is, wth no direct or implied responsibility on thepartof LTC for thir operation within customer circuit or system. Further, Linear Tech= nology Corporation reserves the right to change these ‘models without prior notice. Inall cases, the current data sheet information for a given real device is your final design guideline, and is the only actual performance guarantee. For further technical infor- ‘mation, refer to individual device data sheets. Your feed- backand suggestions on these (and future) models willbe appreciated!” So, perhaps the first thing to understand about SPICE op ‘amp macromodelsis that they invariably come with cave~ als. Such are the op amp macromodel facts of lf. But, like many other things in design engineering, an op amp macromodel can be good or bad, dependent upon what you need to do with it. Indeed, circuit requirements differ, and eitherDC or AC considerations can drive a given application. AtLTC, wefeel that the overalipertormance of ‘a macromodel is what can make or breakit. Therefore, the ‘op amp modeling has been directed towards getting maximum real world performance in the models, that is, performance which in many waysis like the actual op amp device, But, it also means models which do not sacrifice general utility to maximize one single aspect of perfor- mance, AC, DC, or whatever. ‘ABackground of SPICE Op Amp Macromodels Circuit designers generally like to work quickly and effi- ciently with SPICE simulations, so the macromodel ap- proach is fundamentaly very attractive, for good reason, Rather than using a full set of transistors, macromodels use the various controled sources supported within SPICE, and they also minimize/simplity PN junctions as much as possible. This approach can increase simulation speed several fold over full circuit using 30-40 actual transistor ‘models. itcan also work wel (within its imitations) given a well designed macromodel Op amp macromodeling got its start about 15 years ago, in what is now a classic topological approach by Boyle, Cohn, Pederson, and Solomon.’ The model topology described in this seminal work has now become known generically as the Boyle macromodel. With recent ad- vances in computing hardware, modeling as a linear circuit design aid has taken off in the last few years. This of course has re-focused attention on modeling tech- niques in general, but the Boyle architecture in particular. Now, armed with better macromodels for their designs, analog circult architects are able in many cases to move more quickly toward better designs Note Boye, 6, Cob, 84, Pederson 0.0, Sloman LE "Macromodeing of negra Gut Operaonal Ampiters” IEE outal of Soli tae Guts, Vl SC, #6, December 1874 AN48-2 LT WERApplication Note 48 Die ecetat ad ‘AShort Course on the Boyle Macromode! While the Boyle model topology has become a default macromodel standard, italso has received criticism for op amp performance aspects it doesn't handle. Unfortu- nately, not all of this criticism has been well focused, or couched in a meaningful perspective. For example, many critics of the Boyle mode otten faut it for what it doesn’t dio in its original or most basic form, and simply ignore ‘more recent enhancements (which, ironically, aren't so hardto find). One such case of Boyle based macromodels with many useful enhancements are those produced by the MicroSim Parts? program. And, as the following aiscussions show, the basic Boyle model has been use- fully enhanced and expanded in other regards. The Boyle macromodel is shown in Figure 1, essentially just as it was originally described in the 1974 paper. This example model is for a 741 op amp, which has a bipolar [NPN input stage. The model parameters are noted inthe figure, and when run, this macromodel duplicates the characteristics of the device quite well. Comparison of the actual parameters for the 741 as modeledcan be done bya detailed contrast of the paper's appendix parameters, and those of this figure. Note that the typical op amp pin ‘numbers have been added to tie this model more closely NODE (ND) SOFA COMMON MSE Figure 1. Boyle 741 Op Amp Macromadel to a real device. As will later be apparent, this nodal ‘convention is used throughout in the LTC amplifiers. Listing 1 (see listings at end of application note) is a sample macromodel for an 8741 op amp. This model was roduced by the LTC macromodel program for NPN op amps, with input data taken from the Boyle paper appendix (Note: thereis no actual TC "8741"; this particular model ‘was done asan exercise). Comparison ofthe first portions of this model with the values of Figure 1 shows good correlation § ‘Some ofthe key equations forthe basic Boyle macromodel are noted in Figure 1, and they all can be found within the text of the paper itself. The key op amp parameters modeled are gain bandwidth product (GBP), slew rate (SR), phase margin, DC gain (Ayo), CMRR, input offset voltage (Vos), Input bias current (Ip), input offset current Not 2: Micrsim,venor of FSpie™, Probe" ane Parts 20 Farr, vine CA, 92718, (718) 70-322 Note: Tis comparison of he Lising 18741 macromacel wth the Boy xii is vad al forte code witin secon “INPUT” and porns of "INTERMEDIATE As wil notoe, hr ron lok iteenes here (cue to ound), Because oe aterert ype ot votageuent iting Used he LTC macromode ther ar lr cterece in, RO and ‘those portions flowin, which show up s ew coe ater “OUTPUT.” LT NEAR AN48-3Application Note 48 (Ios), output current limiting (gc), output voltage limits (Vsar 2), output resistance (Rou), and power supply quiescent current (Ig). (Note: The diode/VCCS and diode/ voltage source elements of this figure around ROT are associated with the voltage and current limiting of the original Bayle model. Inasmuch as these networks are not heavily used in the LTC macromodels, they are not dis- cussed inany detail. Thenew LTC functional replacements for current and voltage limiting will be discussed in the following section). Gain-Normalized Input Stage Operation ‘There is a very important design distinction ofthe Boyle model topology which allows it to be extremely flexible with regard to adaptations to other input transistor types. Referring to Figure 2, a simplified schematio-form Boyle type model, this feature lies in the fact that the input cifferential transistor pair 01/02 are, in fact, set by the macromodel design parameters to operate ata differential gain of unity. In the case of the bipolar types shown, the original Boyle design equations establish this by the wee {Ga ea peace vos VF asus) presumption thatthe gain from the amplifiers inputs to the differential output VA is by definition unity. In the original model, this unity gain, or gain-normalized operating condition for 01/02 was provided by the inclu- sion of emitter resistances, RE1/RE2. These resistors force the differential topology to this gain (once given a current for IEE). This gain normalization step adds great usefulness tothe model, in simpliying the design expres- sions for slew rate and gain bandwidth product. As a result, it leads to the substitution of other input devices within this architecture with relative ease, Speaking more broadly, the input stage gain-normaliza- tion step provides specifcaly for implementing variants of the structure, without major topology changes. As ‘noted, the original paper allowed for NPN or PNP bipolar pairs in the basic design equations. However, ifthe model topology is viewed more generally, a fundamental fact about it is that virtually any differentially operated transconductance paircan be used in the tront end, From the signal point VA (the differential outputs of Q1/02), the feng 7. a OSE Seaver Figure 2. Input Gain-Normalized Op Amp Matromodel AN48-4 ATERApplication Note 48 remaining path of the model can be essentially the same, with the basic design equations holding. For example, in the case of a PFET type amplifier, 1/02 are replaced by P- channel FETs J1/J2; or for PMOS types, they become MOS devices M1/M2, and so on. With other variations ofthistype of macromodel topology, provisions are made for transconductance adjustments to the stage, such tha the differential pair used operates at unity gain. Thiscan be eitherthrough the transconductance parameters of the transistors themselves, or via the asso- ciated degeneration resistances (RS1/RS2 for FET devices would correspond to the RE1/RE2 for bipolars). Of course, forwhatever typeof transconductance devices used, suit- able biasing steps must be made. Note that this general concept allows many variations of the original Boyle model to exist. The basic Boyle model design equations of Figure 1 then can be viewed to dictate the model's performance. This can easily be extended to include the various types mentioned. For example, as shown in the extended equations, the PFET and PMOS expression for SR will follow the same form, with Igg replacing IEE. The corresponding expression for GBP in these amplifiers is similar, with RD1 substituting for RC1 Increatinga differentinput stage op amp, thedifferentinput transistor types are accommodated viathe SPICE transistor model parameters of J1/J2, M1/M2, etc. The specific tran- sistor model parameters of these devices then determine the amplifier input Vos, Ip, and log, While this input stage gain normalization step makes the input flexible, it does have a basic trade-off. Because the input transistors are operated at current/gain levels gen- erally unlike those used in the actual op amp, the noise properties are generally uncorrelated (note that a low noise op amp will have. very high voltage gain inthe first stage, distinctly unlike this model). AS a result of this, the input noise performance of a gain-normalized model will usually not track the real IC accurately, Please note how- ever that this factor is not unique to Boyle type models, it is just as true for other models with input stage gain normalization. THE LTC APPROACH TO SPICE OP AMP MACROMODELS The LTC approach to op amp macromodel has been one aimed towards achieving design improvements within the models, but witha balanced array of simulation enhance~ ments, Attention fas been directed towards practical, useful op amp macromodels which emulate the LTC catalog devices in both their specifications as well as ‘general functionality. This approach has been rooted in building on the Boyle macromodel topology, enhancing it where appropriate. To one degree or another, this has been done for each case ofthe family ofthe four amplifier ‘macromodel topologies supported. LTC macromodels are produced in original form by an appropriate member from a family of macromodel pro- grams. These programs implement the algorithms and otherwise support features of the customized op amp ‘macromodels. Fora given program, the output consists of a SPICE compatible ASCII file, in the form of an op amp specific macromodel. With this approach, op amp macromodels can be produced virtually as fast as spec sheet definition data can be keyed in. ‘As noted, the program produces an ASCII macromodel, and Figure 3is @ header portion ofa sample macromodel produced by one of the programs. Note that the header includes information in the form of SPICE comment lines (those ines" prefixed), in addition tothe actual code of the macromodel itself. In this case the header is for the 11022 (top ine). Online two, the date/time stamp and the ‘general model type are liste. Inthe next four lines all key ‘pecs as used within the model are recorded. This infor- mation comprises the macromodel specifications, and the format is generally consistent across the four families of “ia Teny 1020 art “Wie ob 8 Fe PET oa ome Io 06-2, GBP-0.0 rc at onsen ht 2.8 nS Figure 3. LT NEAR AN48-5Application Note 48 NUT ELEMENTS AE coM cam VARY WH DRM ieee comecrato ears ex CoM: Denes 5) coupe ees ce c2 UT Saou ETENOE FORM ‘outer abate wae a wih Ge $5) Soren GacuIT MDEaTESeNHMNCENENTS. Figure 4A. Bipolar NPN Input Op Amp Macromadel (Simple) ‘macromodel types. An optional comment ine completes the main part of the header. The macromodel header conveniently documents actual working parameters ofthe model Obviously, the programmedapproach is anefficient method for generating new or revised macromodels fr release to the public. Italso has the important additional feature that itallows LTC application engineers to quickly respond to field requests for custom macromodel values for any parameter modeled. ‘THE LTC MACROMODEL FAMILY As previously noted, the LTC macromodel families are ‘comprised of four types of models. There are models for NPN and PNP bipolar input devices, for P-channel JFET input devices, and for PMOS FET input devices. While thereare similarities across these four macromodel types, there are also unique distinctions within each. The follow- ing sections detail each of these macromodel types, illustrating the common overal features as well as those ‘unique to each type of device The LTC Bipolar NPN Input Macromodels Listing 2 (see listing at end of application note) is a macromodel of the LT1007 NPN bipolar op amp, which (generally corresponds directly to the complete NPN macromodel schematic of Figure 4.* For clarity, the sche- matic is shown in two forms; the “simple” form in Figure 4A.uses symbolic connections, while the “detailed” form in Figure 48 follows the actual listing This schematic appears busy, because of the fact that it shows al possible options ofthis NPN topology. While al Note This generic schematic nas na values fr this NPN cas, nor wl ‘ose forte other ampli. Instead, actual vals for the davis uncer discussion ar ote inthe mode isting AN48-6 ATERApplication Note 48 ores {Ne ees raa.sowrnae mut yn never 2G wen comeste foes rane come oes ‘commun eenenTs he C2 MeN SHOWN W TENCE FOAM, ‘Souter uc wi va wr Gene ‘SS OOTTED CUT KATES EANCEMES, Fi of the possible options need not be present within a given device, most of them are in fact used in the case of the L11007. With regardto the schematic as shown, the many device specific conditional details which this NPN ‘macromodel can handle willbe discussed inthis context. Atte very front end of the model, there is optional use of differential input clamp diodes, with or without series resistance, etc.,and similar comments apply toCIN. These model enhancements are employed specifically to closely mimic device characteristics. For example, with the (real) 11007 and OP-27 type of device shown, a pair of two- diode differential clamps are used, DDM-DDMS, but withouta series resistance (RB1 = RB2=0). These options 48. Bipolar NPN Input Op Amp Macromodel (Detailed) {and others) are shown dotted in Figure 4, to suggest the ‘multiple possibilities, and will vary from one device type to another. Other DC enhancements used are a power con- sumption current source IP, to mimic OC current drain, and a reverse substrate diode, DSUB {which also can be diven a breakdown voltage to simulate maximum supply voltage). Overall, the general intent is to make the macromodels behave more as their real IC counterparts, in these and other functional details ‘Throughout this macromodel the main DC signal flow path is shown by the heavy lines, for larity. Controlled sources GA and GB function as they do in Figure 1, as do passive components R2, RO2,C2, and. Asisnoted, both C1 and LT WEAR AN48-7Application Note 48 C2 canbe expanded from the original Boyle single capaci- tor, to more complex optional network(s). The LT1007 Uses both ofthese networks, to simulate the muttiplepole~ zero roll-off characteristic of the actual device. This is Covered in more detail in the following section, with performance examples. The output stage ofthis model s entirely new vis-a-vis the Boyle model, and is discussed in the following section in terms of the new current/vottage limiters. Because of the reduced 192 value used for RSO (or RS), the net small signal output resistance of this model will usually be dominated by the value for RO2. This in turn makes the R02 value higher, compared to a basic Boyle model, and italso makes GB larger (for the same DC gain). ‘Improved Voltage and Current Limiting In the original Boyle model of Figure 1, bias voltages VE and VCalong with diodes 03and D4 were usedtoa provide brute-force type output voltage limiting. While workable, this scheme produces large internal limit currents within the model also can give rise to gain errors in very high gain precision ampiiiers, due to parasitic diode leakages below the limiter threshold For maximum output current simulation, diodes D1 and 102 of Figure 1 provide current limiting by indirectly sens- ing the voltage drop across RO1 (the controlled source GC produces a replica ofthe output voltage across RC, which effectively places D1/02 in parallel with RO), WhenD1 or 2 conduct to start limiting, this also produces very large currents in limit, as well as some gain degradation below threshold In many macromodels, LTC has implemented new forms of voltage and current limiting. These schemes use butt- ered biased diodes, which alow both full amplifier gain below the limit thresholds, as well as accurate imi thresh- lds for output voltage and current. They are described ‘now, and are used not only within many of the NPN macromodets, but throughout the family of models Voltage limiting in the new model of Figure 4B can be described for either the negative or positive swing, as they are similar. The positive swing limiter, whichis composed ‘of D3A, D3B, VC, RPLA, RPLB and GPL, will be described. This setup would appear at first as a modified brute-force limiter with two series diodes and a similar offset voltage source forthe threshold. It is not however; iis infact a local closed loop system, which depletes the total current available from source GA when the output voltage limit threshold is reached. This allows clean limiting, with no large internal currents The buffered biased diode D3A and resistance RPLB are used o control the leakage of 038, which would otherwise cause gain errors for an amplifier of the LT1007/0P-27 family. This vottage limit technique was found to be justified for most op amps with OC gains of 12048 or ‘more. With it active, the LT1007's 1504B gain is reached within a fraction of a dB, Current limiting inthis model is symmetrical, thats it has the same current limit level for both source and sink Currents. This is typical of amplifiers which use bipolar ‘output stages. CMOS output stages are often asymmetri- cal, and a modified form of this current limiter will be shown under the discussion of the PMOS input amplifier types. To minimize loading effects of the current limiter, it uses dedicated tloating differential inputbuffer amplifier, ECL. This VCVS senses the voltage drop across ASO (or RS), which is directly proportional to output current. The cur- rent limit threshold is defined by the gain of ECL, and the characteristics of D1, D2, RCL, and GCL. In ths instance, ‘the local loop is closed when the amplified output of ECL drives RCL, through either D1 or D2. As was true in the case of the voltage limiter, when the limit threshold is reached the controlled source (inthis case GCL) depletes all available current from GA. Again, this allows clean ‘current limiting, with no large internal currents being produced. Because ofthe buffering by ECL, this type of current miter has very low errors when below its threshold. Not only are the errors low with regard to gain degradation, but the current limit is very accurate There's also a much more subtle advantage common to these two limiters, and that is the fact that they are achieved via a parallel feedback path. As such, they will by definition be transparent below threshold, a point already made above, However, a useful side advantage ofthis is that this macromodel can get along quite wel in truth AN48-8 ATMAwithout either limiter (for special cases). n fact, they can be disabled for signal purposes very simply, by comment- ing out the controlled source driving GA, bet ether GPL, GNL, or GCL. This can come in handy, if it should ever be necessary to troubleshoot a circuit andior model for errors. Caution! Those wo may be tempted to try this should of course know what they are about! Do bear in mind that a ‘macromodel without any limiters fs capable of vey high Voltages and/or currents! Perhaps a more significant bonus ofthis limiter design schemes that special “turbo” forms of a given mode! can be saved, such as an LT1007 ‘model sans limiters. This will greatly speed up analyses, aslongas theexternalcircuitprovides fora proper DC loop closure, Macromode! Embedded Models Atthe bottom of each macromodellistingisa section titled MODELS, which does in fact define those transistor, diode, or any other models used local to the macromodel. In the case of the NPN LT1007 op amp, the NPN models for 01/02 are, as noted, different in terms of IS and BF (current gain), for the following reasons. Vos; the input offset voltage of the amplifier input pair, is modeled by using two slightly different NPN transistor models, QMt and OM2. The ratio oftheir two saturation currents will produce an offset voltage, Vos, which is: Vos = kT/q* In(1S1/1$2) With the ratios as shown in Listing 2, this produces the typical 20, offset of the LT1007¢. Bias and offset currents are modeled by using a different BF forthe two input pair halves, as: BF1 = ICA/Ig + (Ios/2)) and BF2 = IC2/(lp~ (los/2)) ‘The BF values shown for QM and QM2 are those which correspond to currents of Ig= 15nA and Ips = 12nd (again for thie LT1007C). The gains listed appear high, however this is a by-product of the fact that the actual LT1007 Application Note 48 device uses bias current compensation, and the model accounts for this simply with a higher BF. The remaining models usedin the LT1007 are diodes used in various locations, with IS scaled as to the specific use. Phase/Frequency Response Extensions One performance area where op amp modeling has re- cently received strong attention is in regard to frequency response. The original Boyle model of Figure 1 has a dominant pole set by C2 and a secondary pole set by C1. Many op amps now popular have a much more complex phase/frequency response. Asa result, using abasic Boyle ‘model AC topology to simulate their transient response can be inaccurate for some applications, Solutions to modeling additional poles and zeros can range from simple to complex, depending upon what overall trade-off the mode! designer chooses. For ex- ample, a number of sequential pole/zero stages can be added to a model for very fine emulation of small signal transients. In practice, this approach needs to be weighed carefully on an overall basis. itis not under question here that itis possible to greatly improve upon a simple Boyle type models’ phase/tre- quency response. However, what the macromodel user needs fo know is not just how the AC response is im- proved, but also whats the price to be paid fort. The end results may or may not be worth the possible drawbacks, specifically potential penalties in terms of additional memory required, longer simulation times, and possible convergence issues. Of course these considerations are basic, and are applicable to any model, LTC types in- cluded. Nevertheless, it should be noted that these types of problems exaggerate very quickly with multiple ampli- fier simutations (such as in active filters). it is entirely Possible to create more complex models which will not even run in larger mutti-amp circuits, when used in stan- dard PC environments with modest memory (~500K). Alternately, an intermediate approach to modeling some additional poles and zeros can be taken, simply by extend- ing the above mentioned two compensation caps of the basic Boyle model with additional network elements. Itis AT LNB AN48-9Application Note 48 = sop—|_ oo of 1 | Cr oo Figure 5A. LT1O07 Test F6: Isc (Open Loop, Vs = +150) oT HN even Figure SC. LT1007 Test F8: GaivPhase fa A aa Hats The “Hy + He on 4 itl coo tt tL Figure $8, LT1007 Test F7: Vsar (Vs | | | ME Figure 6D. LT1007 Test FS: Transient Response Figure. Composite Performance Points this approach that LTC has usedin Figure 4. For C1, RXC1/ GXCt can be added as one extension, while for C2, AXC2/ CXC2 can be added. Speaking generally, these are part- ‘specific options, with defaults (ie.,no extensions used) of onlyC1 andC2. Ofcoursefor the LT1007 underdiscussion a full set is used, as noted by Listing 2 In contrast to arbitrary additional pole/zero stages, this method can be viewed as relatively limited, which in truth it is. However, it has the advantage of minimal added ‘complexity, as no active stages are added to the model. It also has the fundamental virtue of working well within the overall Boyle topology, since it is an extension of it Together, these controls allow more complex frequency responses tobe simulated without additional active stages, with a net result of minimal simulation overhead in- creases. NPN model examples which use taretheLT1007/ 11037 families, the LT1028 and LT1115, and the OP-27/, P-37 families, but itis an option available with all device families. NPN Macromodel Performance At this point, some sample macromodel performance will be shown to illustrate key points, For these and the following SPICE displays, the macromodels used were taken directly from the current released LTC diskette. For the purposes of this application note, the models were edited into the form of the listings as shown herein (by editing out only the header and copyright notice sections for brevity). These files were then used in the various simulations. Unless specified otherwise, the test circuits use +15V power supplies, and the op amp model tested thas a (+) input nade of (50), a (-) input node of (51), an AN48-10 ATMAApplication Note 48 ‘output of (55), and the signal source is applied to node (2) Unless otherwise specified, no SPICE option default changes were made in the CIR files used for the tests. A 16MH2/BM PC compatible computer was used under DOS 4.01, along with MicroSim's PSpice version 4.03 (DOS version). A ramdisk was used as the work disk in all simulations. The picture series of Figure Sin composite form illustrates various performance points of the LT1007 macromodel In terms of the new limiting schemes employed, they are shown by Figure 5, in tests L 1007 F6 and F7. For display of shor circuit current, test F6 operates the amplifier as a ‘comparator (open loop) on-+15V supplies, with the output Ariving a low value resistor (100). The display is a dual trace of the load current I(R3) and its mirror ~i(R3). This allows both the current limits to be shown here, on an expanded 1% scale. As can be noted, both the limits are ‘well within 1% of the design current limit of 25mA. For display of output voltage saturation, the amplifier is ‘connected ina unity gain inverter on +15V supplies, and driven with a ~18V to +18V ramp. This overdrives the amplifier at input/output of more than #13.5V, so the extremes of the input sweep can be used to evaluate output saturation. Bath extremes of display are offset by the nominal imiting voltage of +13.5V, so the error can be showin expanded around zero, with a range of 1%. Both limits are well less than 1% in terms of error. Gain and phase response ot this particular model is interesting, ait clearly shows the effects of the C1/RXC1/ CXCt and C2/RXC2/CXC2 extensions to frequency re- sponse. Shown in Figure 5, test F8, isa composite plot of inverting mode gain/phase operating with +15V supplies, The load resistance is varied as a parameter, in steps of 100k, 10k, 2k, and 1k. As shown, the gain varies slightly around the nominal 146dB for the various loads, as would be expected for a 7002 output resistance. The phase response shows a multiple pole/zero characteristic just before unity gain crossover noint, as does the real L T1007. While the macromodel display is not as dramatic in terms ‘of phase change as the data sheet, itis still effective for its urpose. Figure 5, test F5 is a small signal transient test with the T1007 connected as a follower, emulating a correspond- ing data sheet photo. The testis a deceptively simple one, as most would think a voltage follower isa fairly straight- forward circuit. Actually, tisareatstresstestforan opamp macromodel, in terms f potential problems with conver- gence, memory usage, required simulation time, andsoon. Thisparticular simulation uns without any mishap whatso- ever, inabout 20s ona t6MH2386 PC clone, using PSpice 4.03, with no tweaking of SPICE defaults. Italso suns with ‘noapparentproblems.as one ofthe LTC demo simulations distributed on the SPICE macromodel diskette (using a demo PSpice version 3.06).5 These performance tests summarize those aspects of the LT1007 NPN macromodel previously discussed as new design features. It should be kept in mind that many of ‘them can also appear in other models as well, but they will not necessarily be repeated with subsequent examples, The LTC Bipolar PNP Input Macromodels With bipolar PNP input stage op amps, a distinct applica tion and functional difference is that they often are de- signed for single supply operation, often with supplies of 5V or less. In addition, they may also be designed for ‘micropower applications, with current drains of 100A per amplifier, or even less. LTC has a large number of such amplifiers, with the macromodels supporting them using either of two PNP model topologies ‘TheLTC PNP macromodelsare, insomesenses, similarto those using the NPN model topology. While itis true that there are similarities, since both are based on a Boyle mode, thereare also many practical differences, Speaking fof those beyond the obvious polarity differences, the ‘unique distinctions ae largely due to functional character- istics of the various amplifiers modeled. And, they are in ‘tum brought about by the single supply and/or micropower operational features previously mentioned. These ditfer- ences are the thrust of the LTC modeling enhancements. The L11013 Family of Macromodels {mn terms of historical accuracy, the family of LTC SPICE macromodels for op amps had its beginnings in 1988, Note 5: Te "DEMO1007 CR" onthe LTC SPICE ste nites se tot this "simp." ransient test wth other model, to compar relative Dartrmance. canbe reveling for sucha seemingly mace et AT Nee AN48-11Application Note 48 with the release of macromadels for the PNP input op amps LT1013 and LT1014.° These models actually had their roots in the MicroSim Parts program, and Listing 3, the macromodel for the LT1013/LT1014, is the version available today. Close akin are derivative models for the LT1013A and the LT1013D. Also related to this model are those of the LT1006 family, including the LT1006, the LT1006A, and the LT1006S8, ‘Theenhancements that these models offer overthe original Parts version are three-fold: * Oneistheinputcommonmode clamping circuitry (DCN1/ DcM2and VCMC); ‘* Two is the use of different models for input transistors 1/02 (which allows input bias and offset currents, as well as offset voltage to be simulated); * Three is the use of a controlled output saturation char- acteristic when operating near the negative supply ral, Note ung. W.G., “An LT1013 Op Amp Macromade,” Linear Techolony Design Hota #13, uy 1988. vers CE eR tn Sowrenerioneteen9 ove CaN BEOTTAGED. Further discussion and performance examples of this ‘specific model type are found in LTC Design Note 13. The L11076/L11178 Families of Macromodels ‘More recent examples of LTC bipolar PNP inputamplifiers are the two micropower families, the 45,:A quiescent cur- renvamplifie LT1078, LT1079, LT1077; and the lower power (15uA quiescent) LT1178 and LT1179, Figure 6 is € dual schematic of the macromodel topology used for these types of PNPop amps. It simulatesall those features previously noted, andis discussed below. For the purpose of minimum repetition, only features which differ from models previously discussed are addressed here. Figure 6Ais the simple version, while Figure 68 shows all detail, like the actual macromodel listing. LTC single supply op amps have had a distinction of input phase reversal protection since the introduction of the LT1013/LT1014, This also includes more recent devices suchas the T1078 andLT1178 families. For simulation of this in the macromodel, diodes DCM and DCM2 provide Figure 6A. Bipolar PNP Input Op Amp Macromodel (Simple) AN48-12 AT NEA"Mev cee evens as, na. cea Dee veuc ws vane 2 McRoeonen oe Wve ALTONA. RED, 900 MODS 5 Cowsenston eves cra 2 canes SE Figure 68. ‘a negative range input common clamp, for voltages ap- plied to the Q1-02 inputs, With the two diodes referenced ‘oa slightly positive common mode clamp voltage, VCMC, they are reverse biased for normal CM voltages. Note that the perspective here is with regard to the negative supply rail, which is also the negative CM limit for single-supply use. In customizing a macromodel, the inclusion or exclusion ofthe clamp diodes is an option, as is the RB1/RB2 current limit resistor value, and VCMC. For these single supply devices, VCMC is typically 0.4V, which allows linear com- ‘mon mode responsea few hundred mV below ground, just like the actual devices. Without this network, an LT1078 macromodel will (mis)behave just like typical 324/358 amplifiers, with input stage saturation when the inputs are taken below GND. This will be evident by an uncontrolled sign reversal t the output, or hard positive rail saturation. A key feature added to this model specifically for rmicropower devices is the extra output network, RO2B ‘and D5/D6. For ordinary dual supply applications, or even Application Note 48 polar PHP Input Op Amp Macromodel (Detailed) single supply uses where close simulation of output voltage saturation is not highly critical, this network isn’t needed. However, for single supply op amps such as the LTC PNP input devices which feature active pulldown and linear negative swing operation, simulation to within afew mV of the negative rail is entirely possible. To properly simulate this, a model which displays characteristics similar to the real device when sinking current is needed, which is the function of this network, 11076 Macromode! Performance The LT1078 is a device which illustrates all of the previ- ously mentioned performance points. Its model, shown in Listing 4, canbe compared to the schematic of Figure 6 for actual values, The composite pictures of Figure 7 illustrate various performance points, In terms of CM protection, the model input diode clamp works effectively, as shown by Figure 7, test F3, an overdriven input, +5V single ral follower. Here, the DC input V(2) is swept from -SV to 6V. The displayed output LT NEAR AN48-13Application Note 48 “Gp 49 20 00 2006 Figure 7A. 1078 Test F2: +5V Supply, Overdriven Follower “TT Te LL | Zoo TTT 0 AEE . Hy | | | | Figure 78. L11078 Test FE: gc (Open Loop, Vs = =15V) Figure 7C. LT1078 Test F7: Negative Saturation Characteristics Figure 7. Composite Performance Points is V(55), and as noted, itis clamped at OV/4V limits, and there is no phase reversal when the input is taken well below GND (maximum input sink current is SV/100K).. Figure 7, test F6 shows output voltage V(55) into a 102 load, as atest of output current limit, The + limit levels are 150mV, which corresponds to +15mA, as is specified tor the model. This display also shows the effects of the R028/D5/06 Class B output stage used in the model, asis evident by the multiple slope rise/fall For a single supply micropower op amp, one of the more difficult aspects of model performance lies in simulating the suppiy ral saturation, while retaining the micropawer performance and a relatively high maximum current out- put. For the LT1078 typical supply current is only 45, and the output resistance isa few kQ. Yet, the device can also deliver +15mA (just demonstrated). For the macro- model, the output Class B network allows concurrent mmicropower small signal characteristics, a8 well as this relatively high maximum current. The importance of the smal signal characteristics come to ply for single supply applications, where the output stage is called upon to sink Current at output voltages near GNO (ar the V- rail The finer details of the output current sinking near the negative rail are shown in Figure 7, test F7. This tests for voltage follower, with a DC input V(2) swept from OV to BV. The output stage of the model is required to sink 100uA, when the output voltage V(55) i close to GND. AS can be noted, the model is linear with voltages above 100mY. For lower voltages, it saturates at about 80mV ‘hile sinking 100A, as does the real LT1078, The LTC P-Channel JFET (PFET) Macromodels Historically speaking, the use of both junction and MOS- FET transistor types within a Boyle type macromodel topology was described by Krajewska and Holmes, in an early enhancement to the Boyle model.” The Krajewska topology isa modified Boyle type model with ether type of FET replacing the bipolars of the original model. This, enhancement took advantage of the gain-normalization referred to previously. Note 7: Krsewsta, 6, Holmes, FE. Macromodelng of FETBIpolar (Operational Ampito," IEEE Jou of Soli-State Crus, Vo. $04, +5, December 1972 AN48-14 AT NERJunction FET input op amps make up an important part of the overall field of op amps, as they are capable of both ‘medium to higher speed performance and have low DC errors. For modeling factors, LTC has chosen to realize a FET amplifier type, specifically P-channel (PFET) input stage types, with part specific enhancements for the PFET macromodets. The LTC PFET op amp macromodel is shown in schematic form in Figures 8A and 8B, (simple and detailed respec- tively). On an overall basis this model is fundamentally similar to that of Krajewska, butit has several adaptations added. It can in fact become one of the more complex ‘models in the LTC library, when all features are used, The following discussions highiight the various enhancements beyond the basic Krajewska form of the Boyle model. Those model improvement areas previously discussed ‘will not be covered in detail. The actual macromodel of an Application Note 48 T1056 (a representative LTC PFET op amp) is shown in Listing 5. PFET Macromodel Features ‘Atthe input side ofthe PFET macromodelis the J1/J2ront ‘end, which has a number of options possible within this stage. Input capacitance is simulated by Cyy, and series gate resistances RG1/RG2 are optionally added. The optional buffered clamping network around DCM1~ DCM4 is quite complex, and warrants some discussion, This circuit simulates the anti-phase reversal common mode clamping present in most (but not all) LTC PFET inputamplfiers. Inthe actual parts which useit, this clamp becomes active whenever the input voltage approaches within 4V (oF less) of the negative supply ral. This pre- vents the sign inversion typically seen in most PFET input ‘op amps, when the negative CM range is exceeded. mares INatehvs soa pore> orn avin voter CG cM 5 gern cowtnttco coun For st ASINETR. ‘source esarance nse oro ‘abana canon awe cg aN Be TENDED Figure 8A. P. rannel JFET Op Amp Macromode! (Simple) AT nee AN48-15Application Note 48 |} PTONAL CONTROLLED SOURCE FR SR ASYAMETEY ‘coun Reset ase orraL 2) Sowmendeio sevens cis oan 9 xr Figure 8. P-Channel JFET Op Amp Macromadel (Detailed) ‘The circuit appears moderately complex, but is so out of necessity. For high performance in this macromodel clamping diodes DCM1 and DCMS are bootstrapped, for lowest leakage. VCVS followers ECMP and ECMN, through resistances RCMP and RMN, reduce the voltage seen by these two diodes to a 2er0 potential for inputs where the clamp is not active. Ths is necessary to preserve the low pA bias currents of J1/J2, for normal operating range CM voltages (when the clamp is back biased). In other words, the clamp mustclamp effectively below its voltage thresh- ‘ld, yet it must not introduce leakage errors which would ruin the bias current characteristics seen at the op amp input(s). Actually the bootstrapping is quite effective, with DCM and DCM3 introducing a pA or less of error. ‘As noted, this circuit is an option with all LTC PFET input amplifiers which employ a 356 type topology, which includes the LT1056, LT1057,L 11058, LT1022, and older AN48-16 LT NERindustry standard parts such as the LF156-LF356 series, the OP-15/0P-16 series, and the related duals, Since the clamp circuits only needed for simulations which need to explore overvoltage CM inputs, it comes commented out within the respective model files. P-channel JFETS J1/J2 have individual model characteris- tics calculated to yield an input stage unity gain, gate currents consistent with the ly/los of the amplifier mod- eld, and the Vos characteristics of the opamp. All ofthese are as defined by models JMt and JM2, respectively. For the gain-normalization of the input stage, the JFET transconductance parameter BETA is adjusted for J1/J2, to provide unity gain. Alternatively, source resistances RS1/RS2 can be used for gain normalization. This option isone thatcan be exercised atthe timethe modelis created (in the interest of simplicity however, no present models Use these resistances). Vog is modeled simply as the difference in the Vzo for the two models. A subtle detail which may not be obvious is the (optional) use of voltage source VCM2, which appears within the LT1056 mode! (and similar topologies), This bias voltage simulates negative input range change of Vos, character- istic of these amplifiers. Inthe nnerstages of the model, overall gain and frequency response capability characteristics are similar to the NPN prototype discussed previously, and extensions to both Ci and C2 can optionally be used. These extensions are not used with the LT1056, As noted inthe discussion of gain-normalization, the basic equations which govern this model are quite close to the original Boyle expressions, with the adaptations for dtfer- ent circuit references. These are summarized in Figure 2. TheSR ofthe Figure 8 model is set bythe tal current of J1/ 2 and C2 for the most simple JFET ampitier cases. However, many P-channel JFET op amps are not just simple cases, inthe sense that they don't slew symmetri- cally. For asymmetric slewing JFET amplifiers, the op- tional circuitry used is described in detail in the Appendix, and it employs the VCCS GOSIT, connected as shown, nons. 2 OUTPUT VOIMGECUENT TI ca Ay 5) Sou messiness UPA ‘)obumensaion Lewes cea CaN a TENDED Figure 108, PMOS FET Op Amp Macromodel (Simpl equations (refer to Figure 2 again). Practically speaking, the variation of a PMOS input stage model allows such useful device categories as the low Ip and very low Vos chopper-stabilized units." Accurate rail-rail output limit characteristics also allow features of single supply CMOS technologies tobe realistically modeled. PMOS Macromodel Features One area where the emphasis on fidelity to the actual devices influences a model is found in this PMOS ‘macromodel. While itis in fact more complex, its so for thereason of better match tothe real parts. But, IC vendors Note 10: These models emule actual LC chopper amis intrms ot the ula low fst, he high gat and ag ners of single (ow votage) supply operation, inpwvowput anges, ete Homer tare is no actual fomimtation urcton, and therfore te ects of locking paras of ‘the actual device arent modeled haven't all taken such steps in modeling op amps with PMOS inputs and CMOS outputs. For example, inspection of some models released show such obvious deficiencies as input transistors unlike what is in the part actually modeled, and/ora lack of close attention to output imiting levels. Obviously, such models can't simulate input or output CM ranges with a high degree of fidelity, even though these factors can be critical to single supply use. ‘The output current/voltage limiters used with the LTC PMOS model ae of the more complex form shown be- ‘cause of several important performance issues. For ex- ample, amplifiers emulated by these PMOS models have ‘ail-rail outputs, with mV level saturation voltages typical of CMOS outputs. The amplifiers also have the 160dB gains, 140dB CMARs, and sub-microvolt Vog levels, as is typical of chopper stabiized amps. Many ofthese perfor- mance characteristics are made possible by some model —_—___—_—__C_—_—_—_—_—_—_—_—_————— LT NEAR AN48-19