Scaling is a discipline of science applicable to many areas such as mechanics (e. g. MEMS), electronics (e. g. ICs), and optics (e. g. micro- optics). As the dimensions of an object are linearly scaled up or down, many properties scale do not scale linearly.
Example: As the linear dimensions of an object are scaled, how do the following properties scale?
Surface area Volume Mass and weight Mechanical stability Electrical characteristics Optical properties
Different properties can scale very differently It will be useful to know the scaling laws
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 2 Introduction to MOSFET scaling
The lateral geometric dimensions of devices and interconnects are reduced. This reduction in size is referred to as scaling of the geometric dimensions of the integrated circuit (IC).
Minimum feature size is smallest size of object (e. g. gate length or interconnect linewidth) on IC.
Minimum feature size of ICs has shrunk considerably over the time of several decades. As a consequence, the number of transistors has increased over time.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 3 Processor name Year of introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 386 1985 275,000 486 DX 1989 1,180,000 Pentium 1993 3,100,000 Pentium II 1997 7,500,000 Pentium III 1999 24,000,000 Pentium 4 2000 42,000,000
This table shows the year of introduction and the number of transistors on the processors of Intel Corporation.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 4 The name Gordon E. Moore (co-founder of Intel Corp.) is frequently associated with MOSFET scaling (see, for example Gordon E. Moore "Cramming more components onto integrated circuits" Electronics, April 19, 1965).
(after Intel Corporation)
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 5 Scaling of a MOSFET:
Definition: The scaling parameter is the pre-factor by which dimensions are reduced. It is < 1.
Gate length L G L G
Gate width Z Z
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 6
Recall the basic result of the gradual channel approximation: ( ) 2 th GS G OX OX 2 sat DS, G OX OX sat D, 2 2 1 V V L d Z V L d Z I
=
=
and ( ) th GS G OX OX GS sat D, sat m, d d V V L d Z V I g
= =
The gradual channel approximation shows:
Shorter gate length results in higher transconductance. Smaller gate thickness results in higher transconductance.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 7 Gate capacitance L G Z
Gate capacitance scales with 2 . Smaller gate width results in smaller input capacitance.
Linewidths are shrunk on a two to three year cycle. The linewidth in 2002 was 0.13 0.18 m and a typical die size was 2 cm 2 .
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 8 The number of transistors per IC grows due to higher computing demand, shrinking linewidth, and growth of die size. Even if die size were a constant, the number of transistors per IC would grow.
Illustration of die size of DRAMs versus year:
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 9 Constant-voltage scaling
There are two types of scaling, namely constant-voltage scaling and constant-field scaling. Next, we discuss constant-voltage scaling.
In constant-voltage scaling, only the lateral dimensions of the MOSFET are scaled. Thus, constant-voltage scaling is a purely geometrical process.
What happens as the dimensions shrink?
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 10 If constant-voltage scaling (i. e. pure geometrical scaling) is performed, L G and Z are reduced by the scaling factor . Because the drain-source voltage remains unchanged, the lateral field increases. It increases approximately by the factor , since E V DS / L G , at least in the ohmic regime.
This will lead eventually to very high fields in the channel so that dielectric breakdown (avalanche breakdown) will occur.
Therefore, the voltages must be reduced as well. As V DS is reduced, so must be V th . As V th is reduced, so must be d OX .
Thus the electric field must stay constant. This brings us to constant- field-scaling.
Consequences of constant-voltage scaling
Consider an integrated circuit that consists of transistors. Assume that one transistor charges the input capacitance of a following transistor.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 11 As L G and Z of the transistor are scaled by the scaling factor, , the drain current of the transistor does not change because I D Z and I D 1 / L G
so that Drain current I D
1 I D = I D
Thus the drain current is not changed.
However, as L G and Z of the transistor are scaled by the scaling factor, , the gate capacitance changes because C G Z L G
so that
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 12 Gate capacitance C G
2 C G
Thus the gate capacitance strongly changes upon scaling.
The time required to charge the gate capacitance with a drain current so that a threshold voltage V th is reached, can be derived form the equation Q = C G V th . The time is given by: = C G / (dQ / dt) = C G / I D
Thus the charging time changes according to Charging time 2
As a consequence, scaled integrated circuits can operate at higher frequencies.
These factors allow one to attain higher clock speed in integrated circuits as they are scaled down.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 13 The following table illustrates performance increase as linewidths shrink.
Year Linewidth Clockspeed Beginning of 1970s 10 m 1 MHz End of 1970s 3 m 5 MHz Beginning of 1980s 2 m 20 MHz End of 1980s 0.8 m 50 MHz Beginning of 1990s 0.5 m 100 MHz End of 1990s 0.25 m 750 MHz Beginning of 2000s 0.13 m 2 GHz
Table shows typical linewidths and clock speeds versus year.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 14
Picture shows that processor IC has different areas, namely random logic and ordered arrays. Interconnect structure is very different in these areas. Scaling laws will be different for these different areas.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 15 Short-channel effects
As the gate length is reduced, the characteristics of a MOSFET change due to short-channel effects, i. e. effects that arise at very short gate (and channel) lengths.
At short gate lengths, the electrostatic field no longer resembles that of a planar capacitor.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 16
At short gate lengths, FETs suffer from; Threshold voltage shift Clear pinch-off of channel Increased leakage current Increased output conductance Minimization of leakage currents is enormously important in VLSI. Why?
How can short-channel effects be mitigated? By vertical scaling, i. e. by scaling the lateral dimensions but also by the dimensions perpendicular to the wafer plane!
By scaling all dimensions, the original field distribution can be re-created.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 17 Constant-field scaling
In constant-field scaling, the lateral dimensions (L G , Z), the perpendicular dimensions (d OX ), and the voltages (V DS , V GS , V th ) of the MOSFET are scaled. Thus, constant-field scaling is not a purely geometrical process.
What happens as the dimensions shrink?
If constant-field scaling is performed, L G , Z, d OX , V DS , V GS , and V th are reduced by the scaling factor . Electric field in the channel and oxide are
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 18 independent of the factor (with < 1), since E Channel V DS / L G (at least in the ohmic regime) and E OX V th / d OX .
Gate length L G L G
Gate width Z Z Oxide thickness d OX d OX
DS voltage V DS V DS
Threshold voltage V th V th
Thus, by constant-field scaling, the original magnitudes of E fields are re- established (approximately), hence the term constant field scaling.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 19 Punch-through effect However, the scaled structure has another problem, namely the closer proximity of source and drain depletion regions.
As a consequence, the device is now more susceptible to punch-through breakdown.
To avoid this problem, the substrate doping is increased to reduce the depletion widths
J unction depths are also reduced to mitigate short-channel V th effect.
Doping The acceptor doping N A is increased by a factor by in order to reduce the depletion widths to prevent punch-through breakdown.
In addition, the n-type implants (bath tubs) are scaled, i. e. the n-type doping concentration is increased by a factor and the junction depth is decreased by a factor . This lessens short-channel V th effects.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 20 Consequences of constant-field scaling within framework of Shockleys gradual-channel-approximation model
Recall the drain saturation current and transconductance: ( ) 2 th GS G OX OX 2 sat DS, G OX OX sat D, 2 2 1 V V L d Z V L d Z I
=
=
( ) th GS G OX OX GS sat D, sat m, d d V V L d Z V I g
= =
Assuming V GS = 0 V and the scaling dependences for L G , Z, d OX
mentioned above, the following dependences are found: Drain current I D
1
1
2 I D = I D
Transconductance
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 21 Transconductance g m
1
1 g m = g m
The static power dissipation of one transistor is given by P = I V: Static power per device P P = 2 P Power per transistor area: Power
/
area P / (Z L G ) ( 2 / 2 ) P = P The delay is given by = C G / I D : Delay = C G / I D [( 2 / ) / ] = It follows the power delay product: Power delay P 2 P
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 22 As the delay time does not change, the clock frequency would remain constant: Clock frequency f = 1 / f The energy consumed per device per clock cycle was given above: Power delay P 2 P Thus the dynamic power consumption is given by: Dynamic power P f 2 P Dynamic power per transistor area: Dynamic power / area P f / (Z L G ) ( 2 / 2 ) P = P However, we would like the next generation of scaled-down integrated circuits to work faster than the last generation, i.e. ICs should work at an
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 23 increasingly higher clock frequency. This can be accomplished by scaling the supply voltage not as aggressively.
Supply voltage does is not scaled by but by a smaller factor, e. g. () 1/2 .
Such scaling results in an increase in the channel electric field and in a higher drain current. As a result the delay time shrinks and transistors can be operated at a higher frequency. This in turn increases the dynamic power consumption per unit area. (Also note that velocity saturation effects become important at very small gate lengths leading to smaller-than-expected amplifications.)
There is an important consequence from this. The power per device reduction by 2 is optimistic and the realistic power consumption scales with less than 2 . However, the area reduction scales exactly with 2 . Thus the dynamic power consumption per unit area scales with a factor (> 2 / 2 ). As a result, the power consumption per unit area increases as ICs are scaled down. That means, scaled ICs run increasingly hot. This is a severe performance limitation for future ICs.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 24 Solution: Cooling fins and chip fans.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 25 Consequences of constant-field scaling within framework of the saturated-velocity model
Recall the drain saturation current and transconductance: ( ) Z v V V d I sat th GS OX OX sat D,
=
Z v d V I g sat OX OX GS sat D, sat m, d d
= =
If the same analysis as done above is done for the saturated-velocity model, identical results are obtained.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 26 Yield, defect density and die size
Yield, defect density, and die size are related.
Figure illustrates the relation of yield, die size and yield.
For large die sizes, yield can go to zero!
Reduction of defect density is especially important for large die size manufacturing.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 27 Maintaining a clean environment is especially important for large die size manufacturing.
One small defect can ruin a 2 cm 2 -area die!
The situation is very different for discrete device manufacturing, e. g. small-area transistor, LED, or laser manufacturing.
For a given defect density, the yield approaches 0 % and 100 % in the limit of large and small die sizes, respectively.
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 28 After scaling process reaches limits
new ideas, technologies, and concepts will be required for continued performance improvements.
examples of new ideas, technologies, and concepts: Silicon on insulator (SOI) technology SiGe and SiC technology 3D integration Optical interconnects DRAM, S-DRAM, DDR memory, RAMBUS memory Replacement of hard drives by flash memory
E. F. Schubert, Rensselaer Polytechnic Institute, 2003 29 Example: Expected advances based on SOI technology
Due to inherent performance advantages, SOI out-performs conventional CMOS technology.
