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Solution Design

The document provides instructions to design a CS amplifier to have a peak-to-peak output voltage swing of 1V and maximum voltage gain under the constraints that the transistor's transconductance is 100 μS, threshold voltage is 0.9V, and aspect ratio is greater than 50/0.9. To achieve maximum gain, the transistor should operate in saturation with the minimum drain-source voltage, which is achieved by setting the gate-source voltage to the minimum threshold of 0.9V. Calculations are shown to select the drain resistance, drain-source voltage, and transistor width that meet the constraints and provide a voltage gain of 26.

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22 views

Solution Design

The document provides instructions to design a CS amplifier to have a peak-to-peak output voltage swing of 1V and maximum voltage gain under the constraints that the transistor's transconductance is 100 μS, threshold voltage is 0.9V, and aspect ratio is greater than 50/0.9. To achieve maximum gain, the transistor should operate in saturation with the minimum drain-source voltage, which is achieved by setting the gate-source voltage to the minimum threshold of 0.9V. Calculations are shown to select the drain resistance, drain-source voltage, and transistor width that meet the constraints and provide a voltage gain of 26.

Uploaded by

kavita4123
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Q.

13 Design the CS amplifier shown below such that peak-to-peak output voltage swing is
1V and voltage gain i s maxi mumunder the following constraints:
2
100 ; ( / ) 50; 0.9 50 /
D GS N
R k W L V V KP A V s s > =
v
in
m1
R
D
V
GS
3.3V
v
o

Av gm Rd := Rd VDD 3.3 :=
Rd
VDD VDSQ
IDSQ
:=
VDSQ
VDSQ vom VDSAT + >
gm
2 IDSQ
VDSAT
:=
IDSQ
Av 2
VDD VDSQ ( )
VDSAT
:=
VDSQ
For maximum gain, VDSAT should be minimum which implies VGS should be minimum
VGS 0.9 :=
VDSAT 0.2 := VDSQ 0.7 :=
We choose highest possible drain resistance to keep current to a minimum
Rd 100 10
3
:=
IDSQ
VDD VDSQ
Rd
:= IDSQ 2.6 10
5
=
we choose size to keep VGS =0.9V
n
2 IDSQ
VDSAT
2
:=
n 1.3 10
3
=
W
n
50 10
6

:= W 26 =
Av 2
VDD VDSQ ( )
VDSAT
:= Av 26 =

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