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Pseudo Random Sequence Generator

The document discusses a pseudo-random sequence generator that uses an n-bit shift register with XNOR feedback to generate a pseudo-random sequence of numbers. It shows the schematic of a common configuration using two taps and notes that maximal length sequences sometimes require 3, 4, or 5 taps. It also includes a code template for a 7-bit shift register and a table listing the repetition times for sequences generated by shift registers of different sizes using a 4MHz clock.

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74 views

Pseudo Random Sequence Generator

The document discusses a pseudo-random sequence generator that uses an n-bit shift register with XNOR feedback to generate a pseudo-random sequence of numbers. It shows the schematic of a common configuration using two taps and notes that maximal length sequences sometimes require 3, 4, or 5 taps. It also includes a code template for a 7-bit shift register and a table listing the repetition times for sequences generated by shift registers of different sizes using a 4MHz clock.

Uploaded by

nakamo_id
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Switching and Logic

Spring 2008

jeg

Pseudo-Random Sequence Generator


The use of a shift-register with XNOR feedback will yield a pseudo random sequence of numbers. If an n-bit shift register is used, the sequence is 2n-1 where the state of all ones is excluded. The schematic for this pseudo random sequence generator is shown in Figure 1. This diagram shows the most common configuration with two taps. To reach a maximal length sequence sometimes 3, 4 or 5 taps are required. See Table 1 for the taps that give maximal length pseudo random sequences. Note when the shift register is powered up the content is all zeros. By using the exclusive-NOR the sequence is self starting.
=1

clk

Figure 1 Pseudo Random Sequence Generator

The code given below for the 7-bit shift register will work as a template for shift registers of other sizes.
ENTITY PRSG7 IS PORT( CLK : IN BIT; Q : BUFFER BIT_VECTOR (7 DOWNTO 1) ); END ENTITY PRSG7; ARCHITECTURE BEHAVIORAL OF PRSG7 IS BEGIN PROCESS(Q,CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q <= Q(6 DOWNTO 1) & (Q(7) XNOR Q(6)); ELSE Q <= Q; END IF; END PROCESS; END ARCHITECTURE BEHAVIORAL;

The PLDT-2 boards come with a 4 MHz clock oscillator as the standard global clock. Table 1 list the time it will take the sequence to repeat for the 4 MHz clock oscillator. It is assumed that one would allow the pseudo random sequence generator to run continuously, and then pick different taps to generate the smaller bit patterns to cause random events to take place in the design.

Switching and Logic


Table 1 Primitive Polynomial Modula 2 n 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Taps Repetition Time for 4 MHz Clock 1.75 3.75 7.75 15.75 31.75 63.75 127.75 255.75 511.75 1.02 2.05 4.10 8.19 16.38 32.77 65.54 131.07 262.14 524.29 1.05 2.10 4.19 8.39 16.78 33.55 1.12 2.24 4.47 8.95 17.90

Spring 2008

jeg

Units us ns ns us us us us us us ms ms ms ms ms ms ms ms ms ms s s s s s s m m m m m

3,2 4,3 5,3 6,5 7,6 8,6,5,4 9,5 10,7 11,9 12,6,4,1 13,4,3,1 14,5,3,1 15,14 16,15,13,4 17,14 18,11 19,6,2,1 20,17 21,19 22,21, 23,18 24,23,22,17 25,22 26,6,2,1 27,5,2,1 28,25 29,27 30,6,4,1 31,28 32,22,2,1

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