Wednesday, September 4, 2013

Contents:
Introduction Block Diagram and Pin Description of the 8051 Registers Some Simple Instructions Structure of Assembly language and Running an 8051 program Memory mapping in 8051 8051 Flag bits and the PSW register Addressing Modes 16-bit, BCD and Signed Arithmetic in 8051 Stack in the 8051 LOOP and JUMP Instructions CALL Instructions I/O Port Programming

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General-purpose microprocessor
CPU for Computers No RAM, ROM, I/O on CPU chip itself Example Intels x86, Motorolas 680x0

Introduction

CPU GeneralPurpose Microprocessor

Data Bus

Many chips on mothers board

RAM

ROM

I/O Port

Timer

Serial COM Port

Address Bus General-Purpose Microprocessor System Wednesday, September 4, 2013

Microcontroller :
A smaller computer On-chip RAM, ROM, I/O ports... Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU I/O Port

RAM ROM Serial Timer COM Port

A single chip
Microcontroller

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Microprocessor vs. Microcontroller

Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate designer can decide on the amount of ROM, RAM and I/O ports. expansive versatility general-purpose Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical single-purpose

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Embedded System
Embedded system means the processor is embedded into that application. An embedded product uses a microprocessor or microcontroller to do one task only. In an embedded system, there is only one application software that is typically burned into ROM. Example printer, keyboard, video game player

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Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit 2. availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support 3. wide availability and reliable sources of the microcontrollers.

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Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data Wednesday, September 4, 2013

Comparison of the 8051 Family Members

Feature 8051 ROM (program space in bytes) 4K RAM (bytes) 128 Timers 2 I/O pins 32 Serial port 1 Interrupt sources 6

8052 8K 256 3 32 1 8

8031 0K 128 2 32 1 6

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Pin Description of the 8051

PDIP/Cerdip
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0 P ) 0.1(AD1) P0.2(AD2 P ) 0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 P2.5(A13 ) P ) 2.4(A12 P2.3(A11 ) P ) 2.2(A10) P2.1(A9) P2.0(A8)

8051 (8031)

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Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL

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Memory mapping in 8051

ROM memory map in 8051 family
4k
0000H 0000H

8k
0000H

32k

0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

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 RAM memory space allocation in the 8051

7FH Scratch pad RAM

30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0

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RAM memory space allocation in the 8051 Total of 128 bytes of RAM inside the 8051 are assigned addresses 00H to 7FH (a) Total of 32 bytes from locations 00H to 1FH are set aside for register bank and the stack. (b) Total of 16 bytes from locations 20H to 2FH are set aside for bit addressable read/write memory. (c) Total of 80 bytes from locations 30H to 7FH are used for read and write storage, called Scratch pad area used for storing data.
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8051 Flag bits and the PSW register

PSW Register
CY AC F0 RS1 RS0 OV -P

Carry flag Auxiliary carry flag Available to the user for general purpose Register Bank selector bit 1 Register Bank selector bit 0 Overflow flag User define bit Parity flag Set/Reset odd/even parity
RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3

PSW.7 CY PSW.6 AC PSW.5 -PSW.4RS1 PSW.3RS0 PSW.2 OV PSW.1 -PSW.0 P

Address 00H-07H 08H-0FH 10H-17H 18H-1FH

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Instructions that Affect Flag Bits:

Note: X can be 0 or 1

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Wednesday, September 4, 2013

8051 instruction set

MOV copy the data from data memory MOVC copy the data from code memory MOVX - copy the data from external memory

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 MOV A,#data(8bit) load accumulator with 8bit data eg: MOV A,#16h A 16h MOV A,10h the data from RAM location 10 will be loaded to accumulator.
12 11 10 0F 0E 34

34h

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 MOV Rn,# data Eg: MOV R4,#56h R4 56h MOV 03h, # 45h 03h 45h (03 0r R3 is address) MOV A,Rn Eg: MOV A,R3 load Accumulator with the content of R3 MOV Rn,A Rn A
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 MOV addr(8),addr(8) To represent data starting with alphabets from A to F, should be added 0 as prefix Eg : MOV 00h,# 0AEh MOV addr(8), A Addr A MOV Rn,Rn is invalid
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[Rp is R0 or R1) MOV A, @Rn The content of memory location whose address is stored in the register Rp will be moved to the accumulator. MOV addr(8),@Rp MOV @Rp, #data MOV @Rp, A MOV @Rp,addr(8)

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DATA POINTER
The Data Pointer (DPTR) is the 8051s only useraccessable 16-bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the name suggests, is used to point to data. It is used by a number of commands which allow the 8051 to access external memory. When the 8051 accesses external memory it will access external memory at the address indicated by DPTR. While DPTR is most often used to point to data in external memory, many programmers often take advantage of the fact that its the only true 16-bit register available. It is often used to store 2-byte values which have nothing to do with memory locations.
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 Function: Move Data To/From External Memory (XRAM) Syntax: MOVX operand1,operand2 Instructions MOVX @DPTR,A MOVX @Rp, A MOVX A,@DPTR MOVX A, @Rp Description: MOVX moves a byte to or from External Memory into or from the Accumulator. If operand1 is @DPTR, the Accumulator is moved to the 16-bit External Memory address indicated by DPTR. This instruction uses both P0 (port 0) and P2 (port 2) to output the 16-bit address and data.
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MOVX

MOVX
If operand2 is DPTR then the byte is moved from External Memory into the Accumulator. If operand1 is @R0 or @R1, the Accumulator is moved to the 8-bit External Memory address indicated by the specified Register. This instruction uses only P0 (port 0) to output the 8bit address and data. P2 (port 2) is not affected. If operand2 is @R0 or @R1 then the byte is moved from External Memory into the Accumulator.
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MOVC
Operation: MOVC Function: Move Code Byte to Accumulator Syntax: MOVC A, @A+register Instructions : MOVC A,@A+DPTR MOVC A,@A+PC Description: MOVC moves a byte from Code Memory into the Accumulator. The Code Memory address from which the byte will be moved is calculated by summing the value of the Accumulator with either DPTR or the Program Counter (PC). In the case of the Program Counter, PC is first incremented by 1 before being summed with the Wednesday, September 4, 2013 Accumulator.

ARITHMETIC INSTRUCTIONS All addition is done with the A register as the destination of the result ADD A,#data(8) A+data(8) A ADD A, Rn(n=0 to 7) add A and the content of Rn, result is in A A+addr(8) A ADD A,add(8) - add A and the content of address, result is in A A+addr(8) A ADD A, @Rp (Rp is R0 or R1) add the contents of address in Rp ; put result in A
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ADDC add with carry

ADDC A,#data(8) A + data(8)+ CY ADDC A,Rn A + Rn+CY A ADDC A,add(8) A + addr(8)+CY

ADDC A,@Rp add the content of A, the content of indirect address in Rp,and the C flag; put result in A
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 SUBTRACTION

Subtraction can be done by taking the twos complement of the number to be subtracted, the subtrahend and adding it to the other number. The 8051 has commands to perform the direct subtraction of two unsigned and signed numbers. Like addition Register A is the destination address for the subtraction. Subtraction always subtract the carry flag (borrow) as part of the operation
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Subtraction
SUBB A,#data(8) A - data(8)- CY A Subtract immediate data(8) and the C Flag from A and the result will be in A. SUBB A, add(8) A add(8) - CY SUBB A, Rn A- Rn- CY A

SUBB A, @Rp: Subtract the contents of the address in Rp and the C Flag from A and result is stored in A
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Unsigned subtraction
In the above instruction C Flag is always subtracted from A along with the source byte. It must be set to 0, if programmer does not want the carry Flag to be included in the subtraction. In a multibyte subtraction the carry flag has to be cleared for first byte and then included for the subsequent higher byte operations. The result will be in the true form, with no borrow if the source number is smaller than A. The result will be in Twos complement form, with borrow if the source is larger than A. All bits are considered as the magnitude.
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Multiplication and Division

The 8051 has the capability to perform 8-bit integer multiplication and division using A and B registers. Multiplication: Multiplication use registers A and B as both source and destination addresses. MUL AB multiply A by B; put the lower byte of the product in A, and the higher order byte in B The unsigned number in register A is multiplied with the unsigned number in register B and the result will be stored in A, if the product is less than FF h. If the product is greater than FF h, the OV Flag will be Set. The higher order bytes will be stored in register B and lower order bytes in register A. The carry flag is always cleared to 0.
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Example
MOV A, #7B H ;A=7Bh MOV 0F0h,#02h ;B=02h MUL AB ;A=F6h and B=00h,OV=0 MOV B, #0FEh ;B= FEh MUL AB ;A=14h, B=F4h,OV Flag=1

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 Division operation use registers A and B as both the source and destination addresses for the operation. DIV AB Divide A by B; the integer part of quotient in register A and the integer part of the remainder in B. The OV flag is cleared to 0 unless B holds 00h before the DIV. Then the overflow flag is set to 1 to show division by 0. This division is undefined. The carry flag is always reset. Wednesday, September 4, 2013

Division

 Example MOV A,#0FFh MOV 0F0h,#2Ch DIV AB DIV AB DIV AB DIV AB A = FFh B = 2Ch A = 05h and B = 23h A = 00h and B = 05h A = 00h and B = 00h A = ? and B = ?; OV = 1

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Decimal arithmetic
Most of the real world application which involves interacting with the human beings, which insists the numbering to be done in decimal number system. Four bits are required to represent the decimal 0-9 (0000h-1001h) DA A Adjust the sum of two packed BCD numbers found in A register; result in A The DA A will work with the instruction ADDC or ADD.
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INCREMENT
Operation: INC No flags are affected(C,AC,OV) Function: Increment Register Instructions INC A INC Rn INC @Rp INC addr INC DPTR Description: INC increments the value of register or content of address by 1. In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented.
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Decrement
Operation:DEC Instructions DEC A DEC Rn DEC @Rp DEC addr(8) Description: DEC decrements the value of register or the content of address by 1.

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Clear
Operation:CLR Instructions CLR addr(8) Clear the content of address specified CLR C Clear carry flag CLR A Clear the content of accumulator Description: CLR clears (sets to 0) all the bit(s) of the indicated register. If the register is a bit (including the carry bit), only the specified bit is affected. Clearing the Accumulator sets the Accumulators value to 0.
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Logical Instruction
Operation: CPL Function: Complement Syntax: CPL operand Instructions CPL A - complement each bit of A CPL C - complement Carry

CPL addr(8) - complement each bit of the content of address specified.

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Operation: ANL Function: Bitwise AND Instructions ANL addr(8), A AND each bit of A with same bit of direct RAM address and store the result in addr(8) ANL A,addr(8) -AND each bit of A with same bit of direct RAM address and store the result in A ANL addr(8), #data ANL A, #data ANL A, Rn ANL A, @Rp ANL A,R0 ANL C, bit addr

AND operation

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XOR
Operation: XRL Function: Bitwise Exclusive OR Instructions XRL addr(8), A XRL addr(8), #data XRL A, #data XRL A, addr(8) XRL A, @Rp

Description: XRL does a bitwise "EXCLUSIVE OR" operation between operand1 and operand2, leaving the resulting value in operand1. The value of operand2 is not affected.
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OR Operation
Operation: ORL Function: Bitwise OR Instructions ORL addr(8), A ORL addr(8), #data ORL A, #data ORL A, addr(8) ORL A,@R0 ORL C, bit

Description: ORL does a bitwise "OR" operation between operand1 and operand2, leaving the resulting value in operand1. The value of operand2 is not affected.
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RR RL RRC RLC A EXAMPLE: RR A RR: RRC: RL: RLC:

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ROTATE LEFT
Operation: RL Function: Rotate Accumulator Left Syntax: RL A Description: Shifts the bits of the Accumulator to the left. The left-most bit -bit 7 of the Accumulator is loaded into bit0. Operation: RLC Function: Rotate Accumulator Left Through Carry Syntax: RLC A Description: Shifts the bits of the Accumulator to the left. The left-most bit (bit 7) of the Accumulator is loaded into the Carry Flag, and the original Carry Flag is loaded into bit 0 of the Accumulator. This function can be used to quickly multiply a byte by 2.

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ROTATE RIGHT
Operation: RR Function: Rotate Accumulator Right Syntax: RR A Description: Shifts the bits of the Accumulator to the right. The right-most bit -bit 0 of the Accumulator is loaded into bit7. Operation: RRC Function: Rotate Accumulator Right Through Carry Syntax: RRC A Description: Shifts the bits of the Accumulator to the right. The right-most bit (bit 0) of the Accumulator is loaded into the Carry Flag, and the original Carry Flag is loaded into bit 7. This function can be used to quickly divide a byte by 2.

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LOOP and JUMP Instructions

Conditional Jumps :
JZ JNZ DJNZ CJNE A, byte CJNE reg, #data JC JNC JB JNB Jump if A=0 Jump if A/=0 Decrement and jump if A/=0 Jump if A/=byte Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0

JBC Jump if bit=1 and clear bit Wednesday, September 4, 2013

LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory location from 0000 to FFFFH. AJMP(absolute jump) In this 2-byte instruction, It allows a jump to any memory location within the 2k block of program memory. SJMP(short jump) In this 2-byte instruction. The relative address range of 00FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.

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JMP
Operation: JMP Function: Jump to Data Pointer + Accumulator Syntax: JMP @A+DPTR Description: JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the value of the Accumulator.
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Operation: CJNE Function: Compare and Jump If Not Equal Syntax: CJNE operand1,operand2,reladdr CJNE A, #data ,relative-address
Compare the content of the accumulator and the data and branch to the relative address if not equal

CJNE

CJNE A, addr(8),relative-address CJNE @Rp, #data, relative-address Description: CJNE compares the value of operand1 and operand2 and branches to the indicated relative address if operand1 and operand2 are not equal. If the two operands are equal program flow continues with the instruction following the CJNE instruction. The Carry bit (C) is set if operand1 is less than operand2, otherwise it is cleared.
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JNC
Operation: JNC Function: Jump if Carry Not Set Syntax: JNC reladdr Description: JNC branches to the address indicated by reladdr if the carry bit is not set. If the carry bit is set program execution continues with the instruction following the JNC instruction.

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JC
Operation: JC Function:Jump if Carry Set Syntax:JC reladdr Description: JC will branch to the address indicated by reladdr if the Carry Bit is set. If the Carry Bit is not set program execution continues with the instruction following the JC instruction.

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JNZ
Operation: JNZ Function: Jump if Accumulator Not Zero Syntax:JNZ reladdr Description: JNZ will branch to the address indicated by reladdr if the Accumulator contains any value except 0. If the value of the Accumulator is zero program execution continues with the instruction following the JNZ instruction.

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JZ
Operation: JZ Function:Jump if Accumulator Zero Syntax:JZ reladdr Description: JZ branches to the address indicated by reladdr if the Accumulator contains the value 0. If the value of the Accumulator is non-zero program execution continues with the instruction following the JZ instruction.

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JNB
Operation: JNB Function: Jump if Bit Not Set Syntax: JNB bit addr, reladdr Description: JNB will branch to the address indicated by relative address if the indicated bit is not set. If the bit is set program execution continues with the instruction following the JNB instruction.

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JB
Operation: JB Function:Jump if Bit Set Syntax:JB bit addr, reladdr Description: JB branches to the address indicated by relative address if the bit indicated by bit addr is set. If the bit is not set program execution continues with the instruction following the JB instruction.

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JBC
Operation: JBC Function: Jump if Bit Set and Clear Bit Syntax: JB bit addr, reladdr Description: JBC will branch to the address indicated by reladdr if the bit indicated by bit addr is set. Before branching to reladdr the instruction will clear the indicated bit. If the bit is not set program execution continues with the instruction following the JBC instruction.

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SETB
Operation: SETB Function: Set Bit Syntax: SETB bit addr Description: Sets the specified bit.

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SWAP
Operation: SWAP Function: Swap Accumulator Nibbles Syntax: SWAP A Description: SWAP swaps bits 0-3 of the Accumulator with bits 4-7 of the Accumulator. This instruction is identical to executing "RR A" or "RL A" four times.
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Stack in the 8051

The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
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7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0

Operation: PUSH Function: Push Value Onto Stack PUSH addr(8); Description: PUSH "pushes" the value of the specified addr(8) onto the stack. PUSH first increments the value of the Stack Pointer by 1, then takes the value stored in internal RAM addr and stores it in Internal RAM at the location pointed to by the incremented Stack Pointer.

PUSH

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POP
Operation: POP Function: Pop Value From Stack Syntax: POP POP addr(8) Description: POP "pops" the last value placed on the stack into the internal RAM address specified. In other words, POP will load addr(8) with the value of the Internal RAM address pointed to by the current Stack Pointer. The stack pointer is then decremented by 1.

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CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.

LCALL(long call) This 3-byte instruction can be used to call subroutines located anywhere within the 64K byte address space of the 8051. ACALL (absolute call) ACALL is 2-byte instruction. The target address of the subroutine must be within 2K byte range.
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RETURN
Operation: RET Function: Return From Subroutine Syntax: RET Description: RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by the least-significant-byte.
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RETURN FROM INTERRUPT

Operation:RETI Function:Return From Interrupt Description: RETI is used to return from an interrupt service routine. RETI first enables interrupts of equal and lower priorities to the interrupt that is terminating. Program execution continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by the least-significant-byte. RETI functions identically to RET if it is executed outside of an interrupt service routine.
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XCH
Function: Exchange Bytes Syntax: XCH A, Rn XCH A, @Rp XCH A, addr Description: Exchanges the value of the Accumulator with the value contained in register.

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Function: Exchange Digit Syntax: XCHD A,@Rp XCHD A,@R0 XCHD A,@R1 Description: Exchanges bits 0-3 of the Accumulator with bits 0-3 of the Internal RAM address pointed to indirectly by R0 or R1. Bits 4-7 of each register are unaffected. Eg: RAM location 40H = 97H MOV A,#12H MOV R1,#40H XCHD A,@R1 After execution A = 17H and RAM location 40H =92H
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XCHD

Operation: NOP Function: None, waste time Syntax: No Operation Description: NOP, as its name suggests, causes No Operation to take place for one machine cycle. NOP is generally used only for timing purposes. Absolutely no flags or registers are affected.
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Addressing Modes
Immediate Register Direct Register Indirect Indexed

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Immediate Addressing Mode

MOV MOV MOV MOV MOV A,#65H A,#A R6,#65H DPTR,#2343H P1,#65H

Example : Num MOV MOV ORG data1: EQU 30

R0,Num DPTR,#data1 100H db

IRAN

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Register Addressing Mode

MOV ADD MOV MOV MOV Rn, A A, Rn DPL, R6 DPTR, A Rn, Rn ;n=0,..,7

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Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 7FH. MOV MOV MOV MOV R0, 40H 56H, A A, 4 6, 2

Direct Addressing Mode

; MOV A, R4 ; copy R2 to R6 ; MOV R6,R2 is invalid !

SFR register and their address

MOV 0E0H, #66H ; MOV A,#66H MOV 0F0H, R2 ; MOV B, R2 MOV 80H,A ; MOV P0,A
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Bit Addressable Page 359,360

Register Indirect Addressing Mode

In this mode, register is used as a pointer to the data. A,@Rp @R1,B ; move content of RAM loc.Where address is held by Ri into A ( i=0 or 1 ) MOV MOV

In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. Solution: MOV R0,37h MOV R1,59h MOV R2,10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1

; source pointer ; dest pointer ; counter

jump

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Indexed Addressing Mode And On-Chip ROM Access

This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051 MOVC A,@A+DPTR A= content of address A +DPTR from ROM Note: Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The C means code.
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Pins of 8051 1/4

Vcc pin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GND pin 20 ground XTAL1 and XTAL2 pins 19,18 These 2 pins provide external clock. Way 1 using a quartz crystal oscillator Way 2 using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.

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Pins of 8051 2/4

RST pin 9 reset It is an input pin and is active high normally low . The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers Way 1 Power-on reset circuit Way 2 Power-on reset with debounce

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Pins of 8051 3/4

/EA pin 31 external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSEN pin 29 program store enable This is an output pin and is connected to the OE pin of the ROM. See Chapter 14.

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Pins of 8051 4/4

ALE pin 30 address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

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Figure 4-2 (a). XTAL Connection to 8051

Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND

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Figure 4-2 (b). XTAL Connection to an External Clock Source

N C Using a TTL oscillator XTAL2 is unconnected.

EXTERNAL OSCILLATOR SIGNAL

XTAL2

XTAL1

GND

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Example :
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s

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RESET Value of Some 8051 Registers:

Register PC ACC B PSW SP DPTR RAM are all zero.

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Reset Value 0000 0000 0000 0000 0007 0000

Figure 4-3 (a). Power-On RESET Circuit

Vcc

+ 10 uF 30 pF 8.2 K 30 pF 11.0592 MHz 31 19 18 EA/VPP X1 X2

9 RST

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Figure 4-3 (b). Power-On RESET with Debounce

Vcc

31 10 uF 30 pF

EA/VPP X1

9 8.2 K

X2 RST

Wednesday, September 4, 2013

Pins of I/O Port

The 8051 has four I/O ports Port 0 pins 32-39 P0 P0.0 P0.7 Port 1 pins 1-8 P1 P1.0 P1.7 Port 2 pins 21-28 P2 P2.0 P2.7 Port 3 pins 10-17 P3 P3.0 P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7 , P1.X, P2.X, P3.X Ex P0.0 is the bit 0 LSB of P0 Ex P0.7 is the bit 7 MSB of P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).
Wednesday, September 4, 2013

Some Simple Instructions

MOV dest,source MOV MOV MOV MOV MOV MOV MOV MOV A,#72H A, #r R4,#62H B,0F9H DPTR,#7634H DPL,#34H DPH,#76H P1,A ;mov A to port 1 ; dest = source ;A=72H ;A=r OR 72H ;R4=62H ;B=the content of F9th byte of RAM

Note 1: MOV A,#72H After instruction MOV 8086 MOV MOV MOV MOV

MOV A,72H A,72H the content of 72th byte of RAM will replace in Accumulator. 8051 MOV MOV MOV

AL,72H AL,r BX,72H AL,[BX]

A,#72H A,#r A,72H

Note 2: MOV A,R3

MOV

A,3

Wednesday, September 4, 2013

ADD A, Source

;A=A+SOURCE

ADD ADD ADD ADD

A,#6 A,R6 A,6 A,0F3H

;A=A+6 ;A=A+R6 ;A=A+[6] or A=A+R6 ;A=A+[0F3H]

Wednesday, September 4, 2013

SETB CLR
SETB SETB SETB SETB SETB
Note:

bit bit
C P0.0 P3.7 ACC.2 05

; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h
Bit Addressable Page 359,360

CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
Wednesday, September 4, 2013

SUBB
SETB C SUBB A,R5

A,source ;A=A-source-CY
;CY=1 ;A=A-R5-1

ADC
SETB C ADC

A,source ;A=A+source+CY
;CY=1 A,R5 ;A=A+R5+1

Wednesday, September 4, 2013

DEC INC
INC DEC DEC

byte byte
R7 A 40H

;byte=byte-1 ;byte=byte+1

; [40]=[40]-1

CPL
Example: L01: MOV CPL MOV ACALL SJMP

;1s complement
A,#55H ;A=01010101 B A P1,A DELAY L01

CALL

NOP & RET & RETI

All are like 8086 instructions.

Wednesday, September 4, 2013

ANL - ORL - XRL EXAMPLE: MOV R5,#89H ANL R5,#08H RR RL RRC RLC EXAMPLE:
RR A
Wednesday, September 4, 2013

Structure of Assembly language and Running an 8051 program

ORG MOV MOV MOV ADD ADD HERE: SJMP END 0H R5,#25H R7,#34H Myfile.lst A,#0 A,R5 A,#12H HERE
EDITOR PROGRAM Myfile.asm ASSEMBLER PROGRAM Other obj file Myfile.obj LINKER PROGRAM

Myfile.abs OH PROGRAM Myfile.hex

Wednesday, September 4, 2013

Example: MOV A,#88H ADD A,#93H 88 10001000 +93 +10010011 ---- -------------11B 00011011 CY=1 AC=0 P=0

Example: MOV A,#9CH ADD A,#64H 9C +64 ---100 CY=1 AC=1 10011100 +01100100 -------------00000000 P=0

Example: MOV A,#38H ADD A,#2FH 38 +2F ---67 CY=0 AC=1 00111000 +00101111 -------------01100111 P=1

Wednesday, September 4, 2013

Example: Assuming that ROM space starting at 250h contains Hello., write a program to transfer the bytes into RAM locations starting at 40h. Solution: ORG 0 MOV DPTR,#MYDATA MOV R0,#40H L1: CLR A MOVC A,@A+DPTR JZ L2 MOV @R0,A INC DPTR INC R0 SJMP L1 L2: SJMP L2 ;------------------------------------ORG 250H MYDATA: DB Hello,0 END Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.

Wednesday, September 4, 2013

Example: Write a program to get the x value from P1 and send x 2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81 END

Wednesday, September 4, 2013

16-bit, BCD and Signed Arithmetic in 8051

Exercise: Write a program to add n 16-bit number. Get n from port 1. And sent Sum to LCD a) in hex b) in decimal Write a program to subtract P1 from P0 and send result to LCD
(Assume that ACAL DISP display A to LCD )
Wednesday, September 4, 2013

MUL & DIV

MUL MOV MOV MUL MUL MOV MOV MUL AB A,#25H B,#65H AB AB A,#25 B,#10 AB ;B|A = A*B

;25H*65H=0E99 ;B=0EH, A=99H ;A = A/B, B = A mod B

;A=2, B=5

Wednesday, September 4, 2013

Stack in the 8051

The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0

Wednesday, September 4, 2013

Example: MOV MOV MOV PUSH PUSH PUSH R6,#25H R1,#12H R4,#0F3H 6 1 4

0BH 0AH 09H 08H Start SP=07H

0BH 0AH 09H 08H 25

0BH 0AH 09H 08H 12 25

0BH 0AH 09H 08H F3 12 25

SP=08H

SP=09H

SP=08H

Wednesday, September 4, 2013

LOOP and JUMP Instructions

DJNZ:
Write a program to clear ACC, then add 3 to the accumulator ten time Solution: MOV MOV AGAIN: ADD DJNZ MOV A,#0; R2,#10 A,#03 R2,AGAING ;repeat until R2=0 (10 times) R5,A

Wednesday, September 4, 2013

 Other conditional jumps :

JZ JNZ DJNZ CJNE A,byte CJNE reg,#data JC JNC JB JNB JBC Jump if A=0 Jump if A/=0 Decrement and jump if A/=0 Jump if A/=byte Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit

Wednesday, September 4, 2013

SJMP and LJMP: LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the opcode, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH. SJMP(short jump) In this 2-byte instruction. The first byte is the opcode and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.
Wednesday, September 4, 2013

CJNE , JNC
Exercise: Write a program that compare R0,R1. If R0>R1 then send 1 to port 2, else if R0<R1 then send 0FFh to port 2, else send 0 to port 2.

Wednesday, September 4, 2013

CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine. LCALL(long call) In this 3-byte instruction, the first byte is the opcode an the second and third bytes are used for the address of target subroutine. Therefore, LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.
Wednesday, September 4, 2013

 ACALL (absolute call)

ACALL is 2-byte instruction in contrast to LCALL, which is 13 bytes. Since ACALL is a 2-byte instruction, the target address of the subroutine must be within 2K bytes address because only 11 bits of the 2 bytes are used for the address. There is no difference between ACALL and LCALL in terms of saving the program counter on the stack or the function of the RET instruction. The only difference is that the target address for LCALL can be anywhere within the 64K byte address space of the 8051 while the target address of ACALL must be within a 2Kbyte range.
Wednesday, September 4, 2013

I/O Port Programming

Port 1 pins 1-8

Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus)

Wednesday, September 4, 2013

A Pin of Port 1
Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch
D Q

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

Wednesday, September 4, 2013

8051 IC

P0.x

Hardware Structure of I/O Pin

Each pin of I/O ports Internal CPU bus communicate with CPU A D latch store the value of this pin D latch is controlled by Write to latch Write to latch 1 write data into the D latch

2 Tri-state buffer
TB1: controlled by Read pin
Read pin 1 really read the data present at the pin

TB2: controlled by Read latch

Read latch 1 read value from internal latch

A transistor M1 gate
Gate=0: open Wednesday, September 4, 2013

Tri-state Buffer
Output Input

Tri-state control (active high)

Low

Highimpedance (open-circuit)

Wednesday, September 4, 2013

Writing 1 to Output Pin P1.X

Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 1 to the pin

Internal CPU bus Write to latch
D Q

Vcc

1 0
M1

P1.X
Clk Q

P1.X pin

output 1

TB1 Read pin

Wednesday, September 4, 2013

8051 IC

Writing 0 to Output Pin P1.X

Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 0 to the pin

Internal CPU bus Write to latch
D Q

ground
P1.X pin

0 1
M1

P1.X
Clk Q

output 0

TB1 Read pin

Wednesday, September 4, 2013

8051 IC

Port 1 as Output Write to a Port

Send data to Port 1 MOV A,#55H MOV P1,A ACALL DELAY CPL A SJMP BACK

BACK:

Let P1 toggle. You can write to P1 directly.

Wednesday, September 4, 2013

Reading Input v.s. Port Latch

When reading ports, there are two possibilities Read the status of the input pin. from external pin value MOV A, PX JNB P2.1, TARGET ; jump if P2.1 is not set JB P2.1, TARGET ; jump if P2.1 is set Figures C-11, C-12 Read the internal latch of the output port. ANL P1, A ; P1 P1 AND A ORL P1, A ; P1 P1 OR A INC P1 ; increase P1 Figure C-17 Table C-6 Read-Modify-Write Instruction (or Table 8-5) See Section 8.3

Wednesday, September 4, 2013

Reading High at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 1 P1.X pin Vcc 2. MOV A,P1 external pin=High

Q
P1.X

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1

8051 IC

Wednesday, September 4, 2013

Reading Low at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 0 Vcc 2. MOV A,P1 external pin=Low

Q
P1.X

P1.X pin

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1

8051 IC

Wednesday, September 4, 2013

Port 1 as Input Read from Port

In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV MOV MOV MOV SJMP A,#0FFH P1,A A,P1 P2,A BACK ;A=11111111B ;make P1 an input port ;get data from P0 ;send data to P2

BACK:

To be an input port, P0, P1, P2 and P3 have similar methods.

Wednesday, September 4, 2013

Instructions For Reading an Input Port

Following are instructions for reading external pins of ports: Examples MOV A,P2 JNB P2.1,TARGET JB P1.3,TARGET MOV C,P2.4 Description Bring into A the data at P2 pins Jump if pin P2.1 is low Jump if pin P1.3 is high Copy status of pin P2.4 to CY

Mnemonics MOV A,PX JNB PX.Y,.. JB PX.Y,.. MOV C,PX.Y

Wednesday, September 4, 2013

Reading Latch
Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101 ORL P1,#0F0H ;P1=11110101 1. The read latch activates TB2 and bring the data from the Q latch into CPU. Read P1.0=0 2. CPU performs an operation. This data is ORed with bit 1 of register A. Get 1. 3. The latch is modified. D latch of P1.0 has value 1. 4. The result is written to the external pin. External pin (pin 1: P1.0) has value 1.

Wednesday, September 4, 2013

Reading the Latch

1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially) Read latch TB2 2. CPU compute P1.X OR 1 Internal CPU bus 1 Write to latch 3. write result to latch Read pin=0 Read latch=0 Write to latch=1 Load(L1) 0 0 0 1 4. P1.X=1 P1.X pin Vcc

Q
P1.X

Clk

M1

TB1 Read pin 8051 IC

Wednesday, September 4, 2013

Read-modify-write Feature
Read-modify-write Instructions Table C-6 This features combines 3 actions in a single instruction 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin Note that 8 pins of P1 work independently.

Wednesday, September 4, 2013

Port 1 as Input Read from latch

Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN Note that the XOR of 55H and FFH gives AAH. XOR of AAH and FFH gives 55H. The instruction read the data in the latch (not from the pin). The instruction result will put into the latch and the pin.

Wednesday, September 4, 2013

Read-Modify-Write Instructions
Mnemonics
ANL

Example
ANL P1,A

ORL
XRL

ORL P1,A
XRL P1,A

JBC PX.Y, TARGET CPL

INC

JBC P1.1, TARGET CPL P1.2

INC P1

DEC DJNZ PX, TARGET MOV PX.Y,C

CLR PX.Y

DEC P1 DJNZ P1,TARGET MOV P1.2,C

CLR P1.3

SETB PX.Y

SETB P1.4

Wednesday, September 4, 2013

You are able to answer this Questions:

How to write the data to a pin How to read the data from the pin Read the value present at the external pin. Why we need to set the pin first Read the value come from the latch not from the external pin . Why the instruction is called read-modify write?

Wednesday, September 4, 2013

Other Pins
P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output.

Wednesday, September 4, 2013

A Pin of Port 0
Read latch TB2

Internal CPU bus Write to latch

P1.X
Clk Q

P0.X pin M1

TB1 Read pin

P1.x
8051 IC

Wednesday, September 4, 2013

Port 0 pins 32-39

P0 is an open drain. Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. When P0 is used for simple data I/O we must connect it to external pull-up resistors. Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. With external pull-up resistors connected upon reset, port 0 is configured as an output port.

Wednesday, September 4, 2013

Port 0 with Pull-Up Resistors

Vcc 10 K

P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7

Port 0

Wednesday, September 4, 2013

Dual Role of Port 0

When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions. 8031 is capable of accessing 64K bytes of external memory. 16-bit address P0 provides both address A0-A7, P2 provides address A8-A15. Also, P0 provides data lines D0-D7. When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address. There is no need for external pull-up resistors as shown in Chapter 14.

Wednesday, September 4, 2013

74LS373
PSEN ALE P0.0 P0.7
G D

74LS373

OE OC A0 A7 D0

EA P2.0 P2.7

D7

A8 A15

8051 Wednesday, September 4, 2013

ROM

Reading ROM (1/2)

PSEN ALE P0.0 P0.7 Address D0 EA P2.0 P2.7 D7 1. Send address to ROM 2. 74373 latches the address and send to OE ROM OC G 74LS373 A0
D

A7

A8 A12

8051
Wednesday, September 4, 2013

ROM

Reading ROM (2/2)

PSEN ALE P0.0 P0.7 2. 74373 latches the address and send to ROM
G D

74LS373

OE OC A0 A7 D0

Address

EA P2.0 P2.7

D7 3. ROM send the instruction back A8 A12

8051 Wednesday, September 4, 2013

ROM

ALE Pin
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
When ALE=0, P0 provides data D0-D7. When ALE=1, P0 provides address A0-A7. The reason is to allow P0 to multiplex address and data.

Wednesday, September 4, 2013

Port 2 pins 21-28

Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. In an 8031-based system, P2 are used to provide address A8-A15.

Wednesday, September 4, 2013

Port 3 pins 10-17

Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. Port 3 has the additional function of providing signals. Serial communications signal RxD, TxD Chapter 10 External interrupt /INT0, /INT1 Chapter 11 Timer/counter T0, T1 Chapter 9 External memory accesses in 8031-based system /WR, /RD Chapter 14
Wednesday, September 4, 2013

Port 3 Alternate Functions

P3 Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17

Wednesday, September 4, 2013