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    NMOS Logic Circuits: But, If The PDN Is Conducting, Current Will Flow (Will Low

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    rosan.sapkota
    This document discusses NMOS logic circuits, which use a single large resistor as a pull-up network rather than a pull-up transistor network. With NMOS logic, current flows when the output is low, resulting in non-zero static power dissipation and a non-ideal low output voltage. Additionally, resistors are difficult to implement in integrated circuits. However, replacing the pull-up resistor with an active load solves this issue. NMOS logic simplifies circuitry by reducing the number of required devices but has disadvantages compared to CMOS logic.

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    NMOS Logic Circuits: But, If The PDN Is Conducting, Current Will Flow (Will Low

    Uploaded by

    rosan.sapkota
    10 views2 pages
    This document discusses NMOS logic circuits, which use a single large resistor as a pull-up network rather than a pull-up transistor network. With NMOS logic, current flows when the output is low, resulting in non-zero static power dissipation and a non-ideal low output voltage. Additionally, resistors are difficult to implement in integrated circuits. However, replacing the pull-up resistor with an active load solves this issue. NMOS logic simplifies circuitry by reducing the number of required devices but has disadvantages compared to CMOS logic.

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    Logic and gates

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    NMOS Logic Circuits

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    This document discusses NMOS logic circuits, which use a single large resistor as a pull-up network rather than a pull-up transistor network. With NMOS logic, current flows when the output is low, resulting in non-zero static power dissipation and a non-ideal low output voltage. Additionally, resistors are difficult to implement in integrated circuits. However, replacing the pull-up resistor with an active load solves this issue. NMOS logic simplifies circuitry by reducing the number of required devices but has disadvantages compared to CMOS logic.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    10 views2 pages

    NMOS Logic Circuits: But, If The PDN Is Conducting, Current Will Flow (Will Low

    Uploaded by

    rosan.sapkota
    This document discusses NMOS logic circuits, which use a single large resistor as a pull-up network rather than a pull-up transistor network. With NMOS logic, current flows when the output is low, resulting in non-zero static power dissipation and a non-ideal low output voltage. Additionally, resistors are difficult to implement in integrated circuits. However, replacing the pull-up resistor with an active load solves this issue. NMOS logic simplifies circuitry by reducing the number of required devices but has disadvantages compared to CMOS logic.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    11/19/2004

    NMOS Logic Circuits.doc

    1/2

    NMOS Logic Circuits


    An alternative way to construct a digital logic gate is to simply use a single large resistor as the pull-up network!

    VDD iR
    Y

    If the PDN is open, no current will flow (iR =0), and thus there will be no voltage drop across the Pull-Up Resistor Rthe output will be high, just like before! But, if the PDN is conducting, current will flow (iR 0 ), and

    thus there will be a large voltage drop across Rthe output will be low (sort of)!

    Jim Stiles

    The Univ. of Kansas

    Dept. of EECS

    11/19/2004

    NMOS Logic Circuits.doc

    2/2

    This method of constructing digital devices is called NMOS logic (for hopefully obvious reasons!).

    Q: Why would we want use NMOS logic? A: Replacing the PUN with a single resistor greatly simplifies and shrinks the circuit. For complex gates (i.e., gates with many inputs), we can reduce the number of required devices (transistors and resistors) by nearly half! Q: Yikes! This seems to be a lot better. Why wouldnt we

    always use NMOS logic?

    A: There are two really big problems with NMOS logic (at least, when compared to CMOS): 1. Since current flows when the output is low, the static power dissipation is not zero. 2. Since current flows when the output is low, VOL is not equal to its ideal value of zero (i.e., VOL 0 )!
    Additionally, there is one more problem when implementing NMOS in integrated circuits. IC resistors are (relatively) very large and difficult to construct.

    This problem, though, is easily solvedwe replace the pullup resistor with an active load.

    Jim Stiles

    The Univ. of Kansas

    Dept. of EECS

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