Bit Error Recognition and Correction

Experiment objective In this experiment we will investigate the generation of parity bits (even parity) as well recognition of one bit errors through parity comparison. In order to carry out recognition and correction of 1-bit errors a transmission of 4 check bits is undertaken. Equipment procedure Section a) Generation of parity bits and recognition of one bit errors through check bit comparison. - Set the switches on the training panel DATA SOURCE/PARITY GENERATOR to the following positions: DATA SELECT: Input switches: Mode: BAUD RATE: ERROR: manual input all switches se to 0 (downwards) 9+2 bit (asynchronous, 1 parity bit) 2400 bits/s OFF

- Also set the mode switch on the training panel DISPLAY/PARITY CHECK INDICATOR to 9+2. The SYNC switch is set to external as this prevents the shift register from running through all the bits. - Switch on all of the bits of the data word one after the order while-at the same time observing bit 9 in the shift register. This bit is the so-called parity bit. - With any given input pattern count the number of 1 bits in the shift register. They must always be an even number because the so-called even parity is being used here. - The transmitted bit pattern including the parity appears in the shift register of the training panel DISPLAY/PARITY CHECK INDICATOR. The parity bit is calculated anew based on the transmitted 8 data bits and indicated with the LED P1. If the transmitted parity bit does not have the same value as the newly calculated one, a 1-bit transmission error has occurred. The comparison of the two parity bits is carried out via an XOR logic operation. The result of the logic operation is indicated in the box SYNDROME WORD GENERATOR by the LED F1. - The ERROR switch on the training panel DATA SOURCE/PARITY GENERATOR is used to generate specific bit errors, whereby the original bit is simply inverted. Here, both single 19 as well as bit combinations 1+2+3 and 1+2 can be corrupted. The start bit in asynchronous transmission is not affected by the ERROR switch. If present, bit 9 is either a stop bit or a parity bit. - Set the ERROR switch to various positions and observe the effects on the receivers shift register (the transmitters shift register remains unchanged). This error generation can also be observed on the screen of the oscilloscope. - Set any given single error and, if desired, alter the data word to be transmitted. Al single errors are recognized and displayed via the LED F1. - Set the ERROR switch to the position 1+2 (far right stop). Double errors cannot be detected. This applies generally for every number of errors. - Set the ERROR switch to the position 1+2+3 (one setting back). In contrast triple errors can be recognized just like each uneven number of errors. - In position 9 of the ERROR switch the parity bit itself is destroyed. The error is also recognized. Section b) Generation of 4 check bits during 12 bit transmission Recognition and correction of 1 bit errors, recognition of multiple errors -- Set the switches on the training panel DATA SOURCE/PARITY GENERATOR to the following positions:

DATA SELECT: Input switches: Mode: BAUD RATE: ERROR:

manual input all switches se to 0 (downwards) 12 bit (synchronous, 4 parity bits) 2400 bits/s OFF

- Also set the mode switch on the training panel DISPLAY/PARITY CHECK INDICATOR to 12. The SYNC switch is set to external, in order to avoid synchronous problems for faulty data bits. - Set one data bit to 1 respectively (all other bits remain set to 0) and observe here which parity bits change. The bits 912 in the shift register correspond to the parity bits P1P4. Fill out the Table Ex3-1 w found on the worksheet. - Answer question 1 on the worksheet (Section b)! Check your results by setting the bit combination 10010010 and reading off the parity bits. - The operating procedure in the receiver initially corresponds to that of the bit error recognition with only one parity bit, but with the exception here that now for every four bits transmitted, there is a new calculation and comparison carried out. The four resulting bits of the comparison operation form the so-called syndrome word. They are displayed in the box SYNDROME WORD GENERATOR. As long as there is no transmission error, all of the four bits syndrome word must have the value 20 (LEDs remain unlit). - Answer question 2 on the worksheet (Section b)! Test your result by setting different bit patterns and errors and observing the changes occurring to the syndrome word. - Fill in the missing values in the Table Ex 3-2w. The first section of the Table is arranged according to error positions, the second part according to syndrome words. Evaluation Experiment 3 Section a) Questions 1) What value does the `parity bit have for the input bit pattern 10010010? 2) What happens when only the parity bit itself is faulty during transmission? 3) Why can an even numbe4r of bit errors in a code word not be recognized through the use of only one parity bit? Section b) Table Ex3-1 Arrangement check bits/data bits Questions 1) Which values do the 4 parity bits have in the data word 10010010? Use the Table Ex3-1w to answer this question! 2) On what is the generated syndrome word dependent? Please mark the correct answer! () on the transmitted bit pattern () on the fault position Table Ex3-2w Arrangement fault position/syndrome word.