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Inverter Netlist

This document defines a CMOS inverter circuit with an NMOS and PMOS transistor between power (VDD) and ground. It specifies the transistor sizes and models, performs a DC sweep of the input voltage VIN from 0 to 5V in 0.01V steps, and prints the node voltages V(1), V(2), V(3) at each step.

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thesovereignmoonlove
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305 views1 page

Inverter Netlist

This document defines a CMOS inverter circuit with an NMOS and PMOS transistor between power (VDD) and ground. It specifies the transistor sizes and models, performs a DC sweep of the input voltage VIN from 0 to 5V in 0.01V steps, and prints the node voltages V(1), V(2), V(3) at each step.

Uploaded by

thesovereignmoonlove
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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CMOS INVERTER

VDD 1 0 5
VIN 2 0
MQ1 1 2 3 1 PMOD1
MQ2 3 2 0 0 NMOD1
.DC VIN 0. 5. .01

* NMOS MODEL DEFINITION


.MODEL NMOD1 NMOS (L=3U W=6U KP=69U GAMMA=0.37
+LAMBDA=0.06 RD=1 RS=1 VTO=1.0 TOX=0.04U
+CBD=2F CBS=2F CJ=200U CGBO=200P CGSO=40P CGDO=40P)

* PMOS MODEL DEFINITION


.MODEL PMOD1 PMOS (L=3U W=6U KP=34.5U GAMMA=-0.37
+LAMBDA=0.06 RD=1 RS=1 VTO=-1.0 TOX=0.04U
+CBD=2F CBS=2F CJ=200U CGBO=200P CGSO=40P CGDO=40P)

.PRINT DC V(1) V(2) V(3)


.PROBE
.END

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