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Lecture 8: - Don't Delay: Make Sure You Have A Working - Additional Resources

This document provides an overview of Verilog hardware description language (HDL) and the digital circuit design flow using Verilog. It discusses different types of Verilog modules, syntax, operators, vectors, module instantiation, testbenches, and provides a full example of designing a circuit to determine the number of days in a month using a dataflow style in Verilog. Key topics covered include module definition, always blocks, case statements, parameter passing, testbenches, and simulation.

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Minh Hoang
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28 views

Lecture 8: - Don't Delay: Make Sure You Have A Working - Additional Resources

This document provides an overview of Verilog hardware description language (HDL) and the digital circuit design flow using Verilog. It discusses different types of Verilog modules, syntax, operators, vectors, module instantiation, testbenches, and provides a full example of designing a circuit to determine the number of days in a month using a dataflow style in Verilog. Key topics covered include module definition, always blocks, case statements, parameter passing, testbenches, and simulation.

Uploaded by

Minh Hoang
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture8

Dontdelay:makesureyouhaveaworking genvironmentASAP Verilog AdditionalResources


ClassWebSite(Resources):Linetoonlinetutorial ClassWebSite(Textbook):Palnitkar textbook

ECE171 DigitalCircuits
Prof.MarkG.Faust MaseehCollegeofEngineering andComputerScience

HardwareDescriptionLanguages (HDLs)
Benefits
Complete,unambiguousspecificationofdesign
Inputs, p ,outputs, p ,behavior, ,timing g

Simulationfordesigndebug Synthesisforphysicalrealizationofdesign

Severalwidelyused
ABEL primarilyforPLDs VHDL(VHSICHardwareDescriptionLanguage) Verilog(1995, (1995 2001)

Numeroustoolsandvendors
Capture,edit,simulate,synthesize
3

DesignFlow

Modules

Differenttypesofmoduledescriptions
1. 2. 3. 4. Structural actualgates Behavioral behavior,nostructure Dataflow simpleoutput F(inputs) Combinationofabove
5

VerilogSyntax
Casesensitive
module,Module,MODULEnotsame Reservedwordsarelowercase(e.g.module) Userdefinedidentifiers(e.g. (e g variables, variables modules, modules ports)norequirements
Usefulconvention:usemixedcase,leadingcapitals BufferFullnotbufferfullorBUFFERFULL

Whitespace(e.g.spaces,linebreaks)generallyignored
Useittomakeyourmodulesreadable

Comments
//singlelinecomments / /* multipleline comments */

VerilogSyntax
Identifiers
Beginwithletterorunderscore Containletters,digits,underscores,$

4V Valued l dLogic L i
0,1,X,Z

Literals(inlanguagesense)
nBdddd n Bdddd
n=(decimal)numberofbits B=radix
b=binary o=octal h=hexadecimal d=decimal

R R R R R

= = = = =

4b1010; 4hA; 4o12; 4d10; 10;

dddd=digitsindesignatedradix

Verilog
Operators
BitwiseBoolean Arithmeticandshift Logical Misc:concatenation,replication p

Verilog
Vectors
Signals g orports p withwidth Bitselect
Zbus[5] [ ]

Partselect
word1[15:8]

Verilog
Instantiatingamodule
component p name instanceidentifier

Twoformsofparameterlists
Byorderofdeclaration Byexplicitportname

10

VerilogDataflowExample:FullAdder
CI A B 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 CO S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

11

VerilogStructuralExample:FullAdder

12

ATestBench
Providesstimulustomodulebeingtested Mustobeyinterfaceandprotocol
Interface: I t f signal i ldirection di ti and dwidth idth(e.g. ( bus) b ) Protocol:timingandedgerelationships

Facilitatesresponse p frommodule
TestBench canbewrittentoindependentlyverifyresponse Humancanexaminewaveformsproducedinsimulation TestBench canbewrittentoformatresponse(e.g. (e g table) forlaterexaminationorprocessing

IsaVerilogmodule!
13

ATestBench

0000 1100 1010

Module

TestBench
TestBench instantiatesmoduleandprovidesnecessaryinputs,calledtestvectors Declaresregisters(reg)whichwillbeconnectedtothemoduleinputports Declareswireswhichwillbeconnectedtothemoduleoutputports
14

TestbenchExample

15

ACompleteExampleUsing DataflowStyle
Designacircuitthattakesasinputabinaryrepresentationofamonth,andan additionalBooleaninputLeapYear (LY)whichis1ifthecurrentyearisaleap year,anddeterminesthenumberofdaysinthemonth.Thecircuitshouldhave f outputs:D28, four D28 D29 D29,D30 D30,D31which hi haretruewhen h the h given i month hhas h exactlytheindicatednumberofdays.Forexample,ifthemonthinputs indicateMarch,theoutputD31willbe1whileD30,D29andD28willbe0.Use thefewestnumberofbitstoencodethemonthinput.
Methodology(willvarywithtargetimplementation!) 1. Drawablackbox,labelinputsandoutputs(I/Os) 2. Confirmformats,representations,timingofI/Os 3 3. C t atruth Create t tht table bl 4. UseKmapstoobtainminimized/reducedequations 5. TranslateequationstoVerilogdataflowstylesyntax 6. Createatestbenchtoappropriatelytestthemodule Appropriatemaymeanexhaustivetesting 7 7. C Compile il and dtest 8. Debug:Examyourresults;ifnotasexpected,workbackwards 9. Baskinyoursuccess

16

BlackBoxandTruthtable
Jan Feb Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec -unused-unusedd -unused-unusedInputs Outputs Month Leap Encoded Year M3 M2 M1 M0 LY D28 D29 D30 D31 0 0 0 0 X 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 X 0 0 0 1 0 0 1 1 X 0 0 1 0 0 1 0 0 X 0 0 0 1 0 1 0 1 X 0 0 1 0 0 1 1 0 X 0 0 0 1 0 1 1 1 X 0 0 0 1 1 0 0 0 X 0 0 1 0 1 0 0 1 X 0 0 0 1 1 0 1 0 X 0 0 1 0 1 0 1 1 X 0 0 0 1 1 1 0 0 X X X X X 1 1 0 1 X X X X X 1 1 1 0 X X X X X 1 1 1 1 X X X X X

D31 D30

LY

DaysInMonth

D29 D28 28

UseofX(dontcare)ininputsreducesrowsintruthtableandhelpstoclarifyfunctionality UseofXinoutputsmayleadtosimplerBooleanequations
17

KMapsandReducedEquations
Jan Feb F b Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec unused -unused-unused-unused-unusedInputs Outputs Month Leap Encoded Year M3 M2 M1 M0 LY D28 D29 D30 D31 0 0 0 0 X 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 X 0 0 0 1 0 0 1 1 X 0 0 1 0 0 1 0 0 X 0 0 0 1 0 1 0 1 X 0 0 1 0 0 1 1 0 X 0 0 0 1 0 1 1 1 X 0 0 0 1 1 0 0 0 X 0 0 1 0 1 0 0 1 X 0 0 0 1 1 0 1 0 X 0 0 1 0 1 0 1 1 X 0 0 0 1 1 1 0 0 X X X X X 1 1 0 1 X X X X X 1 1 1 0 X X X X X 1 1 1 1 X X X X X

18

VerilogDataflowStyleModule
module DaysInMonth(M3,M2,M1,M0,LY,D28,D29,D30,D31); input M3,M2,M1,M0; // encoded value of month // Jan = 0000, Feb = 0001, etc // 1 if leap year // // // // 1 1 1 1 if if if if month month month month has has has has 28 29 30 31 days days days days

Usuallyablockcommentherewith descriptionofmodule, module author, author date, date otherpertinentinformation

input LY; output output output output D28; D29; D30; D31;

D31 D30

LY

DaysInMonth

D29 D28 28

assign #6 D28 = ~M3 & ~M2 & ~M1 & M0 & ~LY; assign #6 D29 = ~M3 & ~M2 & ~M1 & M0 & assign #6 D30 = M3 & ~M0 | M2 & ~M1 & M0 | ~M3 & ~M2 & M1 & M0; M3 & M0 | ~M3 & ~M0 | M2 & M1; LY;

D28 = M3 M2 M1 M0 LY D29 = M3 M2 M1 M0 LY

assign #6 D31 =

D30 = M3 M0 + M2 M1 M0 + M3 M2 M1 M0
D31 = M3 M0 + M3 M0 + M2 M1

endmodule

Delay

19

VerilogTestbench
module TestDays(); reg M3,M2,M1,M0; reg LY; wire D28, D29, D30, D31; DaysInMonth D1 (M3,M2,M1,M0,LY,D28,D29,D30,D31); initial begin #10 LY = 1'bx; M3 = 1'b0; M2 = 1'b0; M1 = 1'b0; M0 = 1'b0; #10 M3 = 1'b0; M2 = 1'b0; M1 = 1'b0; M0 = 1'b1; LY = 1'b0; // Not Leap Year #10 LY = 1'b1; // Leap Year

Useofdontcareinputs Abilitytoeasilydetermineallinputvalues f anytestvector for


module DaysInMonth(M3,M2,M1,M0,LY,D28,D29,D30,D31); input M3,M2,M1,M0; // Jan // Feb input LY; output output output output // Mar // Apr // May // Jun // J Jul l // Aug // Sep // Oct // Nov // Dec assign #6 D31 = D28; D29; D30; D31; // encoded value of month // Jan = 0000, Feb = 0001

// 1 if leap year // // // // 1 1 1 1 if if if if month month month month has has has has 28 29 30 31 days days days days

#10 LY = 1'bx; M3 = 1'b0; M2 = 1'b0; M1 = 1'b1; M0 = 1'b0; #10 M3 = 1'b0; M2 = 1'b0; M1 = 1'b1; M0 = 1'b1; #10 M3 = 1'b0; M2 = 1'b1; M1 = 1'b0; M0 = 1'b0; #10 M3 = 1'b0; M2 = 1'b1; M1 = 1'b0; M0 = 1'b1; #10 M3 = 1'b0 1'b0; M2 = 1'b1 1'b1; M1 = 1'b1 1'b1; M0 = 1'b0 1'b0; #10 M3 = 1'b0; M2 = 1'b1; M1 = 1'b1; M0 = 1'b1; #10 M3 = 1'b1; M2 = 1'b0; M1 = 1'b0; M0 = 1'b0; #10 M3 = 1'b1; M2 = 1'b0; M1 = 1'b0; M0 = 1'b1; # #10 M3 = 1'b1; ; M2 = 1'b0; ; M1 = 1'b1; ; M0 = 1'b0; ; #10 M3 = 1'b1; M2 = 1'b0; M1 = 1'b1; M0 = 1'b1; #20 $finish(); end endmodule

assign #6 D28 = ~M3 & ~M2 & ~M1 & M0 & ~LY; assign #6 D29 = ~M3 & ~M2 & ~M1 & M0 & assign #6 D30 = M3 & ~M0 | M2 & ~M1 M1 & M0 | ~M3 & ~M2 & M1 & M0; M3 & M0 | ~M3 & ~M0 | M2 & M1; LY;

endmodule

20

TheTimingDiagram

21

ABetterSolution:Buses(Vectors)
module DaysInMonth(M,LY,D28,D29,D30,D31); i input t [3 [3:0] 0] M M; // encoded d d value l of f month th // Jan = 0000, Feb = 0001, etc // 1 if leap year // // // // 1 1 1 1 if if if if month month month month has has has has 28 29 30 31 days days days days input LY;

D31 D30

LY

DaysInMonth

D29 D28 28

output output output output

D28; D29; D30; D31;

assign #6 D28 = ~M[3] & ~M[2] & ~M[1] & M[0] & ~LY; assign #6 D29 = ~M[3] & ~M[2] & ~M[1] & M[0] & assign #6 D30 = M[3] & ~M[0] | M[2] & ~M[1] & M[0] | ~M[3] M[3] & ~M[2] M[2] & M[1] & M[0] M[0]; M[3] & M[0] | ~M[3] & ~M[0] | M[2] & M[1]; LY;

assign #6 D31 =

endmodule

22

ABetterSolution:Buses(Vectors)
Porttypesmustmatch
module DaysInMonth(M,LY,D28,D29,D30,D31); DaysInMonth(M LY D28 D29 D30 D31); input [3:0] M; // encoded value of month // Jan = 0000, Feb = 0001, etc // 1 if leap year // // // // 1 1 1 1 if if if if month month month month has has has has 28 29 30 31 days days days days
module TestDays(); reg [3:0] M; reg LY; wire D28,D29,D30,D31; D28 D29 D30 D31; DaysInMonth D1 (M,LY,D28,D29,D30,D31); initial begin #10 LY= 1'bx; M= 4b0000; #10 M= 4b0001; LY= 0; #10 LY= 1; #10 LY LY= 1'bx; 1'b M= 4b0010; #10 M= 4b0011; #10 M= 4b0100; #10 M= 4b0101; #10 M= 4b0110; #10 # 0 M= 4b0111; b0 ; #10 M= 4b1000; #10 M= 4b1001; #10 M= 4b1010; #10 M= 4b1011; #20 $finish(); end endmodule

input LY; output output output output D28; D29; D30; D31;

// Jan // Feb

assign #6 D28 = ~M[3] & ~M[2] & ~M[1] & M[0] & ~LY; assign #6 D29 = ~M[3] & ~M[2] & ~M[1] & M[0] & assign #6 D30 = M[3] & ~M[0] M[0] | M[2] & ~M[1] & M[0] | ~M[3] & ~M[2] & M[1] & M[0]; M[3] & M[0] | ~M[3] & ~M[0] | M[2] & M[1]; LY;

// // // // // // // // // //

Mar Apr May Jun Jul Aug ug Sep Oct Nov Dec

assign #6 D31 =

endmodule

23

TestBenches withBuses

Busesbundledtogetherin waveformdisplayimprove readability d bilit


24

module TestDays();

AlternativeTestBenches with Buses


M tools Most l provide id ameanstochange h di display l radix di

reg [3:0] M; reg LY; wire D28, D29, D30, D31; DaysInMonth D1 (M,LY,D28,D29,D30,D31); initial begin #10 LY= 1 1'bx; bx; M= 0; // Jan #10 M= 1; // Feb LY= 0; #10 LY= 1; #10 LY= 1'bx; M= 2; // #10 M= 3; // #10 M= 4; // #10 M= 5; // #10 M= 6; // #10 M= M 7; 7 // #10 M= 8; // #10 M= 9; // #10 M= 10; // #10 M= 11; //

Mar Apr May Jun Jul A Aug Sep Oct Nov Dec

# #20 $ $finish(); (); end endmodule

25

TestBenches withBehavioralCode
module TestDays(); reg [3:0]M; reg LY; wire D28, D29, D30, D31;

B h i lcode Behavioral d tofacilitate f ili creation i of ftestvectors Behavioralcodeforautomatingchecking e g consideramethodtoverifyamultiplierdesign e.g.

DaysInMonth D1 (M, LY, D28, D29, D30, D31); initial begin for (M = 0; M <= 11; M=M+1) begin LY = 0; #10; LY = 1; #10; end d $finish(); end endmodule

26

D28 = M3 M2 M1 M0 LY D29 = M3 M2 M1 M0 LY

D30 = M3 M0 + M2 M1 M0 + M3 M2 M1 M0
D31 = M3 M0 + M3 M0 + M2 M1

27

VerilogStructuralStyleModule
module DaysInMonth(M,LY,D28,D29,D30,D31); input [3:0]M; input LY; // encoded value of month // Jan = 0000, Feb = 0001, etc // 1 if leap year days days days days output D28; // 1 if month has 28 output D29; // 1 if month has 29 output D30; // 1 if month has 30 output D31; // 1 if month has 31 wire T1,T2,T3,T4,T5,T6; wire M3bar,M2bar,M1bar,M0bar,Lybar; not #(3,3) U1a(M3bar,M[3]), U1b(M2bar,M[2]), U1c(M1bar,M[1]), U1d(M0bar M[0]) U1d(M0bar,M[0]), U1e(LYbar,LY); and #(5,4) U2a(D28,M3bar,M2bar,M1bar,M[0],LYbar), U2b(D29,M3bar,M2bar,M1bar,M[0],LY); and #(5,4) U3a(T1,M[3],M0bar), ( , [ ], ), U4a(T2,M[2],M1bar,M[0]), U5a(T3,M3bar,M2bar,M[1],M[0]); or #(5,5) U6a(D30,T1,T2,T3); and #(5,4) U3b(T4,M[3],M[0]), U3c(T5,M3bar,M0bar), 3 ( 3 0 ) U3d(T6,M[2],M[1]); or #(5,5) U6b(D31,T4,T5,T6); endmodule

Wiredeclarationsomittedforbrevity Reflectsactualimplementation Primitives:or,and,nand,xor,xnor,nor,not Variablenumberofinputs Outputisfirstport Wiresused dtoconnectgateoutputs/inputs / Commaseparatedlistwillsharetpd Canhaveasymmetricdelays(tPLH tPHL)

28

HierarchicalStructural Description

29

TimingDiagrams

30

TimingDiagrams

31

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