Adv. Dig. Design S.

7 August 18, 2003

i=0
a
i
b
i
= [ a
n1
. . . a
1
a
0
]
_

_
b
n1
.
.
.
b
1
b
0
_

_
(7.1)
Eqn (7.1) says that a number is a sum of products of digits and
weights.
Examples
The twos complement system
a = [ 1 0 1 1 0
. .
A
4:0
]
_

_
2
4
2
3
2
2
2
1
2
0
_

_
= 2
4
+ 2
2
+ 2
1
= 10 ; a
i
{0, 1}
b = 2
Note, that in the twos complement system the most signicant digit is
negative (or zero). The bar over the digit is its sign not the logic
complement.
A.P.Papli nski 71
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A signed-digit ternary system
a = [ 2

1 0 1
. .
A
3:0
]
_

_
3
3
3
2
3
1
3
0
_

_
= 2 3
3
3
2
+ 1 = 46 ; a
i
{2, 1, 0}
b = 3
A signed-digit binary system
a
i
{1, 0, 1} ; b = 2
a = (1 1 0 1
. .
A
3:0
)
2
= 2
3
+ 2
2
1 = 5 ;
7.2 The Booths multiplier
In the context of multiplication it is often convenient to convert a
twos-complement number into a signed-digit form. The multiplication
method using the multiplier in the signed-digit form is known as the
Booths method.
Let
Q
n1:0
= [ q
n1
q
1
q
0
] , where q
i
{0, 1} .
Consider now the following identity:
q
i
= 2q
i
q
i
Using the above identity it is now possible to obtain another numeral
representation of the number q in the following way:
A.P.Papli nski 72
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2
n1
2
n2
2
1
2
0
Q
n1:0
= [ q
n1
q
n2
q
1
q
0
]
= [ q
n1
2q
n2
q
n2
2q
1
q
1
2q
0
q
0
]
= [ q
n1
+ q
n2
q
n2
+ q
n3
q
1
+ q
0
q
0
+ 0 ]

Q
n1:0
= [ q
n1
q
n2
q
1
q
0
]
where
q
i
= q
i
+ q
i1
, or,
q
i
q
i1
q
i
0 0 0
0 1 +1
1 0 1
1 1 0
, and q
1
= 0 . (7.2)
Hence, after re-coding, the Booths multiplier is

Q
n1:0
= [ q
n1
q
1
q
0
] , where q
i
{1, 0, +1} .
Obviously the value of the multiplier has not changed in the re-coding
process and we have:
q = q
n1
2
n1
+
n2

i=0
q
i
2
i
=
n1

i=0
q
i
2
i
Example
(1 0 0 1 0 1 1)
2
= 2
6
+ 2
3
+ 2 + 1 = 53
(1 0 1 1 1 0 1)
2
= 2
6
+ 2
4
2
3
+ 2
2
1 = 53
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7.3 Multiplication methods
Consider multiplication of two numbers represented by numerals Q
and D
P = Q D
Multiplicand
e
eu
Product

#
Multiplier
g
g
g
gy
If the multiplier, Q, and the multiplicand, D, are represented by the
ndigit and mdigit numerals, respectively, then the product, P, is
represented by the (n+m1)digit numeral as follows:
Q
n1:0
= [ q
n1
. . . q
1
q
0
]
D
m1:0
= [ d
m1
. . . d
1
d
0
]
P
k1:0
= [ a
k1
. . . a
1
a
0
] ; k = m + n
If we use the above notation, then the product numeral, P
k1:0
, can be
elegantly expressed as a matrix product of the multiplier numeral,
Q
n1:0
, and the Sylvester resultant matrix of the multiplicand
D
m1:0

n1
P
k1:0
= Q
n1:0
D
m1:0

n1
(7.3)
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The Sylvester resultant matrix, which also known as the convolution
matrix, is formed from the shifted numeral D
m1:0
in the following
way:
D
m1:0

n1
=
_

_
d
m1
d
m2
d
0
d
m1
d
m2
d
0
0
0
.
.
.
.
.
.
.
.
.
d
m1
d
m2
d
0
_

_
T
n
c
'
n+m1
E
(7.4)
The angle brackets have been used to denote the resultant matrix. The
bold 0s in the resultant of eqn (7.4), represent appropriate triangles of
zeroes.
In general, eqn (7.3) can be thought of as a parallelised description of
the multiplication algorithm of two numerals.
Each row of the resultant represents a shifted numeral D
m1:0
which
is multiplied by the respective digit of the multiplier.
Subsequently, the columns of the resultant are summed up to give the
pseudo-digits of the result.
The carry propagation is neglected at this level of the multiplication
algorithm.
In this sense that the carry is incorporated into the pseudo-digits of
the result.
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Example
Consider multiplication of the following decimal numerals
P
5:0
= Q
2:0
D
3:0
= 3 2 1
. .
Q
2:0
1 2 3 4
. .
D
3:0
This multiplication operation can be described in the following matrix
form:
P
5:0
= Q
2:0
D
3:0

2
_
3 2 1
_

_

_
1 2 3 4 0 0
0 1 2 3 4 0
0 0 1 2 3 4
_

_
=

cl
_

_
3 6 9 12 0 0
0 2 4 6 8 0
0 0 1 2 3 4
_

_
=
_
3 8 14 20 11 4
_
where

cl
denotes the column-wise summation, that is, addition of
rows of the matrix.
The product numeral P
5:0
contains pseudo-digits, that is, digits
which are greater than the base b = 10. In order to obtain the proper
digits, the following carry propagation operation is required:
3 8 4 0 1 4
0 1 2 1 0 0
P
5:0
= 3 9 6 1 1 4 = 321 1234
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The above example can easily be extended into a generic
multiplication algorithm. If we combine eqns (7.3) and (7.4) we
obtain the following expression describing the rst step of a generic
multiplication algorithm:
P
k1:0
=

cl
_

_
q
n1
[d
m1
d
1
d
0
0 0 ]
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
q
1
[ 0 d
m1
d
1
d
0
0 ]
q
0
[ 0 0 d
m1
d
1
d
0
]
_

_
(7.5)
Denoting the products of individual digits of multiplier and the
multiplicand by
r
ij
= q
i
d
j
we obtain from eqn (7.5)
P
k1:0
=

cl
_

_
r
n1,m1
r
n1,1
r
n1,0
0 0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0 r
1,m1
r
11
r
10
0
0 0 r
0,m1
r
01
r
00
_

_
(7.6)
In a binary case, when, in general, the digits q
i
, d
j
{1, 0, +1}, the
elementary products are also, r
ij
{1, 0, +1}.
In the second step of a generic multiplication algorithm, the
elementary products in the matrix (7.6), are to be summed up in
columns. For a purely binary case, this operation yields the counts of
ones in each column.
Finally, the column sums must be added together, in a step which
involves carry propagation.
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The above generic multiplication algorithm can be implemented in at
least the following ways:
The word-serial algorithm. This is probably the most popular
algorithm in which the nal product is formed by adding rows of
the matrix (7.6) one by one. In practice, we employ a single
mbit adder, and the partial products are shifted one position right
between n successive steps of the multiplication process.
Parallel algorithms. These are the fastest implementations of the
multiplication operation. In this case we use enough adders
(approximately n m-bit adders), so that the multiplication
operation is performed in one step.
Two groups of algorithms belonging to this class are called the
matrix method, and the Wallace-tree method, respectively.
The column-serial algorithms. In this case, rst elementary products
in a column of the matrix (7.6) are added serially, and then
operation is repeated for the next more signicant column. In
other words, there is a single 1-bit adder, and every addition
operation is performed in m steps. This is clearly the slowest
method, but the amount of hardware required is minimal.
The distributed arithmetic algorithms. We present details of such
algorithms in the subsequent sections.
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7.4 Word-Serial Multiplication Processor the Booths algorithm
The word-serial Booths algorithm is probably the most popular
multiplication algorithm used in most of the general purpose
processors.
Let the product P be
P = Q D
Multiplicand
e
eu
Product

#
Multiplier
g
g
g
gy
and the multiplier, Q = {q
i
}
n1:0
, and the multiplicand,
D = {d
i
}
m1:0
be represented in the twos-complement system by the
ndigit and mdigit numerals, respectively. The product, P, is
represented by the (n+m1)digit numeral.
The one-bit Booths multiplication algorithm can be described by the
following pseudo-code:
P[0] = 0 ; q
1
= 0 ;
for (i = 0 ; i < n ; i++ ) {
q
i
= q
i
+ q
i1
;
P[i + 1] = (P[i] + q
i
D) 2
1
;
}
q
i
q
i1
q
i
0 0 0
0 1 +1
1 0 1
1 1 0
Examination of the pseudo-code reveals the following details of the
algorithm:
The partial product, P[i], is initialised to zero (P[0] = 0).
The additional, q
1
, bit is appended to the multiplier and is also
initialised to zero.
At each step, a Booths multiplier digit, q
i
= q
i
+ q
i1
( q
i
{1, 0, +1}), is formed from a pair of adjacent multiplier
digits, q
i
, q
i1
{0, +1}.
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The Booths multiplier digit, q
i
is used to determine the way in
which the next partial product, P[i + 1], is calculated from the
previous one.
At each multiplication step one of three possible operations is
performed, namely, subtraction of D, no-operation, or addition of
D, that is, either (P[i] D), or P[i], or (P[i] + D).
The result of this operation (P[i] + q
i
D), is then shifted right by
one position to form the next partial product, P[i + 1]. The
shift-right operation implements multiplication by 2
1
.
The nal product is
P = P[n] = Q D
A numerical example is given in Figure 74 and will be examined in
detailed in the subsequent section.
In the next design step, the pseudo-code description of the algorithm is
converted into a structure of the data-path and a specication of the
control unit given in a form of a ow-chart of operations performed
by the word-serial multiplication processor.
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7.5 The top-level structure of the processor
The top level schematic of the WSM processor consists of two
components, namely, the datapath and the control unit, and its structure
is given in Figure 71.
Word-Serial Multiplication Processor
Figure 71: The top level schematic of the word-serial multiplication processor
Two symbols, dpath and cntp, representing the datapath and the
control unit components, respectively, are created and instantiated into
the top level schematic wsm as in Figure 71. The brief description of
the schematic is as follows.
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It is assumed that the multiplier and the multiplicand are 8-bit
twos-complement numbers and are entered through the input
ports qq(7:0) and dd(7:0), respectively.
The 16-bit result is available at the output port aq(15:0).
The multiplication operation is initialised with the assertion of the
start signal, st.
The completion of the operation is signaled by the ready signal,
rdy, being asserted.
Refer to the ow-chart of operations for details.
The clock and reset signals are clk and rst, respectively.
The control unit generates the required 7-bit op-code op(6:0)
to specify micro-operations performed by the functional blocks of
the datapath.
Upon completion of the required number of the multiplication
steps, the step counter from the data path generates the signal zI
which is interpreted in the control unit.
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7.6 Datapath
The block diagram of the datapath is presented in Figure 72. It
consists of the registers which store variables used in the pseudo-code
(sec 7.4), and combinatorial blocks like an ALU (adder/subtractor)
which perform required operations on the stored variables.
0
fo
0:-1
q
-1
q
m
A
F
m-1:0
m
m m
D
D-REGISTER A-REGISTER
n-1:0
n
Q-REGISTER
zI
Q
n-1:-1
Q
DD AA
B A
QQ
Dop
op
clk
clk
Multiplicand
Aop
op
ALU (Adder/Subtractor)
clk
F
Fop
Qop
op
sr
clk
m-1:0
F/2 = asr(F)
Multiplier
n
m-1:0
P=(AQ)
Sop
op
0
clk
COUNTER
Sc
Figure 72: The datapath of the word-serial multiplication processor implementing
the 1-bit Booths algorithm
The main components of the data-path are as follows:
D the multiplicand register,
Q the multiplier register,
A the more-signicant half of the product register.
The least-signicant part of the product is in the Q register, so
that, the (partial) products are stored in the concatenated P = (A
Q) register (see example shown in Figure 74).
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F the ALU (Adder/Subtractor) performing operations
F <= A D, or F <= A.
The output F of the ALU is loaded into the A-register after an
arithmetic shift-right operation, asr(F) = F/2, is performed.
The least signicant bit, f
0
, is shifted into the Q-register.
Sc the step counter which counts from 0 to n 1 and generates
the signal zI when Sc = n 1.
All registers are triggered by the positive-edge of the clock signal clk,
and their operations are controlled by op-code signals which will be
examined in detail in the subsequent sections.
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7.7 State diagram of the control unit
The ow-chart of operations performed by the control unit of the
word-serial multiplier using the Booths method, that is, the state
(transition) diagram describing the control unit as the nite state
machine, is presented in Figure 73.
SM
SF
SI
st
st
zI
zI
st
st
rdy <= 1
A <= 0 , Q <= QQ ,
D <= DD , q
1
<= 0 ,
rdy <= 0, Sc <= 0
F <=
_

_
A if q
0
q
1
A + D if q
0
q
1
A D if q
0
q
1
(AQ) <= asr(F Q),
Sc <= Sc + 1,
zI <= (Sc = n 1)
QQ and DD represent the multi-
plier and the multiplicand respec-
tively.
Sc is the step counter initialised
with zero. The signal zI indi-
cates the Sc = n 1, that is, that
the last multiplication step is per-
formed.
F is the output of the ALU,
which performs conditional oper-
ations as described.
(F Q) is a concatenation of the
outputs from the adder and from
the Q register. (F Q) is arith-
metically shifted one position
right and then loaded into the
concatenation of the registers A
and Q.
st the START signal,
rdy the READY signal, as-
serted when the multiplication is
completed.
Figure 73: The ow-chart of the word-serial multiplier using the one-bit Booths
method
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In the initial state, SI, when st= 0, the multiplicand and the multiplier
are loaded into the registers D and Q respectively, and the signal rdy is
reset.
When the start signal st= 1 the control unit goes into the state SM in
which multiplication steps are repeated n times (signal zI).
In the nal state, SF, the correct result is availabe at the port (AQ).
This is indicated by the signal rdy being asserted.
In order to multiply the next numbers, the start signal, st, must go low.
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7.8 Numerical example
The operations performed by the multiplication processor can be best
explained by a numerical example presented in Figure 74. This
example of the one-bit Booths multiplication algorithm should be
examined in conjunction with the datapath and the ow-chart of the
control unit. The multiplication steps are as follows:
Initially, the multiplicand, DD, is loaded in an m-bit register D,
and the multiplier, QQ, is loaded in an n-bit register Q,
The initial value of the partial product, P[0] = 0, is loaded in the
register A.
The adder has the width m, which is equal to the number of bits
of the multiplicand, D, and to the number of bits of the more
signicant part of the partial products which are stored in the
register A.
At each step, i-th, the digit of the Booths multiplier, q
i
, is
determined from the two least-signicant bits of the register Q,
and the value q
i
D is added to the more signicant part of the
partial product, A[i].
The result of this addition, F, and the multiplier, Q, are shifted
right by one position and loaded back into a combined A Q
register.
In this way, the least signicant bits of the partial products are
gradually shifted into a register Q, while the least signicant bits
of the multiplier are shifted out of the register Q through the
additional position Q
1
.
The nal product resides in the concatenated register A Q.
A.P.Papli nski 717
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D = (101101)
2
= 19 ; QQ = (101001)
2
= 23
A[i], D Q q
1
101001 0 q
0
= q
0
+ q
1
= 1
A[0] 000000

D 010010
c
0
1
F 010011 F = A D
- 10100 1 q
1
= q
0
+ q
1
= +1
A[1] 001001 1
D 101101
F 110110 1 F = A + D
- - 1010 0 q
2
= 0
A[2] 111011 01 A[2] = A[1] 2
1
- - -101 0 q
3
= q
0
+ q
1
= 1
A[3] 111101 101

D 010010
c
0
1
F 010000 101 F = A D
- - - - 10 1 q
4
= q
0
+ q
1
= +1
A[4] 001000 0101
D 101101
F 110101 0101 F = A + D
- - - - - 1 0 q
5
= q
0
+ q
1
= 1
A[5] 111010 10101

D 010010
c
0
1
F 001101 10101 F = A D
- - - - - - 1
A[6] 000110 110101
A = A[6] = Q D = +437
Figure 74: A one-bit, word-serial Booths multiplication algorithm. A numerical
example.
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7.9 Details of hardware implementation Operations of the
data-path blocks
The top-level structure of the multiplication processor was already
discussed in sec.7.5 and presented in Figure 71.
In the subsequent sections we will discuss details of hardware
implementation of the datapath and the control unit.
A detailed block-diagram, or schematic of the datapath has been
presented in Figure 72.
Before we can attempt the detailed design of the datapath we have to
specify operations performed by its blocks in a form of the function
tables as we did it for typical sequential and combinatorial blocks in
previous sections.
This can be done by examination of the operations described in the
ow-chart of Figure 73.
With every operation which is required to perform the multiplication
steps as specied in the ow-chart, we must now associate an
operation of a specic functional block of the datapath.
The result of this examination is presented in Table 3.
For each block of the datapath we specify an operation (function) table
which lists all operations performed by the block.
Every operation is assigned a specic operation code (an op-code)
using mnemonic names like nop which stands for no operation.
Binary values of op-codes are also given in the function tables to x
our attention, but they can be changed during the design process in
order to simplify the internal structure of the components of the
datapath.
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multiplicand register, D
Dop operation
0 D D nop
1 D DD load
partial product register, A
Aop operation
0 A A nop
1 A F/2 ldAshr
2, 3 A 0 reset
multiplier register, Q
Qop operation
0 Q Q nop
1 Q shr(F(0),Q) shrQ
2, 3 Q (QQ & 0) load
step counter, Sc
Sop operation
0 Sc Sc nop
1 Sc Sc+1 count
2, 3 Sc 0 reset
ALU, F
Fop operation
0, 3 F A pass
1 F A + B add
2 F A B subtract
Table 3: Specication of operations performed by the components of the data-path
Some easy-to-miss details of operation need to be repeated from
sec.7.5:
The ldAshr operation, that is, load arithmetically shifted right
signal vector F(3..0) into A, can be more precisely described as
A <= (F(3) & F(3..1))
The Q register is an (n+1)-bit register, e.g., Q(3..-1) (warning: in
VHDL negative subscripts are not allowed). During the load
operation the additional position Q(-1) should be cleared.
The shift operation can be alternatively described as:
Q <= (F(0) & Q(3..0))
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The op-codes for the ALU, Fop, are equal to the value of the
current pair of the least signicant multiplier digits. Therefore,
we have:
Fop = Q(0:-1).
All other op-code signals can be, for convenience, collected in one
7-bit op-code word:
op(6:0) = (Dop, Aop, Qop, Sop)
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7.10 Designing the datapath
The procedure of designing the datapath consists of two main steps:
Synthesis and simulation of all components (functional blocks)
of the data path. For every block follow the steps described in the
previous sections for typical sequential and combinatorial
components.
Connection of the components into a complete datapath. This can
be achieved in one of following three ways:
Use schematic tools of the CAD package and interconnect
blocks as in Figure 72.
Write a new VHDL entity and architecture for the datapath
combining codes for the individual components.
Interconnect components using the VHDL structural design
method.
It is a good practice to simulate every new bit of the design, therefore,
we should simulate not only all components of the datapath, but the
complete datapath as well.
However, due to its complexity it may be easier to do so after the
control unit is designed and connected to the datapath.
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7.11 The control unit
The rst step in designing the control unit is the re-interpretation of the
multiplication owchart from Figure 73 which describes details of the
algorithm as an equivalent state diagram of the control unit in which
we refer to operations performed by the components of the datapath.
st
rst
stt(1:0)
zi
rdy
op(6:0)
nxt_st(1:0)
s
t
t
clk
C/L
Figure 75: The control unit as a nite state machine
The control unit is a nite state machine as in Figure 75 consisting of
the state register, stt, and combinational logic, C/L, implementing the
state transition and output functions. The state register stores the codes
of three states, SI, SM, SF encoded using two ip-ops.
The state diagram describes transitions between the states, and the
output signals generated by the control unit. These output signals
generated by the control unit are primarily the op-codes which specify
operations performed by the blocks of the datapath.
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7.11.1 The VHDL program for the control unit
The behavioural specication of the control unit can be given by the
following VHDL program. This program consists of the entity cntu
in which input/output ports are specied, and an architecture behv
which describes details of the behaviour of the control unit.
-- cntu the control unit -- by app
library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY cntu IS
PORT ( rst, clk, st, zi : IN STD_LOGIC ;
op : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ;
--- stt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
rdy : OUT STD_LOGIC
) ;
END cntu ;
ARCHITECTURE behv OF cntu IS
-- TYPE states IS (SI, SM, SF) ;
-- SIGNAL stt, nxt_st : states := SI ;
SIGNAL stt, nxt_st : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
-- we can use a "hard" encoding of states
CONSTANT SI : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;
CONSTANT SM : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;
CONSTANT SF : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10" ;
-- Internal op-code signals and related constants
SIGNAL Aop, Qop, Sop : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SIGNAL Dop : STD_LOGIC ;
CONSTANT ldD : STD_LOGIC := 1 ;
CONSTANT nopD : STD_LOGIC := 0 ;
CONSTANT nop : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;
CONSTANT ldAshr,shrQ,count: STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;
CONSTANT reset, load : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10" ;
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Adv. Dig. Design S. 7 August 18, 2003
BEGIN
-- to synthesize edge-triggered flip-flops
-- with asynchronous reset when rst = 0
clkd: PROCESS ( clk, rst)
BEGIN
IF (rst = 0) THEN
stt <= SI ;
ELSIF ( clkEVENT AND clk = 1
AND clkLAST_VALUE = 0 ) THEN
stt <= nxt_st ;
END IF ;
END PROCESS clkd ;
-- the stm process describes the transitions between states
-- and the output signals
stm: PROCESS ( stt, st, zi )
BEGIN
-- default assignments
nxt_st <= stt ;
Dop <= nopD ;
Aop <= nop ;
Qop <= nop ;
Sop <= nop ;
rdy <= 0 ;
-- state transitions and output signals
CASE stt IS
WHEN SI =>
rdy <= 0 ;
Dop <= ldD ;
Aop <= reset ;
Qop <= load ;
Sop <= reset ;
IF ( st = 1 ) THEN nxt_st <= SM ; END IF ;
WHEN SM =>
Aop <= ldAshr ;
Qop <= shrQ ;
Sop <= count ;
IF ( zi = 1 ) THEN nxt_st <= SF ; END IF ;
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Adv. Dig. Design S. 7 August 18, 2003
WHEN OTHERS => --- when SF
rdy <= 1 ;
IF ( st = 0 ) THEN nxt_st <= SI ; END IF ;
END CASE ;
END PROCESS stm ;
op(6) <= Dop ;
op(5 DOWNTO 4) <= Aop ;
op(3 DOWNTO 2) <= Qop ;
op(1 DOWNTO 0) <= Sop ;
END behv ;
The clocked process clkd describes the state D ip-ops of the
control unit.
The ip-ops are asynchronously reset when rst = 0.
The state machine process stm describes combinatorial logic of the
next address (excitation) circuit and the output signals circuit of
the control unit.
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Adv. Dig. Design S. 7 August 18, 2003
After the control unit is compiled and synthesized it is important to
verify its behaviour by simulation. The results of the simulation of the
control unit could be of the form as presented in Figure 76.
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1.Bc
SCHEMATIC1.Bc
SCHEMATIC1
SCHEMATIC1.Bc
SCHEMATIC1.Bc
SCHEMATIC1.Bc
SCHEMATIC1.Bc
Context
rst
clk
st
rdy
zI
nxt_st
stt
op
Dop
Aop
Qop
Sop
Signal
'1'
'1'
'1'
'0'
'0'
1
1
15
'0'
1
1
1
Value
X 0 1 2 0
X 0 1 2 0
X00 6A 15 00 6A
X0 2 1 0 2
X0 2 1 0 2
X0 2 1 0 2
0ns 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns
Figure 76: Simulation waveforms for the control unit
The signal rst resets the state of the control unit to SI.
If the signal st is low, the control unit remains in the state SI until the
rst rising edge of the clock after the signal st goes high when the state
SM is reached.
From the state SM the transition to the state SF is made on the rising
edge when the signal zI from the step counter is asserted.
It is important to verify that the control unit generates correct op-codes
in every state.
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Adv. Dig. Design S. 7 August 18, 2003
7.12 The complete word-serial multiplication processor
Once the datapath and the control unit are synthesized and simulated
the can be connected together to form the complete word-serial
multiplication processor as in Figure 71. Then the processor should
be tested by simulation.
An example of simulation results is presented in Figure 77.
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + +
69 36 10 69
53 00
65 00
0065 D6B2 14D9 E0EC 19F6 0CFB DCFD EE7E 20BF 0000
/rst
/clk
/st
/zI
/rdy
/op(6:0)
/dd(7:0)
/qq(7:0)
/aq(15:0)
0.0 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0
Time(ns)
Figure 77: Simulation waveforms for the word-serial multiplication processor.
Note that 53
H
65
H
= 20BF
H
Note that the processor correctly multiplies two positive numbers. It
should be also tested for negative numbers.
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