TRANSISTOR-LEVEL ANALOG IC DESIGN

Analog Basic Structures

M. Kayal Swiss Federal Institute of Technology (EPFL) Electronics Laboratory 1015 Lausanne- Switzerland E_mail: [email protected]

Integrated Systems

Analog Sensors
Analog Front-end

Mixed/ Mode
Analog Digital Convertor A/D

Digital
Signal Processing

HF-VHF
Communication (RF- Internet)

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Information Technology & Microelectronics

RFID Systems

Low Frequency Low Baud rate

Wireless PDAs Station de base Intranet

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High Frequency High Baud rate

2005_2006

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Analog Basic Structures

2005_2006

Power Management
Coupling Energy and data
Power communication Base station Load Modulation Transducer

ASIC
AS IC

Half-duplex
80 %
Digital
Reader emission modulation (ASK 100%) or (ASK 10%)

Analog

1
RF LINK Contactless card

20%
HOST

RF Reader 13.56 MHz

Area 70 70% %of ofapplications applicationsneeds needsAnalog Analogfunctions functions

2005_2006 M. Kayal-LEG/EPFL 2005_2006

3
M. Kayal-LEG/EPFL

Reader reception demodulation

Analog Basic Structures

Analog Basic Structures

Digital Switching Noise

L Vef f i(t) Vd d
Heat sink Epoxi Chip die

Switching Noise

Die attache pad Bond wire Leadfram e

CL V V CL CL

Inductive loop

Veff = Vdd-L di(t)/dt i(t)= C. d(VCL )/dt = C. Vdd /dt

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Analog Basic Structures

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Analog Basic Structures

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Mixed mode circuits

Power supply voltage

Power Supply

10

Digital circuit Noisy part Power supply Substrate coupling ...

Analogue circuit Sensitive part High impedance

0

Digital

Analog

Digital

Analog

1 0

1 0

Shielding techniques. Increasing the matching and symmetry of analogue part (differential designs).

Technology

Decreasing the switching noise in the digital part

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11

12

Energy, Energy, Energy

I=100A
Telecom. Micro-nano Electronics

HF-VHF

100A
3.3V
Ah 1000 .3V/

Information Technologies

Power Management

Electronics

Vo

RL
Modeling VLSI Signal Processing

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Analog Basic Structures

2005_2006

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Analog Basic Structures

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Electronics systems
Au_S3
S3
R2 T6 T5

13

Steps
Devices Analog Structures
P.D.
+

14

Au_S2
R6 R5

Au_S1=1
+Vcc

S2
iB2
T2

S1

I.C

Functions

systems

i Qo
Cin T10 T9

T1 Re

Iout

Re Vin

R1 i10

R7

i9 i7 iB7
T7 T8

iB4
T4

Vout T3

i8 iB8

A.O

Filtering

IQ1 R10 R9 R8

-V cc

R4

R3

S4
C1

System
Mult.
CCD YOUT S2OUT S1OUT AGND VCC XAGC AGC PHIV4 PHIV3 PHIV1 PHIV2 -9.5V SUB PHIH2 PHIH1 PHIPG +15V 22V

SBX 15 4 7
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

VR HR VI NT COM LA LT 4F SC SC B F BL K C L HD VD SY NC XD L1 XD L2 CL P0 CL P2 CL P3 ID 5V CK IN G N D O S CO 0S CI SH UTT ER F L

INT /E XT 28 AGC M AX 29 CCD 30 AGND 31 YO UT 32 S2 OUT 33 S1 OUT 34 IR ISOU T 35 AGND 36 VCC 37 XAGC 38 AGC 39 GC 40 PH IV4 41 PH IV3 42 PH IV1 43 PH IV2 44 VL 45 GND 46 GND 47 SUB 48 PH IH2 49 PH IH1 50 PH IP G 51 15V 52 22V

27

U1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

SBX1547
27 INT/EXT VR 28 AGCMAX HR 29 CCD VINT 30 AGND COM 31 YOUT LALT 32 S2OUT 4FSC 33 S1OUT SC 34 IRISOUT BF 35 AGND BLK 36 VCC CL 37 XAGC HD 38 AGC VD 39 GC SYNC 40 PHIV4 XDL1 41 PHIV3 XDL2 42 PHIV1 CLP0 43 PHIV2 CLP2 44 VL CLP3 45 GND ID 46 GND 5V 47 SUB CKIN 48 PHIH2 GND 49 PHIH1 OSCO 50 PHIPG 0SCI 51 15V SHUTTER 52 22V FL +5V U10 C20 100n C26 22p

Modulation Demodulation

COM LALT 4FSC BF BLK CL HD VD SYNC XDL1 XDL2 CLP0 CLP2 CLP3 ID +5V

M.C.

+ +

Oscillators Calculator . . . . . .
2005_2006

22V +15V -9.5V C21 1 00n C22 C23 100n 100n

P.P

C25 22p

C24 33p GND

Microcontroleur
+A15V 1 K2 K2 K2 K2 VIDEO 2 BIRIS 3 AGND 4

+
+A15V VCC C19 100 n 7 + 6 5 R12 10K 4 C18 100n VCC R13 22K 8

1 1 U5

2 POT4 2K3 + 2 3

R11 10K

. . .
2005_2006 M. Kayal-LEG/EPFL

. . .
Analog Basic Structures

M. Kayal-LEG/EPFL

Analog Basic Structures

Example-1
Circuit
+

15

Example-2

16

Vin

Rc= 8

R R2 1 C

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Analog Basic Structures

2005_2006

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Analog Basic Structures

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Implementation

17

Contents
Overview of analog electronics MOS transistors: structure and modes of operation, large and small signal models, standard process and layout. Basic analog structures design:
Differential Pair Current Mirror Cascode Stage Analog switch

18

Style: Ex. cathedra With Exercises

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

Transistor

19

Small Signal Model

10

20

Iout
Slope = gm

Variations i(t)

Iout

I out

20 15 10
IC0

Slope = g

I0

10

10
t

Vin (V) 0.2 0.4 0.6 0.8 vin(t)

5 -VA -12 -10 -8 -6 -4 -2 0

VCE0

10

12

Vout (V)

Small signal vbe(t)

iin gmvin vin gin i

iout gout

0.2

0.4

0.6 Vin (V)

10

12

Vout (V)

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Transistor output Behavior

IC Pmax ICmax IB1 IB2 Pmax IB3 Pmax IB4
Pmax IDmax ID Pmax

21

Input Resistance

Output Resistance Transconductance COMMON SOURCE

i2

Voltage Gain

RL

RS

v1
v1 RL v2
R out

RL

v2

R in

Rin =

1 Rout = g

ds

gm Gm = 1+g R ds L Gm0 = gm (RL=0) High COMMON GATE

i2

gmRL Av = - 1+g R ds L gm Av0 = - g (RL=)

ds

High

High

VGS1
RL

RS R out

v1 v1 RL

RL

v2

R in

VGS2 Pmax VGS3 VGS4

gds 1 Rin g + g RL m m

gm 1 Rout g + g RS ds ds

gm+gds Gm = - 1+g R ds L Gm0 = -gm-gds (RL=0)

Av0 =

Low

VCEsat

VCEmax

VCE

VDSmax

VDS

Very High High COMMON DRAIN

i2

(gm+gds)RL Av = 1+g R ds L gm+gds gds (RL=) High

Bipolar

MOS

RL

RS

v1
v1 RL
R out

RL

v2

R in

Rin =

1 Rout = g +g m ds

gm Gm = - 1+(g +g )R m ds L Gm0 = - gm (RL=0) High

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Low

gmRL Av = 1+(g +g )R m ds L gm Av0 = g +g (RL=) m ds Unity

Impedances
1 gbe + .RE RB 1 RB gm + 1 gce R gce 1 gds gm + RD gm RS

23

OTA_1

24

1 gm gds + RS gds RD
T9

VDD

Ro Vout I1 T1 I2 T2 I0 CL

VDD

T3 I1 T1

T4 Vout I2 T2 I0 CL

T9

RE

T8

VSS

T6

T8

VSS

T7

T6

Ao =
M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

gm1,2 2go
2005_2006

Analog Basic Structures

Basic Analog Structures

1 3

25

OTA Specifications
Gain- A0 [dB] Gain Band width product GBW [rad/s] Slew Rate- SR [V/s] Common-mode input range- CMR [V] Common-mode rejection ratio- CMRR [dB] Power-supply rejection ratio-PSRR [dB] Output-voltage swing-Vout [V] Offset- [mV] Noise nv / sqrt (Hz)
Analog Basic Structures 2005_2006

26

4 2

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Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Op Amp.
R1 S1 RP V1 IC1 T1 T2 IC2 R2 S2 T6 IC6 T7 D1 S3 D2 T8 Iq T4 S4 Iq T3 Iq T5 -VCC S2 T6 IC6 T7 D1 S3 D2 T8 Iq Iq I2 RL V2 +V CC I2 RL V2 +VCC

27

Exercice_1
Explain the function of each structure in this OpAmp Topology Where is the negative and the positive input of this op-amp? Propose a solution for setting the gain of this OpAmp to Av= 48 dB. With Rp= 29.3 K, estimate the currant Iq. Find out the expression of the open loop gain. With R1=R2= 1.4 K, RL=2 K, an Early voltage VA= 80V and a current gain =100, calculate the value of the open loop gain.

28

R1 S1 IC1 T1 V1 T2

R2

IC2

-VCC

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Analog Basic Structures

2005_2006

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Analog Basic Structures

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29

1st- Differential input stage

Vcc
R1 R2

2- Common emitter
Vcc
S2 T6

30

v1Gm,S1
IC2

vaGm,S2 v1 Rin,S2 Rout,S2 v2

vd
IC1 T1 V1 T2

v2

v1 Rin,S1 Rout,S1

v2

Iq Iq

Rin,S1 = g
-Vcc R G m,S1 = out,S1

2
-Vcc

1 Rin,S2 = g

be6

be1/2

gm1/2 2
ce2

Gm,S2= gm6 Rout,S2= (1/gce6)// (1/g ce5)

= R2// (1/g ) R2
2005_2006 M. Kayal-LEG/EPFL

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Analog Basic Structures

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31

Output stage Push-Pull

DP Vcc
vbGm,S3
T7 D1 S3 D2 T8 Iq

Overall gain
CE
vaGm,S2 va Rin,S1 Rout,S1 Rin,S2 Rout,S2 vb Rin,S3 Rout,S3

32

PP-CC
vbGm,S3 v2 RL

v1Gm,S1

RL v2
v1

I2

Rin,S3
RL V2

Rout,S3

-Vcc

Rin,S3 = g

v2 v1 =

va v1

vb va

v2 vb

be7/8

+RL R L

G m,S3 - gm7/8
Rout,S3= g
M. Kayal-LEG/EPFL Analog Basic Structures

1
m7/8

(1/gce6)// (1/gce5) 1 gm7/8

2005_2006

v2 vb = -Gm,s3. Rout,s3 //RL 1

M. Kayal-LEG/EPFL

gm1/2 1 va =- Gm,S1. Rout,S1// Rin,S2=. R2// gbe6 v1 2 vb =-Gm,S2 .Rout,S2 // Rin,S3 =-gm6.(1/gce6)//(1/gce5 )//RL va

Analog Basic Structures

2005_2006

MOS Photo
Polysilicon Gate Drain Contact Metal

33

CMOS Transistors
VS G D D G S V+

34

P substrat

n Well

D
Diffusion n+

Wm
G

Polysilicium Metal
Source Contact

Lm

Contact
2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures

S
2005_2006

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Analog Basic Structures

35

Circuits Parameters / Transistors Parameters

Example of circuit level parameters Noise Consumption fT Gain Speed Area ID Dynamic VNoise Linearity W/L Example of transistor level parameters gm gds
S

CMOS-Devices
G D D ID Substrat p G S B B V DS > 0
Source n+ Drain n+

36

VDsat
S
Source p+

D
Drain p+

S G B VSD > 0 ID D

Substrat n

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Device Biasing
V DD VS VG G D pMOST G VG S VS V SS S B ID nMOST D ID B VD VD

37

Strong Inversion
Strong inv.
Blocked

38

VP=

VS et VD VP ID = 0 VS VP VD n ID = 2 (VP-VS) 2 VS et VD VP

Saturation

VG-VT0 n VG < VT0+nVS VD > VS (par dfinition) ID = 0 VG > VT0+nVS VD VP ID = 2n (VG-VT0-nVS) 2 VG > VT0+nVS VD < VP n ID = VDS (VG-VT0-2(VS+VD) )

Linear

n ID = 2 VDS (2VP-VS-VD)

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Analog Basic Structures

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Weak Inversion
Blocked Weak inversion VP - VS <0 , VS >> VP VD >> VP ID = 0 VS > VP, VD > VP VD-VS 4U T V P VS 2 I D 2 n U T exp U T VS > VP , VD > VP VD-VS ~UT VG <VT0+nVS VG <<VT0+nVS VD > VS (defenition) ID = 0 VG <VT0+nVS, VD < VP VD-VS 4 UT VG VT 0 n VS 2 I D = 2 n U T exp n U T VG < VT0+nVS VD-VS de lordre de UT

39

ID= f(VG)- Strong inversion

ID (A) Saturation V S = 0V V S = 1V

40

Saturation

200

150 100

Linear

I D = 2 n U
V U e
S T

2 T

VP U T

I D 2 n U
V D VS U T e UT e

2 T

V G VT n U T

50 V G (V) 0 V T0 1 V T0 +nV S

V D U T

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Analog Basic Structures

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10

ID=f(VDS)
ID (A)

41

Early Effect
ID (A) 300

42

Conduction 200 150 100 50 Saturation V G = 3.4V

(V P = 2.7V)

250 200

Pente = gds

V S = 0V V G = 2.6V V G = 2.0V V G = 1.6V

(V P = 2.1V)

150 100 50

(VP = 1.6V) (V P = 1.3V)

V D (V)

-V A

-15

-10

-5

10

15

V D (V)

VP

10

15 V G = 0.6V
(V P = 0V)

VA = L.Va
2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

Saturation-AC Model
Transistor MOS Cas gnral
g vd vg s vs id
vg s vs b id

43

Strong Inversion AC Model

Dfinition Conduction (VD-VS) gms =n gm et gmd =- gms (VG-VT0-nVS) Intrt: MOSFET en interrupteur, RON = 1/gds Saturation (VP-VS) = 2ID n n (VP-VS) = 2nID =n gm ID VA

44

Schma quivalent petits signaux

d gm vg g id gms vs gds vd

id

ID gm = VG Prepos

gms = -

ID VS Prepos

Cas VS = 0
g vgs

id
g

d gm vgs

id gds vds

ID gds = VDS Prepos

vds id

vgs

id

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Analog Basic Structures

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Analog Basic Structures

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11

Weak Inversion AC Model

Dfinition ID gm = VG Prepos Conduction Saturation
ID n U T

45

MOS Transistor: Strong/Weak Inversion Saturation

D G
VG+VG VS+VS
2

46

IDq+ID

G V G

gm VG -gms Vs gDS V S

D
V D

S B

B
n
2
2 VDsat

ID gms = - P VS repos

ID UT MOSFET as switch, RON = 1/gds

ID =

2n

(VG VT 0 nVS ) =
W L

gm =

ID gds = VDS Prepos

With = k P
VDsat =

& kP = Cox

Strong
g DS =

2 I Dq 2 I Dq = .VDsat = n n.VDsat g mS = n g m

VG VT 0 2 ID VS = ; .n n
VG nVS nUT VT 0

VG > VT 0 + nVS

I D = I D 0e

2 nUT I D 0 2 n UT e VDsat (4.U T ) 100mV

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

Weak
g DS
Analog Basic Structures

I Dq (U = Early Voltage) UA A I g m = Dq n.U T I = Dq (U A = Early Voltage) UA

2005_2006

Hand Calculation Model

Strong inversion Weak inversion

47

Transistor/Tradeoffs- Examples
g m [log] ID nU T
W L

48

DC Param.

ID, VG, VS, VB

Saturation : I D

2n

(VG VT 0 nVS )2

Saturation : I D = I D 0 e
VG nU T

VG nVS nUT VD UT

Triode : I D VG VT 0

n (VS + VD ) (VD Vs ) Triode : I D 0 e 2

.(e

VS UT

e )

Linearity

4U T 100mV
Dynamic

VDsat Small signal param. gm

VG VT 0 n

W/L [log] ID Strong VDsat -200mV -100mV W/L [log] ID 8nU2T Strong
2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures

2 ID n
n.g m

ID nU . T
Maximum

gms gds Speed Capa. fT Therm. Flicker Layout

M. Kayal-LEG/EPFL

T Moderate

2n U 2

Weak

g ds =

I Dq , U A = f ( L) , L Gain UA

Cgs, Cgd, Cgb, Csb, Cdb, Cgsov, Cgdov, Cgbov gm 2 C gs

VSR Noise

Area

1 ) gm 1 f( ) W .L f (W .L) f(
Analog Basic Structures

ID 2nU2T Weak
2005_2006

12

49

Inversion Factor
Inversion Factor Ic is a normalized value that describes the inversion level
IC = ID ID ID I' = = = 2n U T2 2n C W U 2 2nK W U 2 2nK pU T2 ox T p T L L

50

Strong inversion Ic > 10 Weak inversion Ic< 0.1 Moderate Inversion 0.1 Ic 10
gm 1 1 = . I D nU T 1 1 + + IC 2 4
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The Normalized gm/ID Characteristic

The choice of gm/ID ratio translates current into transconductance (gm efficiency and consumption efficiency). It gives an indication of the device operating region (strong, moderate or weak). The greater the gm/ID value, the greater the transconductance we obtain at a constant current value. The normalized gm/ID is almost invariant to process parameters and scaling

51

Circuit Design Tradeoffs

IC Strong
Speed Linearity

52

L (W=Cte,ID=Cte)

gmnUT/ID

0.5

Weak
0.01 0.1 1 10 100 1000

Dynamic

DC Gain Noise

0
0.001 C C. Enz F. Krummenacher and E. A. Vittoz, "An Analitical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications", J. Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, July 1995 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

13

Small Signal AC-Model

Small signal model
CSG

53

Common Source(1/2)
- Static characteristic:
Vout ,max = VDD VDsat = VDD

54

Vin
CGD

CDS

CL

Vin

G CGS

CGD CDS CL gm VG 1/gds

D
Vout

Vout

- DC gain : g AV 0 = m g ds
Rout V = out I out
Vin = 0

Vin VT n

VDD Vin Rout CL Vout

(Vin Vout ) j CGD = g m Vin + Vout g ds + Vout j CL

0 Vout g 1 j CGD / g m = m Vin g ds 1 + j (CL + CGD ) / g ds

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Zero Pole
2005_2006

m~

0 ~I D -1/2

I D

ds ~

ID

Vin ( j CGD g m ) = Vout ( j CGD + j CL + g ds )

- Strong Inversion: 2 .I D 2I D = .VDsat = gm = n n.VDsat - Weak inversion: I gm = D nU . T

M. Kayal-LEG/EPFL

1 U A U a .L (U A U a .L with U a [V / m ]) = = = g ds I D ID
(log)
~ ID gm
1/ 2

IC (log)
2005_2006

Analog Basic Structures

Common Source (2/2)

Small signal model Vin Rout CL
V G G CGS CGD gm VG

55

Transistor Design
Electrical Behaviour:
GBW = 2fT 2. .10Mhz A0 60 dB SR 106 V/s CL= 1pF Power Budget 330 W Power supply = 3.3V Early Voltage, Ua= 11V/ m Kp= 39.6 A/V2 n = 1.4 VT0 = 0.57 V
Analog Basic Structures 2005_2006

56

ZL Vout
g ds CL

Vout
H j [dB] A0

S
P 1

Vout g 1 j CGD / g m = m Vin g ds 1 + j (CL + CGD ) / g ds

gm gm = .U a .L g ds I D gm gm I D GBW = = . C L I D CL ID SR = CL A0 =
M. Kayal-LEG/EPFL

Technology Data:
GBW= gm/(CL)

GBW g m = SR ID
Analog Basic Structures

Z1= gm/(CGD)
2005_2006

M. Kayal-LEG/EPFL

14

Design strategy-1
SR & CL ID fT, CL gm A0, gm gds gds,Ua L W & Techno?
I D = SR. CL > 1 A g m fT 2 CL 63 s

57

Main Questions
IC = ID ID ID I' = = = 2 2 W 2 W 2n U T 2n Cox U T 2nK p U T2 2nK pU T L L

58

g ds =
L=

gm 63 ns A0

gm 1 1 = 27.5( n = 1.4) . I D nU T 1 1 + + IC 2 4

ID =1.44 m U a g ds

In Strong Inversion In Weak Inversion

Av =

2.L
(1 ) Ua

2.K p L 2. 2 = Ua n.I D n.W .I D

Av =

Ua L
2.nU . T
2005_2006

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Analog Basic Structures

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Analog Basic Structures

Structured Transistor Sizing

fT = gm 2 CL
gm gm = .U A g ds I D
fT & C L g m

59

Design strategy
fT, CL gm ID (cond Ic=1) A0, gm gds gds,Ua L
g m fT 2 CL 63 s
ID gm/17 ID 3.7 A
SR = ID = 3.7 V / s CL

60

A0 =

A0 & U a & g m I D

g ds =
L=

gm 63 ns A0

gm 1 1 = . I D nU T 1 1 + + IC 2 4 ID ID ID I' = = = IC = 2n UT2 2n C W U 2 2nK W U 2 2nK pUT2 ox T p T L L

M. Kayal-LEG/EPFL Analog Basic Structures

W L

ID > 5.3 m U a g ds

IC W

IC =

ID L.I D =1W > = 261 m 2 W 2 2 nK pU T 2nK p U T L

2005_2006

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15

Matching of devices
1. 2. 3. 4. 5. 6. 7. 8. Same structure Same temperature Same shape and size Minimum distance Common centroid geometries Same orientation Same surroundings Non minimum size
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61

62

Current Mirrors

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Resistive Biasing
V DD R1 Iout

63

Current Mirrors Advantages

Current mirrors are less sensitive to thermal drift and power supply voltage. For low current, the area is less than resistive biasing technique. Well controlled power consumption

64

Strong inversion saturation

I out =

2n

(VG VT 0 ) 2

VG

R2 VSS

VG = VDD

R2 R1 + R2

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16

Biasing_1
V DD Iout

65

Biasing_2
Strong inversion saturation VDD- VG
Iout Mb
V DD Iout

66

Strong inversion saturation

Iout
R1

I out =
2nI out

2n

(VG VT 0 )

I out =

2n

(VG VT 0,n ) 2

VG
VSS

VG =

+ VT 0 =

2 LnI out + VT 0 K pW

VG
VSS

VG =

2nI out

+ VT 0,n

R1 =
M. Kayal-LEG/EPFL Analog Basic Structures

VDD VG I out
2005_2006 M. Kayal-LEG/EPFL

VDD VG = VG , Mb =
Analog Basic Structures

2nI out

Mb

+ VT 0, p

2005_2006

Current Mirror
Iout Iout VDD

67

Multiple Current Mirror

VDD

68

Strong inversion saturation

I out =

2n

(VG VT 0,n ) 2

I1 T1 VG

Ii Ti

Tn Same bulk

VSS

Matching Rules

VS

Ii/I1 = i/1. Same surroundings

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

With = k P

W L

& k P = Cox

Analog Basic Structures

2005_2006

17

Diode Connected Transistor

I1 VDS I1
VG

69

Dynamic Behavior
VDD I2= K.Iref Iref
CD1 CG1 d L CG2

70

Small signal model

G C gm Vg

D
1/gds V

ds

T1 C

T2
W1 K.W1

DC
Strong Inv. VDS = VGS = 2 n I1

+ VT 0 =

2 L n I1 + VT 0 W .K P

AC

Weak Inv. VGS = VT 0 + nU T .ln( I c )

With I c < 0.1
M. Kayal-LEG/EPFL

VDS 1 1 1 R= // = g m g ds g m I1
2005_2006

COX 3.4 fF/m2 - tech : 0.5 m 8.5 fF/m2 - tech : 0.18 m Cj 0.74 fF/m2

<0
Analog Basic Structures M. Kayal-LEG/EPFL

C = CG1+ CG2 + CD1 CG= W.L.Cox in strong inv. CG= W.L.Cox.(1-1/n) in weak inv. CD= CJ.W.d
2005_2006

Analog Basic Structures

Small Signal Model

VDD I2= K.Iref Iref T1 C
g

71

Frequency Response
p =

72

T1
1/gm1

T2
d2
gm2 Vg
1/gds V ds

Weak inversion I ref I ref 1 1 . . nU T W [(1 + K ) L.C (1 1 ) + dC )] nU T W L.C (1 + K )(1 1 ) Xj ox ox 1 1 n n

With I ref 0.1*2 n U T2

1 L .(1 + K )(1 ) n Strong inversion
2

T2

Vg

0.2 U T

i2 =

i1 1+ j

fp =

g m1 2 C
2005_2006

p
M. Kayal-LEG/EPFL

VDS 2 sat
L2 (1 + K )
Analog Basic Structures 2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

18

DC Example- Techno :0.5m

With, W=10 m L=2m L=5m L=20m
ID2
VDD
12uA

73

AC Example- Techno :0.5m

With, W=10 m L=2m L=5m L=20m
[dB]
4

74

VDD
0

Vin
Iref= 10A T1 T2

10uA 8uA 6uA 4uA 2uA Vin 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V

Iref= 10A T1 T2

-4 -8

f
-12
1MHz 10MHz 100MHz

VDsat= 280mV Rout= 3.5 M

M. Kayal-LEG/EPFL

VDsat= 320mV Rout= 19 M

Analog Basic Structures

VDsat= 550mV Rout= 140 M

2005_2006

fp= 157MHz
M. Kayal-LEG/EPFL

fp= 45 MHz
Analog Basic Structures

fp= 6 MHz
2005_2006

Current Mirrors: Trade off

IC
VDD Iref= 10A T1 T2

75

Mismatch Error
Random error can be characterized by the standard deviation, for instance:
Resistance : R= (R/R) Capacitance: R= (C/C) Bipolar transistor: S= (IS/IS) & (/) MOS Device: T= (VT0/VT0) & (/)

76

Strong

Speed Accuracy Noise

Weak

Dynamic

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

19

Mismatch Effect on Current

ID = 2n (VG-VT0) 2
I D =

77

Standard Deviation
(
g I D 2 + ( m T )2 ) = ID ID

78

I D I D 1 + (VG VT 0 ) = (VG VT 0 ) 2 g m VT 0 (VG VT 0 ) 2n

I D g m = V ID ID T 0

= (/) & T = (VT0)

Techno:

A= W.L et AT= T W.L

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Example
With = 2% and T = 5mV
(
g I D 2 ) = + ( m T )2 ID ID

79

Exercice
Design of the following current mirror with :
VDsat2 300 mV Rout 500K
VDD

80

Example (with nUT = 40mV):

ID ( ) ID

[%]

T nUT

= 2% T = 5mV

Iref= 10A T1
IC

I2= 40 A

10 5 2 0 0.01 0.1

T2

10

100

With KP= 169 A/V2 n= 1.4 VT0= 0.61 V Ua= 11V/m VDD= 3.3 A=0.025m AT=12.3 mV/m

Bad precision of currents in weak inv.

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

20

Solution-1
Rout 500 K
Rout =

81

Standard Deviation
(
g I D 2 ) = + ( m T )2 ID ID

82

LU . a R .I 1 = 500k L out D = 1.8 m ( L = 2 m) g DS ID Ua

W1 I D1 10 = = 3.1 2 2*1.4*169*10*(26.103 ) 2 L 2nK p I CU T

gm 1 1 1 1 . . = = = 7.4 V 1 I nU T 1 nU T 1 1 1 + + IC + + 10 2 4 2 4

2 A g AT 2 I D +( m )= ) = 1.3% ID W .L I D W .L

Rout =
L

L.U a 1 = 500k g DS ID
W1 3.1* L = 6.2 m
2005_2006

Rout .I D = 1.8 m ( L = 2 m) Ua

gm 1 1 . = I D nU T 1 1 + + IC 2 4
M. Kayal-LEG/EPFL

IC =

ID W 2 2nK p 2 U T L
2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

Analog Basic Structures

Solution-2
Rout 500 K
Rout =

83

AC Transistor Impedances

84

LU . a R .I 1 = 500k L out D = 1.8 m ( L = 2 m) g DS ID Ua

IC =

W1 312.6 W1=625m, W2=2500m L

gm/ID 1/nUT =27.5 V-1
M. Kayal-LEG/EPFL

I D1,2 0.1 W 2 2nK p 1,2 U T L

1 gm gds + RS gds RS RD

VDsat 4* UT 100mv
2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

Analog Basic Structures

21

Source-Degenerated Current Mirrors

VDD Vout Iref T1 Iout T2

85

Output Impedance
Rout = /Vin=0 avec Vin=Vg+Vs=0 on -Vg = Vs = -IoutRs

86

Iout gm2 Vg 1/gm1 Vin RS Iout RS Vg Iout Vs RS Rout gds2 Vout

Iout= gm2Vg + gds2(Vout-Vs) = -gm2IoutRs+ gds2(Vout-IoutRs) Iout= -gm2IoutRs + gds2Vout -IoutRs gds2

Vin

Rs VSS

Rs

Rout =

Vout 1+Rs(gm2 + gds2) = gds2 Iout

Rout
M. Kayal-LEG/EPFL

Rs g m 2 g ds 2
2005_2006 M. Kayal-LEG/EPFL

Rout

1+Rsgm2 Rsgm2 gds2 gds2

Analog Basic Structures 2005_2006

Analog Basic Structures

Cascode Mirror

87

Stacked Mirror
VDD

88

In strong inversion with Iref= Iout:

Iout T2 VG Vout

Vb
TD

Iout VGS

Iout T2 Vout
T 1 Vb-VGS

Iref

Rout

1 gm2 g ds1 g ds 2

VD1 = VG = With VD1, sat =

2.n.I out

TD2 VG Vb TD1 VG

+ VT 0 > VD1, sat

T1

2.I out VG VT 0 = n n.

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

22

Example
VDD

89

Solution
Ic 15 (strong inversion)
VDD

90

40 TD2

40 T2 Vout

With KP= 169 A/V2 n= 1.4 VT0= 0.61 V Ua= 11V/m VDD= 5 W/L= 8/1

40 TD2

40 T2 Vout

gm 1 1 = = 6.2 . I D nU T 1 1 + + IC 2 4 g m1 = g m 2 = g m = 40* 4.5 = 248 A / V g ds1 = g ds 2 = g ds = Rout = VD1 = I D 40.106 1 = = 3.6 1 ( 278k ) Ua g ds 11

g m1 = 19.1 M 2 g ds 2.n.I D + VT 0 0.9V K p *W / L 2.I D = 205mV nK p *W / L

TD1

T1

TD1

T1

Calculer, Rout et Vout,min?

VDS , sat 2 =

Vout ,min = VD1 + VDS ,sat 2 1.1V

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

Low Voltage Cascode Mirrors-1

Goal: Bias VD2 at the edge of its saturation voltage and indep. of absolute values
VDD Ib = Iref T4 Vb T1 Iout = Iref T3

91

92

Low Voltage Cascode Mirrors in Strong inv.

VP 2 =
VDD Ib = Iref T4 Vb Iout = Iref T3 W/L

2.n.I ref K p *W / L

I D3 =

n
2
2 I ref

(VP 3 VD 2 ) 2

Iref

T1 & T2 T3 T4 & Ib

Current Mirror Cascode stage Cascode biasing

Iref

VP3=VP4 Same VG & VD2=VP2

Vout
VP 3 VD 2 =

T2

Vout

W/4L
T1 T2

3n

2 I ref

4n

2 I ref

2n

2 I ref

3n

Vp2

W/L

W/L

With 1= 2= 3=4 4, VP2 = VP3/2

Vb = 2 2.n.L.I ref K p .W + VT 0
2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

23

93

94

Low Voltage Cascode Mirrors in Weak inv.

I D = 2n U . e
2 T VG VT 0 nUT

Low Voltage Cascode Mirrors in Weak inv.

VD UT

VDD Ib = Iref T4 Vb Iout = Iref T3

(e

VS UT

e
VD 2 UT

)
VDD

I D = 2n UT2 . e
2n 3U T2 . e
Iout = Iref T3
VG VT 0 nUT VD 2

VG VT 0 nUT

VS

VD

( e UT e UT )
VG VT 0 nUT VR

Iref

I ref 2n3UT2 . e
2 T

VG VT 0 nUT

(e UT e

4UT UT

) = 2n 4UT2 . e

(e UT e

(VR +VDS 4 ) UT

(e

)
T4

Ib = Iref Vb

W/L

W/55L
T1 T2

I ref 2n 4U . e
Vout

VG VT 0 nUT

(e

VG UT

Iref

3e U = 4 e U
T

VD 2

VR
T

VD2 = UT ln(3/4) 4UT

T1

W/L

W/L

VR

T2

Vout

VD2 = VR+ UT ln(3/4)

3/4= eVD2/UT e4 55
Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

M. Kayal-LEG/EPFL

95

Low Voltage Cascode Mirrors in Weak inv.

VD2 = VR+ UT ln(3/4)
VDD Iout = Iref T3

Low Voltage Cascode Mirrors

VDD

96

I ref =
Iout = Iref T3

3n
2

(VP 3 VP 2 ) 2 =

2n
2

(VP 2 ) 2

With '1=3 & 1=2

VR= UT ln(1 +25/6)

Iref

Iref T5

Iref T4

VD2 = UT ln[3/4 (1 +25/6)]

Vb

I X ref T 1

VP 3 = VP' 1 = VP1,2 (1 +
With '1=2 1 (1)

1 ) 1'
1

Vb T1

8W/L
2Iref

W/L
VR

8W/L
T2 Vout

VD2 = UT ln[8 (1 +16)] 5 UT

T2 T1

Vout

VP 3 = VP' 1 = VP1 (1 +
Vb = nVP1 (1 + 1

W/L
T6

8W/L

8W/L

VD3 10 UT
Analog Basic Structures 2005_2006

) + VT 0 + Vm arg e
2005_2006

Design with additional margin accounting for process uncertainties

M. Kayal-LEG/EPFL M. Kayal-LEG/EPFL Analog Basic Structures

24

97

Low Voltage Cascode Mirrors Dimensions

VDD
VDD

Example
50uA 40uA 30uA

98

=2

Ib = Iref Iout = Iref I X ref T T 1 W/L 3 W/L W T4 (1++)2L Vb Vout T2 T1 W/2L

Choose
M. Kayal-LEG/EPFL

W T4 (1+ ) L

Ib = Iref Iout = Iref I X ref T T 1 W/L 3 W/L Vb T1 W/ L W/ T2 L Vout

2.0V

2.5V

3.0V

W/2L

to add Vm arg e 100mV

Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

W/L = 10/0.5 =1 VD3,min 350 mV Rout 2.5 M fp 1 GHz

Analog Basic Structures

W/L = 10/0.5 =2 VD3,min 450 mV Rout 56 M fp = 370 MHz

2005_2006

Low Voltage Cascode Mirrors-Level shifter

VDD Iref T5 Vb T3
T4 VDD

99

100

Iout = Iref

Iref

T5 Vb T3

Iout = Iref

T4

Differential Pair
Vout

T2 T1

Vout
T1 T6

T2

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

25

Differential Pair

101

Static Characteristics
Weak inversion
Iod/I0 1 Vid/(nUT)

102

T1

I1 Vid

I2 T2

T1

I1

I2 T2 Vid

-4

-2

Min. lin. input range Min. sat. voltage Max gmd gmd lin. with I0

-1

Strong inversion I /I
Vi2

od 0

I0 gmd= 2nU T
Vid/Vidsat

Vi1 I0

Vi2 Vi1 I0

-1

-1

g md =
I C is the inversion factor

I0
n
2005_2006

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

Vidsat =

2nI 0

= 2nU T I C

Analog Basic Structures

103

104

Inversion Excursion

Inversion Excursion

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

26

DC-Offset_1

105

DC-Offset_2

106

T1

I1 = I2 T2

T1

I1

I2 T2

Ideal diff. Pair

I0
Vin

Mismatch effect on diff. Pair

I0
Vin

= (/) & T = (VT0)

Techno:
M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

A= W.L et AT= T W.L

Analog Basic Structures 2005_2006

DC-Offset_3

107

Common Mode Effect

gm1 T1 I1 V DD I2

108

i1
gm2 T2

i2 d 1,2 gm2vg g02 s 1,2 R0 vg v ic

gm1vg g01
V ic

gm

T1

I1

I2 T2

R0 I0

Voff
I0
Vin

Mismatch effect modeling

vg

vic & i1 i2 = g m vg 2 g m R0 vic i i g 1 Therefore 1 2 = m . 2 g m R0 vic g m 2 R0

i1 i2 = g m .

VG = VT 0
M. Kayal-LEG/EPFL

Offset is minimum when gm is maximum -> weak inv.

Analog Basic Structures 2005_2006

I D gm

(VG ) = T2 + (

ID )2 gm

g m I D n ID = nU T gm ID n g m 1 I D n 2 I D In strong inv. g m = = ( + ) n gm 2 I D n In weak inv. g m =

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

27

OTA_1

109

OTA_1-Improoved Mismatch

110

VDD

Ro Vout I1 T1 I2 T2 I0 CL

VDD

T3 I1 T1

T4 Vout I2 T2 I0 CL

VDD

T3 T4 T4 Vout CL

T9

T9

I1 T1

I2 T2

T9

T8

VSS

T6

T8

VSS

T7

T6

I0

T8

VS S

T7

T6

Ao =
M. Kayal-LEG/EPFL

gm1,2 2go
2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

Analog Basic Structures

OTA_2
V+ T3 i1 I0 T1 Vin+ T4 Vout

111

DC Example- Simple Mirror

With, W=10 m
ID2
VDD
12uA

112

L=5m

C L i1 Vid I0 T6 T 5
Analog Basic Structures

Vin
Iref= 10A T1 T2

10uA 8uA 6uA

i2

T2 Vin-

4uA 2uA Vin

Ao =

gm1,2 2go

0V

0.5V

1.0V

1.5V

2.0V

2.5V

3.0V

g0=gds2+gds4
M. Kayal-LEG/EPFL 2005_2006 M. Kayal-LEG/EPFL

VDsat= 320mV Rout= 19 M fp= 45 MHz

Analog Basic Structures 2005_2006

28

Example- Cascode Mirror

50uA 40uA 30uA

113

Telescopic OTA_2
V+ T3 T4 Vout

114

VDD Ib = Iref Iout = Iref I X ref T T 1 W/L 3 W/L Vb T1 W/ L W/ T2 L Vout

VB1
C L

W T4 (1+ ) L

I0
2.0V 2.5V 3.0V

Vin+

Vid I0

VB2 Vin-

W/L = 10/2 VD3,min 450 mV Rout 56 M fp = 370 MHz

Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

Ao = g0

gm1,2 2go

T6

T 5
Analog Basic Structures

M. Kayal-LEG/EPFL

2005_2006

Folded OTA
V+ I0 I0 Vin+ I0 /2 T1 Vid I0 T6
M. Kayal-LEG/EPFL

115

Folded OTA
V+

116

I0 I0 /2 T2 VinI0 /2 I0 /2 T4 Vout
2005_2006

I0 C L I0 Vin+ i1 T1 Vid I0 T6
M. Kayal-LEG/EPFL

I0 i2 T2 C L i1 Vini2

T 5
Analog Basic Structures

T3

T 5
Analog Basic Structures

T3

T4 Vout
2005_2006

29

Folded / Cascoded OTA

V+

117

Folded / Cascoded OTA

V+

118

I0 T1 Vin+ Vid I0 T6
M. Kayal-LEG/EPFL

VB1
T2 VinT4 Vout
2005_2006

C L

I0 T1 Vin+ Vid I0 T6
M. Kayal-LEG/EPFL

VB1
T2 VinT4 Vout

VB2
C L

T 5
Analog Basic Structures

T3

T 5
Analog Basic Structures

T3

2005_2006

Class A Structures
VDD
VDD
M3 M4 Vin+ VinM2

119

Basic Analog Structures

1

120

VDD
M10 M9

Iss1
M1

Iss1
Bias3 M7 M2 M1 M8

VOUT

M8 M7

Vin+
Vout

3
Vout

M1

VinM5 Bias2 M3 Bias1 M6 M4

M2
M5

I ss1

M6 M3 M4

4 2

Limited gain Low swing

Boosted gain Low swing

Boosted gain Large output swing

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

30

OTA Basic Structure: Input and Output Swing

VDD
M3 M4

121

OTA Basic Structure: Voltage Gain (1/2)

Small Signal Voltage Gain: gm2 g L Av = g m 2 .Ro,OTA = = m2 gds 2 + gds 4 I D 2 ( 1 + 1 - Strong Inversion: .I ss1 I gm2 = = 2 .VDsat ,2 = ss1 n n.VDsat - Weak inversion: I g m 2 = ss1 2.n.U T
2

122

VDD
)
M3 M4

VSGp
Max M4 Vout = V Vdsat DD

Ua2

U a4

Vout CL + Vin M1 M2

VOUT

VCM VGSn VSAT

+ Vin -

M1

M2

I ss1

g ds =
Output
2005_2006

I ss1 , U A U a .L, U a [V / m ] 2.U A

1 2.L = g ds 2 + g ds 4 I SS 1 ( 1 + 1 ) U a2 Ua4

Iss1

Input
M. Kayal-LEG/EPFL Analog Basic Structures

Ro ,OTA =

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

OTA Basic Structure: DC Voltage Gain (2/2)

- Strong Inversion:

123

OTA Basic Structure Example:Open Loop Gain

Techno.: 0.35m. W/L de M1,M2 -> 50/1 W/L de M3,M4 -> 5/1 1- Small signal gain simulated as a function of Iss1 (W/L constant) 2- Small signal gain simulated as a function of channel length (Iss1= constant, W/L constant)
M. Kayal-LEG/EPFL Analog Basic Structures

124

VDD
2. 2 n.I ss1
M3 M4

VDD
M3 M4

Av = Av =

2.L
(1 + 1 ) U a2 U a4

2.L
(1 + 1 ).n.VDsat 2 U a4 U a2

Vout CL + Vin M1 M2

Vout CL + Vin M1 M2

- Weak inversion:

Av =

L
+ 1 )2.nU (1 . T U a2 U a4

Iss1

Iss1

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

2005_2006

31

DC Voltage Gain versus Tail Current

Simulation Results
Strong inversion Weak inversion
200

125

DC Voltage Gain versus Channel Length - Simulation Results

200

126

W/L constant

gm1 I

gm1 I
L= 2m L= 1.5m

Av =
150

. + 1 ) nVsat Analytical estimation (1 U a2 U a4

2.L

W/L constant Iss1=170uA

Gain [V/V]

Area !!!

L= 1m L= 0.75m

Gain [V/V]

100 90 80 70 60 50 40 30

100

L= 0.5m

50

Simulation
L= 0.35m
0

20
M. Kayal-LEG/EPFL

50

100

150

200

250

300

Iss1 [ A]
2005_2006 M. Kayal-LEG/EPFL

0.5

1.0

1.5

2.0

L [ m]
Analog Basic Structures 2005_2006

Analog Basic Structures

OTA Basic Structure: Band Width and Slew Rate

g Gain Band Width,GBW m1 CL g m3 B C C parasitic 4 gs C gs 3 1 + + C gs3 C gs 3 g g I .V .V P2 m3 = m3 . D3 = 3 Dsat 3 = n Dsat 3 3C gs3 I D3 3C gs 3 3.Cox .W3 .L 3.L2 P2
Phase Margin >70 degree P2 > 3 GBW , gm3 > GBWmax <
M3

127

OTA Basic Structure: Bode Plot

H j [dB]
A0 = gm2 g ds 2 + g ds 4

128

VDD
M4

P 1=

gds 2 + gds 4 CL
g m3 3C gs3

Vout CL
9C gs 3 .g m1 CL

P2

n .VDsat 3
9.L2

+ Vin -

M1

M2

g GBW m1 CL Phase(H(j )) [degree]

-45o -90o -135o -180o

SlewRate : SR = I ss1 CL
Analog Basic Structures

Iss1

M. Kayal-LEG/EPFL

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

32

Linearized CMOS Diff. Pair

129

Simple Analog Switch-1/2

D G G VD S VS B

130

T1

I1 T1 T2

I2

T2

VG

D Ron

Vi1 I0/2 I0/2

Vi2

n I D = (VD VS )[VG VT 0 (VD + VS )] 2

1 dU = Ron = gn dI =
`VS VD

n [VG VT 0

L = nn n (VD + VS )] W .K P [VG VT 0 n (VD + VS )] 2 2

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Simple Analog Switch-2/2

n [V + VT 0 n ]
gn

131

Analog Switch-1/2
On VS Off A B A VF=VS B A VF VB Off On V+

132

VS = VD 0 V+-VT0 nn

n Strong inv. (conduction): I D = (VD VS )[VG VT 0 (VD + VS )] 2

g n = n [VB VT 0
2005_2006 M. Kayal-LEG/EPFL

nn (VD + VS )] = n (VB VT 0 nnVF ) 2

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

Analog Basic Structures

33

Analog Switch - 2/2

gon

133

Same Structure
Les composants apparis doivent prsenter la mme structure de base et utiliser les mmes couches technologiques afin de garantir des caractristiques identiques.

134

n (V + VT 0 n )
gn
gn +g p

VG>VGcrit VG<VGcrit gp VS = VD= VF

V + VT 0 p np trou de conduction

V + VT 0 n V+ nn

VG ,crit VT 0 n nn
VBcrit
M. Kayal-LEG/EPFL

= VG ,crit

VG ,crit VT 0 p np
Paire de rsistances (mme couche )

2V = = T 0 With Tp = Tn n p + nn n p nn 2n
Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

nnVT 0 p + n pVT 0 n

Same Temperature

135

Same shape and size

R1 R3 R4 R2 R1 R2 R1 R3 R4

136

G1 S G2

T1

D1 Source de chaleur

Chacune de ces rsistances comporte 10 carrs, Seules R1 et R2 sont convenablement apparies.

T2

D2
I 2I

isotherme
I I 2I

Les 3 transistors de cette source de courant sont identiques

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

34

Minimum Distance

137

Same Orientation

138

D1

D2 G1

T1

D1

G1

T1

T2

G2 G2

S D2

T2

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Same surroundings

139

Common Centrod Geometries

140

R1 R2 Rd
1/2 T1 D2

Rd

R1

R2

Rd
G1

D1

D2

D1

1/2 T2

T1

T2

G2 1/2 T1 1/2 T2

I1

I2 = I3

I4
S

G1

G2

transistors suppl mentaires inutilis s

M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006

35

Hall sensor analog front-end for current measurement

141

142

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

143

144

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

36

Non minimum size(1)

Large devices match better!!!!

145

Non Minimum Size(2)

( x)
1 W .L

146

True stochastic mismatch is caused by random fluctuations of devices properties (doping, charges, grains, etc). These average out when the active areas of the matched components are enlarged.

W- W 2 moyennes

dispositif 1 L 2

idal

dispositif 2

W+ W 2 moyennes

(W )

1 L

L-

L+ L 2

(L)

1 W

(W .L) = (
M. Kayal-LEG/EPFL Analog Basic Structures 2005_2006 M. Kayal-LEG/EPFL

W 1 1 1 1 1 1 ) W +L = + = + L W 2 L L2W WL WL W L
Analog Basic Structures 2005_2006

Mismatch Effect
ID = 2n (VG-VT0) 2
I D =

147

Standard Deviation
(
g I D 2 ) = + ( m T )2 ID ID

148

(VG ) = T2 + (

I D I D 1 (VG VT 0 ) 2 g m VT 0 + (VG VT 0 ) = 2n (VG VT 0 )

ID )2 gm

I D g m = V ID ID T 0
VG = VT 0
M. Kayal-LEG/EPFL

= (/) & T = (VT0)

Techno:

I D gm
2005_2006

A= W.L et AT= T W.L

Analog Basic Structures

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

37

Example
With = 2% and T = 5mV
ID ( ) ID

149

Big Ratio
Series

150

I1
[%] T nU T Exemple (avec nU T = 40mV): ( V G ) [mV] = 2% T = 5mV 10

T14 T13 T12 T11

W/4L 4W/L

I2

Same transistors I2/I1 = 4/0.25 = 16

Parallel

10

5 5 2 IC IC 0 0 0.01 0.1 1 10 100 0.01 0.1 1 10 100 Faible tension d'offset Mauvaise pr cision des en faible inversion courants en faible inversion

T21
Same W/L

T22 T23 T24

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

M. Kayal-LEG/EPFL

Analog Basic Structures

2005_2006

Non Minimum Size(2)

(xs )
1 W .L

151

W- W 2 moyennes

dispositif 1 L 2

idal

dispositif 2

W+ W 2 moyennes

(W )

1 L

L-

L+ L 2

(L)

1 W

(W .L) = (
M. Kayal-LEG/EPFL

W 1 1 1 1 1 1 ) W +L = + = + L W 2 L L2W WL WL W L
Analog Basic Structures 2005_2006

38