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SPI DSP Communication

The document configures several GPIO pins for use as SPI functional pins by enabling their internal pull-ups, selecting asynchronous qualification, and configuring them in the GPIO multiplexer registers to match the SPI signal names like SPISIMOA, SPISOMIA, SPICLKA, and SPISTEA. It performs these configurations for GPIO pins 16-19 and 54-57.

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95 views1 page

SPI DSP Communication

The document configures several GPIO pins for use as SPI functional pins by enabling their internal pull-ups, selecting asynchronous qualification, and configuring them in the GPIO multiplexer registers to match the SPI signal names like SPISIMOA, SPISOMIA, SPICLKA, and SPISTEA. It performs these configurations for GPIO pins 16-19 and 54-57.

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ramu497
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Enable internal pull-up for the selected pins */ // Pull-ups can be enabled or disabled by the user.

// This will enable the pullups for the specified pins. // Comment out other unwanted lines. GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // // // // GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO16 (SPISIMOA) // Enable pull-up on GPIO17 (SPISOMIA) // Enable pull-up on GPIO18 (SPICLKA) // Enable pull-up on GPIO19 (SPISTEA) // Enable pull-up on GPIO54 (SPISIMOA) // Enable pull-up on GPIO55 (SPISOMIA) // Enable pull-up on GPIO56 (SPICLKA) // Enable pull-up on GPIO57 (SPISTEA)

/* Set qualification for selected pins to asynch only */ // This will select asynch (no qualification) for the selected pins. // Comment out other unwanted lines. GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) // // // // GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)

/* Configure SPI-A pins using GPIO regs*/ // This specifies which of the possible GPIO pins will be SPI functional pins. // Comment out other unwanted lines. GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA // // // // } GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA EDIS;

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