Advanced Digital Design

Lecture 11: HW Datapath Components

HW Components for Fully Dedicated Architecture

Adder Multiplier Barrel Shifter Register File

These blocks occur frequently in digital system design. They often limit the speed of the system. Many architectures have been proposed for their high speed implementation at the cost of large silicon area

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Adders

Adders

Pipelined Time Shared Architecture

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Adders

Used in addition, subtraction, multiplication and division Speed of a signal processing or communication system ASIC depends heavily on these functional units

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Half Adder
Truth Table x 0 0 1 1 y 0 1 0 1 C 0 0 0 1 S 0 1 1 0 Logic Equations C = x y S = x y Schematic X Y
A B
XOR 2

Y B XAND 2

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

module HALF_ADDER(ai, bi, si, cout); input ai; input bi; output si; output cout; assign si = ai^bi; assign cout = ai & bi; endmodule
ai

Half Adder in Verilog

C i =a ib i Si =ai b i

Si

bi

cOut

HALF ADDER

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Half Adder using Data Flow modeling

module HALF_ADDER(ai, bi, si, cout); input ai, bi; output si, cout;

// data flow modeling assign {cout,si} = ai + bi; endmodule

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Full Adder
Truth Table x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Full Adder
Cin Half Adder ai Half Adder bi
SiHA1 cOutHA1 cOutHA2 cOut Si

ci = (ai bi )ci1 + ai bi

si = ai bi ci
Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Full Adder: Other implementations

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Full Adder: Implementation in Verilog

module FULL_ADDER(ai,bi,cin,si,cout); input ai,bi; input cin; output si,cout; wire SiHA1,CoutHA1,CoutHA2; HALF_ADDER HA1(ai,bi,SiHA1,CoutHA1); // instance HA1 HALF_ADDER HA2(SiHA1,cin,si,Cout); //instance HA2 Or (cout,CoutHA1,CoutHA2); // using or gate primitive endmodule
Cin Half Adder ai Half Adder bi
SiHA1 cOutHA1 cOutHA2 cOut

Si

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Full Adder Using Data Flow Modeling

module FULL_ADDER(ai,bi,cin,si,cout); input ai,bi; input cin; output si,cout;

// through data flow level of abstraction assign {cout,si} = ai + bi + cin; endmodule

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Ripple Carry Adder

a[5] b[5] a[4] b[4] a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0]

cout FA

C4

FA C S

C3

FA C S

C2

FA C S

C1

FA C S

C0

FA C S cin

C
c5

c4

c3

c2

c1

c0

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

Shortcut to VERIWELL.lnk

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

RCA: Dataflow modeling

Six bit ripple carry adder through data flow modeling // SIX BIT FULL ADDER ; module fulladder_6bit(s,cout,a,b,cin); output cout; output [5:0] s; input [5:0] a,b; input cin; reg [5:0] s,c; reg cout; always@(a or b or cin) begin {c[0],s[0]}= a[0] + b[0] + cin; for(i=1; i<6; i=i+1) {c[i],s[i]}= a[i] + b[i] + c[i-1]; // through data flow modeling. cout = c[5]; end endmodule
Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Ripple Carry Adder

Implements the conventional way of adding two numbers It is the slowest adder Takes minimum area Used where minimum hardware is required and speed is not critical N-bit full adders are required to add two N-bit operands Speed is linear with word length O(N)
Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Principle

Operands are added bit-wise starting from LSB to MSB, adding at each stage the carry from the previous stage The carry out from the FA at stage i goes into the FA at stage i+1 Hence the carry ripples from the LSB to MSB ci,si ai+ bi + ci-1

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Drawbacks!

Delay of full adder at each stage Carry ripples through the entire adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

How can we make it run faster? How can we make it slower?

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Pipelining and Resource Sharing

Registers

Registers can be expensive (1/3 of a simple adder) pipeline only when needed Registers load clock distribution

be aware of clock skews

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Pipelining

Simple to implement Does not work for recursive algorithms. e.g. IIR-filter, adaptive computation

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Pipelining
Before Pipelining
I/P O/P

Combinational Cloud

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Pipelining
I/P O/P

After Pipelining

Combinational Cloud 3

Register 2
Combinational Cloud 1

Register 1
Combinational Cloud 2

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

We can achieve speed by pipelining

Pipeline Stage introduction

Pipeline Stage introduction

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Single Stage Pipelining

at[3] bt[3] at[2] bt[2] at[1] bt[1]

Register
at-1[3] bt-1[3]

Register
at-1[2] bt-1[2]

at[0] bt[0]

F.A

F.A

Register

F.A
st[0]

F.A
Register

st[1]

Register

st-1[3]

st-1[2] st-1[1]

Shortcut to VERIWELL.lnk

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Single Stage Pipelining 01

Register
at-1[3] bt-1[3]

10
Register
at-1[2] bt-1[2]

11 F.A
st[0]

01

F.A

F.A

Register

F.A
Register

st[1]

Register

st-1[3]

st-1[2] st-1[1]

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Align Data / Balance Paths

Good discipline to line up pipe stages in diagrams.

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Three Stage Pipelining

Register Register Register Register Register
Register

Register

F.A

F.A
Register

Register

F.A
Register Register

Register

F.A
Register Register Register

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Types of Fast Adders

ADDERS

Carry Select Adder

Carry Look ahead Adder

Conditional Sum Adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Carry Select Adders

Important Observation in ripple carry adders

Do we have to wait for the carry to show up to begin doing useful work? We do have to know the carry to get the right answer. But, it can only take on two values

Carry Select Adders compute both possible values and select correct result when we know the answer

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Basic Principle

The adder is partitioned into K groups Two values of sum with cin (1 and 0) are pre computed for each adder group Actual sum is selected using a 2-to-1 MUX by the carry of the previous group Compute possible results in parallel Select when actual carry-in available Requires internal carry for blocks, e.g. ripple Affected by block sizing
1 1

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Two ways of implementation

Carry Select Adder

Uniform Group Carry Select Adder

Non-uniform Group Carry Select Adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Uniform Group 12-Bit Carry Select Adder

Three partitions have been made of 4 bits each Outputs of each 4 bit adder block would be ready simultaneously including the cout of the first adder
Cin = 0 4 - bit Adder Cin = 0 4 - bit Adder S0 Cin = 1 4 - bit Adder Cin = 0 4 - bit Adder S0 Cin = 1 4 - bit Adder

C0

C0

C0
Cin = 1 4 - bit Adder

S0

C1
2-to-1 Mux

S1 4-bit 2-to- 1 Mux

C1
2-to-1 Mux

S1 4-bit 2-to- 1 Mux

C1
2-to-1 Mux

S1 4-bit 2-to- 1 Mux Carry in

Cout[11]

Cout[7]

Cout[3]

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

SUM [11-8]

SUM [7-4]

SUM [3-0]

CSA in an ALU

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Non-uniform Group 12-Bit Carry Select Adder

Three partitions of 3-bits, 4-bits, 5-bits are made The cout of the first block is ready earlier making it faster in functionality than the uniform group 12- bit carry select adder So non-uniform group carry select adder is faster than the uniform group carry select adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Non-uniform Group 12-Bit Carry Select Adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Example

1 1 1 1 1 0 1 1 1 1 0 0 (a) 1 1 1 1 1 1 0 1 0 0 1 1 (b) 1 1 1 1 0 0 0 0 1 1 1 1 (cin=0) 1 1 1 1 1 0 0 1 0 0 0 0 (cin=1)

1 1

11111 11111

1 1

0111 1010

0 1
000

100 011
111

11111

0001

111

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Carry-select: Carried one step further Two-Level Carry-Select Adder

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

A Cin

B Cout

Full Adder

Full adder Sum

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE

Generalization

Advanced Digital Design Fall 2004 Lecture 11 Delivered By M. Mohsin Rahmatullah @ CASE