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Implementation of Ieee Single Precision Floating Point Addition and Multiplication On Fpgas

This document summarizes the implementation of IEEE single precision floating point addition and multiplication on FPGAs. It describes building a bit-parallel floating point adder and a digit-serial floating point multiplier to accommodate the need for 32-bit floating point arithmetic on FPGAs. The adder uses pipelining to increase throughput, while the multiplier uses a digit-serial structure due to the large size of a 32-bit parallel design. Synthesis results show the adder uses 358 logic elements and 27 registers, operating at 183.62MHz, while the multiplier uses 709 logic elements and no registers, operating at 51.937MHz.

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37 views

Implementation of Ieee Single Precision Floating Point Addition and Multiplication On Fpgas

This document summarizes the implementation of IEEE single precision floating point addition and multiplication on FPGAs. It describes building a bit-parallel floating point adder and a digit-serial floating point multiplier to accommodate the need for 32-bit floating point arithmetic on FPGAs. The adder uses pipelining to increase throughput, while the multiplier uses a digit-serial structure due to the large size of a 32-bit parallel design. Synthesis results show the adder uses 358 logic elements and 27 registers, operating at 183.62MHz, while the multiplier uses 709 logic elements and no registers, operating at 51.937MHz.

Uploaded by

yrikki
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs

Aim of the project:


Hardware implementation of addition and multiplication for IEEE single precision floating point numbers . The adder is a Bit-parallel adder, and the multiplier is a Digit Serial Multiplier.

Introduction:
Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. They usually require excessive chip area, a resource that is always limited in FPGAs. On the other hand many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Thus, the necessity for 32-bit floating point operators implemented in FPGAs arises. In an effort to accommodate this need, we use the IEEE 754 standard for binary floating point arithmetic (single precision) to implement a floating-point adder and a floating-point multiplier . The adder is built in a parallel structure and pipelining techniques are used to increase its throughput. The multiplier was implemented with a digit serial structure because a 32-bit parallel multiplier is so large that it is virtually impossible to fit in a single FPGA chip.

Floating Point Format


To determine the value of a floating point number in this format we use the following formula: Value = (-1)s x 2e-127 x 1.f23f22f21.....f0 1-bit sign, S: A value of 1 indicates that the number is negative, and a 0 indicates a positive number. Bias-127 exponent, e = E + bias: This gives us an exponent range from Emin = -126 to Emax = 127. Fraction, f: The fractional part of the number.

FLOATING POINT ADDER


Given two numbers N1 and N2 .el, e2 and s1,s2 are the exponents and significands of the numbers, respectively.

Results : (adder)

FLOATING POINT MULTIPLIER

S1 . 2e1 x S2. 2e2 =S1 x S2 . 2e1+e2 BIT MULTIPLIER:

DIGIT-SERIAL MULTIPLIER:

FLOATING POINT MULTIPLIER:

RESULTS:

Synthesis Summary: Floating point adder: Total Logic Element Total registers Family of FPGA Device Maximum Frequency Floating point multiplier: Total Logic Element Total registers Family of FPGA Device Maximum Frequency Conclusion and Future work: 358 27 Cyclone IV GX EP4CGX22CF19C7 183.62Mhz 709 0 Cyclone IV GX EP4CGX22CF19C7 51.937Mhz

References:

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