Processors

Advanced Computer Architecture

Agenda
Modern processor technology
Instruction set architectures (CISC vs RISC) Typical processors: superscalar, VLIW, superpipelined and vector

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar Processors VLIW Architecture Vector and Symbolic Processors

Design space of processors

Mapping processor families onto a coordinated space of clock rate vs cycles per instruction (CPI) Trends: Clock rates are moving from low to high (implementation technology) Lowering CPI rate (hardware and software approaches)

Superpipelined Conventional Todays Special Very Long subclass RISC Instruction processors processors processors of RISC Word like like processor have (VLIW) Intel Intel higher i486, i860, architecture (Superscalar clock M68040, SPARC, rate uses MIPS VAX/8600, processors) ~ 100 even R3000, 500 IBM 390, RS/6000, IBM which more MHz, etc functional however allow fall into multiple etc. CPI units this have is family. instructions than also faster high superscalar, Typical clock unless to be clock rate issued there thus rate ~ 20 its is during ~ use CPI 33 120 of is each MHz 50 multiple further MHz and cycle, and Withbut with thus low, functional hardwired taking microprogrammed due units CPI to control, long as to a ininstructions lower the typical control, case value CPI of(microprogrammed), typical with vector ~1 similar -CPI supercomputers 2 ~ clock 1 - 20 rate its as clock that of RISC rate is slow

Source: Kai Hwang

Instruction Pipeline
Typical instruction execution involves four phases: fetch, decode, execute & writeback Often executed by instruction pipeline

Source: Kai Hwang

Definitions (instruction pipeline)

Instruction pipeline cycle clock period of the instruction pipeline Instruction issue latency time (cycles) required between issuing of two adjacent instructions Instruction issue rate number of instructions issued per cycle

Instruction issue latency: one instruction issued every two cycles

Pipeline cycle time: doubled by combining pipeline stages

Source: Kai Hwang

Processors & Coprocessors

Central processor of computer is called CPU
Scalar processor Multiple functional units Floating point accelerator

Floating point unit can be coprocessor

Attached with CPU Executes instructions dispatched by CPU Cant be used alone, cant handle I/O operations

Source: Kai Hwang

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar Processors VLIW Architecture Vector and Symbolic Processors

Instruction Set Architectures

Instruction set, defines the primitive commands or machine instructions Characteristics of instruction set: Instruction formats Data formats Addressing modes General purpose registers Opcode specifications Flow control mechanisms

Two approaches: CISC and RISC

Complex Instruction Set Computing (CISC)

Add more and more functions into the hardware, thereby making instruction set very large & complex Characterized by microprogrammed control Typical CISC contains 120 350 instructions Uses a small set of 8 24 general purpose registers Large number of memory reference instructions More than a dozen addressing modes HLL statements directly implemented in hardware Improve execution efficiency

Reduced Instruction Set Computing (RISC)

Only 25% of large set of instructions used frequently 95% of the time 75% of hardware supported functions not used Why use valuable hardware which is rarely used ? Push all these rare instructions to software, only frequently used instructions are done by hardware Characterized by hardwired control Typical RISC contains less than 100 instructions Fixed instruction format (32 bit) Large general purpose registers, most instructions are register based Memory access only by load/store instructions

CISC vs RISC Architectures

Source: Kai Hwang

Source: Kai Hwang

CISC Scalar Processor

Scalar processor executes with scalar data
Simple models work with integer instructions using fixed point operands Complex models work with integer and floating point operations

Both integer unit and floating point unit may be present in same CPU Ideally, its performance should be that of instruction pipeline with one instruction fed per clock cycle Practically, it works in underpipelined situation due to data dependencies, resource conflicts, branch penalties, etc.

Design Philosophy - CISC

1. Implement useful instructions in hardware, resulting in shorter program length and lower software overhead 2. However, this is achieved at the expense of lower clock rate and higher CPI Balance between the two required !

Example 1
Typical CISC architecture with Microprogrammed control Instruction set contains 300 instructions with 20 different addressing modes

CPU consist of two functional units for execution of floating point and integer instructions
Unified cache holds both instructions and data 16 GPRs in instruction unit and Instruction pipelining has six stages

Source: Kai Hwang

Example 2
Processor implements over 100 instructions using 16 GPRs Separate cache each of 4KB for data and instruction with MMUs present in separate memory units

Instruction set supports 18 addressing modes

Integer unit has six stage instruction pipeline, decodes all instructions Floating point unit consist of three stage pipeline

Source: Kai Hwang

General characteristics Large number of instructions More options in the addressing modes

Lower clock rate

High CPI Widely used in personal computer (PC) industry

Source: Kai Hwang

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar Processors VLIW Architecture Vector and Symbolic Processors

RISC Scalar Processor

Generic RISC processors are called scalar RISC because they are designed to issue one instruction per cycle RISC processors push some of the less frequently used operations into software RISC processors depend heavily on a good compiler because complex HLL instructions are to be converted into primitive low level instructions, which are few in number RISC processors have a higher clock rate and lower CPI

General characteristics All use 32-bit instructions Instruction set consist of less than 100 instructions High clock rate Low CPI

Source: Kai Hwang

Example 1
SPARC stands for scalable processor architecture Scalability is due to use of number of register windows (explained on next slide) Floating point unit (FPU) is implemented on a separate chip

Source: Kai Hwang

Window Registers
SPARC runs each procedure with a set of thirty two 32-bit registers

Eight of these registers are global registers shared by all procedures

Remaining twenty four registers are window registers associated with only one procedure Concept of using overlapped registers is the most important feature introduced

Each register window is divided into three sections Ins, Locals and Outs

Source: Kai Hwang

Locals are addressable by each procedure and Ins & Outs are shared among procedures

Example 2
64 bit RISC processor on a single chip It executes 82 instructions, all of them in single clock cycle There are nine functional units connected by multiple data paths There are two floating point units namely multiplier unit and adder unit, both of which can execute concurrently

Source: Kai Hwang

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar and Vector Processors VLIW Architecture Vector and Symbolic Processors

Scalar vs Superscalar Processors

Scalar processors: Execute one instruction per cycle One instruction is issued per cycle Pipeline throughput: one instruction per cycle

Superscalar processors: Multiple instruction pipelines used Multiple instruction issued per cycle and Multiple results generated per cycle

Superscalar Processors
Designed to exploit instruction-level parallelism in user programs Amount of parallelism depends on the type of code being executed On average, at instruction level around 2 instructions can be executed in parallel There is no benefit to have a processor which can be fed with 3 instructions per cycle Thus, instruction-issue degree in superscalar has been limited to 2 5

Pipelining in Superscalar Processors

A superscalar processor of degree m can issue m instructions per cycle To fully utilize, at every cycle, there must be m instructions for execution Dependence on compilers is very high Figure depicts three instruction pipeline

Source: Kai Hwang

Example 1
A typical superscalar architecture Multiple instruction pipelines are used, instruction cache supplies multiple instructions per fetch Multiple functional units are built into integer unit and floating point unit

Multiple data buses run though functional units, and in theory, all such units can be run simultaneously

Source: Kai Hwang

Example 2
A superscalar architecture by IBM Three functional units namely branch processor, fixed point processor and floating point processor, all of which can operate in parallel Branch processor can facilitate execution of up to five instructions per cycle Number of buses of varying width are provided to support high instruction and data bandwidths.

Source: Kai Hwang

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar and Vector Processors VLIW Architecture Vector and Symbolic Processors

Very Large Word Instruction (VLIW) Architectures

Typical VLIW architectures have instruction word length of hundreds of bits Built upon two concepts, namely
1. Superscaler processing
Multiple functional units work concurrently Common large register file is shared

2. Horizontal microcoding
Different fields of the long instruction word carries opcodes to be dispatched to multiple functional units Programs written in conventional short opcodes are to be converted into VLIW format by compilers

Typical VLIW Architecture

Multiple functional units are concurrently used All functional units use the same register file * A typical instruction format

Source: Kai Hwang

Pipelining in VLIW Architecture

Each instruction in VLIW architecture specifies multiple instructions Execute stage has multiple operations Instruction parallelism and data movement in VLIW architecture are specified at compile time

CPI of VLIW architecture is lower than superscalar processor

Source: Kai Hwang

Processors
Advanced Processor Technology
Design Space of Processors Instruction-Set Architectures CISC Scalar Processors RISC Scalar Processors

Superscalar and Vector Processors

Superscalar and Vector Processors VLIW Architecture Vector and Symbolic Processors

Vector Processors
Vector processor is a coprocessor designed to perform vector computations Vector computations involve instructions with large array of operands
Same operation is performed over an array of operands

Vector processor may be designed with : Register to register architecture

Involves vector register files

Memory to memory architecture

Involves memory addresses

Vector Instructions
Register-based instructions
Vi represent vector register of length n si represent scalar register of length n

Memory-based instructions
M(1:n) represent memory array of length n

Source: Kai Hwang

Vector Pipelines
Scalar pipeline Each Execute-Stage operates upon a scalar operand

Vector pipeline

Each Execute-Stage operates upon a vector operand

Source: Kai Hwang

Symbolic Processors
Applications in the areas of pattern recognition, expert systems, artificial intelligence, cognitive science, machine learning, etc. Symbolic processors differ from numeric processors in terms of: Data and knowledge representations Primitive operations Algorithmic behavior Memory I/O communication

Characteristics

Source: Kai Hwang

Example
Symbolic Lisp Processor Multiple processing units are provided which can work in parallel Operands are fetched from scratch pad or stack Processor executes most of the instructions in single machine cycle

Source: Kai Hwang