About The ARM Processor Advanced Risc Machine

Yongjin Kim CASP Lab. Hanyang Univ. [email protected]

ARM Ltd

Founded in November 1990

Spun out of Acorn Computers

Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers

ARM does not fabricate silicon itself

Also develop technologies to assist with the design-in of the ARM architecture

Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

ARM HISTORY(1985 1995)

1985

Acorn Computer Group develops the world's first commercial RISC processor Acorn's ARM processor debuts as the first RISC processor for low-cost PCs Advanced RISC Machines (ARM) spins out of Acorn and Apple Computer's collaboration efforts with a charter to create a new microprocessor standard. VLSI Technology becomes an investor and the first licensee ARM introduces the ARM7 core Samsung license ARM technology ARM introduces the ARM7500 "system-chip" for multimedia applications ARM's Thumb architecture extension gives 32-bit RISC performance at 16-bit system cost and offers industryleading code density ARM launches Software Development Toolkit First StrongARM core from Digital Semiconductor and ARM ARM extends family with ARM8 high-performance solution ARM launches the ARM7100 "PDA-on-a-chip

1987

1990

1993

1994

1995

ARM HISTORY (1996 1998)

1996

ARM and VLSI Technology introduce the ARM810 microprocessor ARM announces ARM7500FE multimedia "system-chip" for the Network Computer Virtual Socket Interface Alliance (VSIA) is formed, with ARM as a charter member ARM and Microsoft work together to extend Windows CE to the ARM architecture ARM and Sun offer direct JavaOS support for ARM RISC architecture ARM introduces high-performance, embedded software modem solutions ARM9TDMI family announced Qualcomm license ARM technology ARM joins Bluetooth consortium Intel licenses StrongARM microprocessor family ARM introduces ARM910 and ARM920 solutions for Windows CE applications ARM develops synthesisable version of the ARM7TDMI core ARM announces ARM10 Thumb family of processors ARM establishes consortium for Windows CE ARM Partners ship more than 50 million ARM Powered products

1997

1998

ARM HISTORY (1999 2001)

1999

ARM announces synthesisable ARM9E processor with enhanced signal processing ARM works with Microsoft to optimize Windows Media Audio ARM introduces MP3 and Dolby Digital Software solutions ARM launches SecurCore family for smartcards ARM introduces Jazelle technology for Java applications ARM introduces ARM922T core Lucent ships ARM10 silicon ARM supports Intel's launch of ARM architecture-compliant XScale microarchitecture ARM announces new ARMv6 architecture ARM announces the ARM VFP9-S and ARM VFP10 vector floating-point coprocessors ARM introduces the ARM926EJ-S soft macrocell, the ARM7EJ core, and the Jazelle Technology Enabling Kit (JTEK)SavaJe and Symbian license Jazelle software for incorporation into their operating systems ARM announces the PrimeXsys platforms. ARM introduces the SecurCore SC200 and SC210 microprocessor cores ARM announces MOVE multimedia acceleration technology for wireless devices

2000

2001

ARM PARTNER

ARM POWERED PRODUCTS

ARM FEATURE

RISC(Reduced Instruction Set Computer) architecture General purpose 32-bit microprocessors Very low power consumption and price Big/Little Endian Mode

Intel x86 Little Endian Motorola Big Endian FIQ Mode C Language Auto Increment/Decrement addressing mode Load/Store multiple instructions Conditional execution

Fast Interrupt Response

Excellent High Level Language Support

Simple and powerful Instruction Set

ARM ARCHITECTURE
Architecture V4T V5TE V5TEJ V6 THUMB X X X X X X X X X X DSP Jazelle Media

ARM ARCHITECTURE

v4T

Thumb instruction set Short 16-bit instructions Typical memory savings of up to 35% DSP instruction set 70% speed up(audio DSP applications) Jazelle technology for java 80% reduction SIMD extensions

5TE

v5TEJ

V6

The Thumb Architecture Extension

Excellent code-density for minimal system memory size and cost 32-bit performance from 8 or16-bit memory on an 8 or 16-bit bus for low system cost.

ARM DSP Instruction Set Extensions

Single-cycle 16x16 and 32x16 MAC implementations 2-3 x DSP performance improvement on ARM9TDMI based CPU products Zero overhead saturation extension support New instructions to load and store pairs of registers, with enhanced addressing modes New CLZ instruction improves normalisation in arithmetic operations and improves divide performance Full support in the ARMv5TE and ARMv6 architecture

ARM Jazelle Technology

The ARM Jazelle technology provides a highly-optimized implementation of the Java Virtual Machine (JVM), speeding up execution times and providing consumers with an enriched user experience on their mobile devices.,

ARM Media Extensions

Overview streaming media performance (film, video phone, music and more), more human-oriented interfaces (voice and handwriting recognition) Feature 2-4x performance increase for audio and video processing Simultaneous computation of 2x16-bit or 4x8-bit operands Fractional arithmetic User definable saturation modes (arbitrary word-width) Dual 16x16 multiply-add/subtract 32x23 fractional MAC Simultaneous 8/16-bit select operations

THE ARM CORE FAMILY- ROADMAP

ROADMAP
Performance

400-900 MIPS (150-825mW)

Xscale

400MIPS

ARM1136J(F)-S

400-550 MIPS +DSP (<300mW)

ARM10E/EJ ARM9E/EJ
200-300 MIPS +DSP (<300mW)

100 MIPS (<50mW)

ARM9

200-300 MIPS (<160mW)

ARM7

Secure core

V4T

V5TE

V5TEJ

V6

ARM7 FAMILY(60-100MIPS)
MMU 8K Cache ARM7 ARM740T
Embedded RTOS core 60-75Mhz(0.18um w/c) Hard Macro IP

PU 8K Cache ARM7 ASB i/face

EMT7 i/face ASB i/face ARM720T

Platform OS core 60-75Mhz(0.18um w/c) 0.65mW/Mhz Hard Macro IP

ARM7TDMI-S ARM7-S
Base Integer core 100Mhz(0.18um w/c) Synthesizable(Soft IP)

ARM7

ARM7TDMI
Base Integer core(Hard Macro IP) 60-100Mhz (0.18um w/c) NEW: low-voltage layout

ARM v4T ISA Von Neumann Architecture Thumb Support Debug Support 3-Stage Pipeline 0.9 MIPS/Mhz

ARM9 FAMILY(200 MIPS)

MMU ARM922T
Platform OS processor core Up to 200Mhz(0.18um w/c) 0.8mW/Mhz

16K Caches MMU 8K Cache ARM9 EMT9 i/face ASBi/face PU ARM9T EMT7 i/face ASB i/face ARM920T
Platform OS processor core Up to 200Mhz(0.18um w/c) 0.8mW/Mhz

4K Caches ARM9T ASB i/face ARM940T

Embedded RTOS processor core Up to 180Mhz(0.18um w/c) 0.85mW/Mhz

ARM9T

ARM9TDMI
Base Integer processor core Up to 220Mhz(0.18um w/c) 0.3mW/Mhz

Hard macro IP ARM v4T ISA Harvard architecture Thumb Support Debug Support 5-Stage Pipeline Dual Caches AMBA ASB bus 1.1 MIPS/Mhz

ARM9E FAMILY(200 MIPS+DSP)

MMU PU ARM946E-S
Embedded OS processor core 160MIPS(0.18um w/c) ~140K gates + SRAM

TCM i/face TCM i/face Flexible Caches Flexible Caches ARM9E-S ARM9E-S EMT7 i/face EMT9 i/face AHB i/face AHB i/face ARM926EJ-S
Platform OS processor core 200MIPS(0.18um w/c target ~190K gates + SRAM

Jazelle Enhanced

Flexible SRAMs ARM9E-S ETM9 i/face AHB i/face ARM966E-S

Embedded processor core 180MIPS(0.18um w/c) ~110K gates + SRAM

ARM9E-S ARM9E-S
Base Integer processor core 180MIPS(0.18um w/c) ~65K gates

Synthesizable (Soft IP) ARM v5TE ISA Thumb Support Debug Support 5-Stage Pipeline Dual Caches AMBA AHB bus

ARM10E FAMILY(390 MIPS+DSP)

MMU ARM966E-S
600Mflops Vector floating Point coprocessor

16K/32K Cache VFP10 ARM10J EMT10 i/face Dual AHB MMU 2x16K Cache ARM10E EMT10 i/face Dual AHB

Jazelle Enhanced

ARM946E-S
Platform OS core 300Mhz(0.15um w/c) Hard Macro IP

ARM966E-S
Platform OS core >400Mhz(0.13um w/c) Hard Macro IP

MMU 2x32K Cache ARM10E EMT10 i/face Dual AHB ARM1020E

Platform OS core 300Mhz(0.15um w/c) Hard Macro IP

ARM v5TE ISA Thumb Code Compression Debug Support 6-Stage Pipeline Dual Cache architecture Dual 64-bit AHB bus Optional VFP coprocessor AMBA AHB bus 1.3 MIPS/Mhz Low power: 0.7mW/MIPS

ARM11 FAMILY(<400 MIPS+DSP+ Jazelle)

ARM1136JF-S
Platform OS core 600Mflops Vector floating Point coprocessor

VFP TCM I/D Cache ARM11

ARM1136J-S TCM
Platform OS core Up to 1Ghz(0.15um w/c)

Multi Port M-layer AHB

I/D Cache ARM11 Multi Port M-layer AHB ARM v6 ISA Thumb Code Compression DSP extensions 8-Stage Pipeline( 35% enhanced) SIMD media processing Multi-port 64bit memory system Optional VFP coprocessor TCM(scratch-pad) memory Low power: 0.4mW/Mhz

ARM11 ARM11
Platform OS core Up to 1Ghz(0.15um w/c)

INTEL SA & XSCALE FAMILY

SA1110
206Mhz

I/D MMU 32K I/D Cache SDRAM 2K Mini/D Cache 64-bit BIU Xcale Core PXA210(250)

SA1100
199Mhz

MMU 8K-D-Cache 16K I-Cache DRAM SA Core

Up to 400Mhz

MMU 16K I/D Cache DRAM SA Core

Up to 233Mhz Only Core Support

SA110

SA core(StrongARM) ARM8 ARM v4 Architecture Harvard Architecture ,I/D Cache 5-Stage Pipeline Xscale ARM5T Architecture Thumb mode Support 7-stage integer, 8-stage memory superpipeline

ARM PROCESSOR CORES

MIPS
Basic Cores Un-cached Cores For Hard real-timer Applications Cached Cores With Embedded real-time applications Cached Cores With full MMU OS Support for e.g. winCE , Symbian OS, Linux ARM1136(J)-S ARM1020E ARM920T ARM926E-S ARM720T

400 200 100

ARM9TDMI ARM9E-S ARM7TDMI ARM7TDMI-S ARM966E-S

ARM1136(J)-S ARM940T ARM946E-S ARM740T

ARM7TDMI Core diagram

ARM INSTRUCTIONS

Registers

31 general-purpose 32-bit Registers 6 Status Registers 6 mode banked( Remapping ) 16 visible Register(R0 R15)

R0-R13 : R14 : R15 : CPSR : SPSR :

General purpose registers( R13 : Stack Pointer (SP) ) Link register ( LR ) Program counter ( PC ) Current program status register Saved program status register
(only accessible in privileged modes)

Conditional execution of instructions

ARM : which executes 32-bit, word-aligned ARM instructions Thumb : which operates with 16-bit, halfword-aligned THUMB instruction (PC uses bit 1 to select between alternate halfwords

Program Status Register Format

Condition Code Flags
31 30 29 28 27

Reserved
8 7 6

Control Bits
5 4 3 2 1 0

N ZCV
Condition Code Flags( arithmetic and logical operations)

F T M M M M M 4 3 2 1 0

N Z C V

: Negative/Less Than : Zero : Carry/Borrow/Extend : Overflow

Control bits

I : IRQ disable (Active Set) F : FIQ disable (Active Set) T : State bit ( 1: Thumb state 0: ARM state) Mode bits

User, FIQ, IRQ, Supervisor, Abort, Undefined

Processor Modes
Mode
User( usr ) FIQ( fiq ) IRQ( irq ) Supervisor( svc) Abort( abt ) Undefined( und ) System( sys )

Value M[4:0]
10000 10001 10010 10011 10111 11011 1111

Description
Normal program execute mode Supports a high-speed data transfer or channel process Used for general purpose interrupt handling A protected mode for the operating system Implements virtual memory and/or memory protection Supports software emulation of hardware coprocessors Runs privileged operating system tasks

Register organization in the ARM state

User R0 R7 R8 R9 R10 R11 R12 R13(SP) R14(LR) R15 (PC) FIQ R0 R7 R8_fiq R9_fiq R10_fiq R11_fiq r12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Abort R0 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)

CPSR

CPSR SPSR_fiq

CPSR SPSR_svc

CPSR SPSR_abt

CPRR SPSR_irq

CPSR SPSR_und

Register organization in the Thumb state

User R0 R7 FIQ R0 R7 Supervisor R0 R7 Abort R0 R7 IRQ R0 R7 Undefined R0 R7

R8 R12 SP LR PC CPSR SP_fiq LR_fiq PC CPSR SPSR_fiq SP_svc LR_svc PC CPSR SPSR_svc

Not Used

SP_abt LR_abt PC CPSR SPSR_abt

SP_irq LR_irq PC CPRR SPSR_irq

SP_und LR_und PC CPSR SPSR_und

Exception

Interrupts, traps, supervisor calls Exceptions arise whenever the normal flow of program has to be halted temporarily

CISC and RISC

Pt = Ti + 2Ti + 3Ti+ + nTi
(Pt : , Ti : , n : ) Ti RISC N CISC

CISC (Complex Instruction Set Computing) Memory Access RISC (Reduced Instruction Set Computing) 1975 IBM John Cocke

Interrupt Concept

Hardware Interrupt

CPU CPU - CPU .

Software Interrupt

Interrupt - program . kernel level

(, , ) ( ,) ( 0 , )

Interrupt - ISR
1. 2. 3. 4.

CPU A CPU (Ic) A PCB

(process state)

data (PC, , )

PCB(process control block) interrupt service routine = interrupt routine = interrupt handler

5.

6. 7.

A Ic , ex) ,

Interrupt -

Interrupt source Input pin, counter, Serial port Interrupt Interrupt vector Interrupt (Address) Interrupt service routine(ISR) Interrupt Interrupt priority , Interrupt priority

Exception Vector
Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 IRQ IRQ Exception Reset Undefined Instruction Software Interrupt Abort (Pre-fetch) Abort (Data) Mode on entry Supervisor Undefined Supervisor Abort Abort Priorities 1 6 6 5 2 Reserved 4 The IRQ exception is a normal interrupt caused by a Low level on the nIRQ input. R13 R14 remapped The FIQ exception is a fast interrupt caused by a Low level on the nFIQ input . R8 R14 remapped Description When the nRESET signal goes LOW When ARM comes across an undefined instruction Software Program Interrupt. System call When the current memory access cannot be completed

0x0000001C

FIQ

FIQ

Exception Flow Reset

nReset
R14_svc = PC SPSR_svc = CPSR Supervisor Mode Enter
M [4:0] = 10011 IRQ Mode ( M[4:0] = 10010 ) ARM state ( T = 0 ) FIQ Disable ( F = 1 ) IRQ Disable ( I = 1 )

R13_svc = Unpredictable value R14_svc = Unpredictable value

Reset Vector Branch PC = 0x00 Fetch Next Instruction fetch

ARM State

Reset Exception Flow

Exception Flow IRQ

User Mode(R0-R15)
User Mode

IRQ Event
Register Remapping R13 to R13_irq R14 to R14_irq Return Address ( PC + 4 ) R14_irq IRQ Mode
CPSR SPSR_irq IRQ Mode ( M[4:0] = 10010 ) ARM state ( T = 0 ) IRQ Disable ( I = 1 )

IRQ SR Entry

SPSR_irq CPSR

User Branch

IRQ Service Routine execution

R14_irq PC

Exit
IRQ SR Exit User Mode(R0-R15)

IRQ Vector Branch PC 0x18

IRQ Exception Entry

IRQ Exception Entry

IRQ Exception Exit

IRQ Exception Flow

Instructions Feature

32 bits wide 4-byte boundaries The Load-Store architecture 3-address data processing instructions Conditional execution of every instruction The inclusion of very powerful load and store multiple register instructions The ability to perform a general shift operation and a general ALU operation in a single instruction that executes in a single clock cycle Open instruction set extension through the coprocessor instruction set. Including adding new registers and data types to the programmers model A very dense 16-bit compressed representation of the instruction set in the Thumb

Instruction Format

Instruction Operation
ADD R1, R2, R3 ; R1: = R2 + R3

Operator

Destination Register(Rd)

Source Register(Rn) Operand 1

Comment Source Register(Rs) Operand 2

Result

Note: 1) Operand 1 is always a register 2) Operand 2 can be a register or an immediate value

Branch Instruction(B , BL)

31 28 27 26 25 24 23 0

Cond

Offset

[31:28] Cond : Condition Field [27:25] 101 : B instruction [24] L bit

0 Branch( B) 1 Branch with Link (BL) A singed 2s complement 24 bit offset Branches beyond +/- 32Mbytes ( Because PC increases 2 words (8 bytes)

[23:0] Offset

Examples
label label label PC, #0 func PC, LR LR, PC PC, =func ; branch unconditionally to label ; branch to label if carry flag is clear ; branch to label if zero flag is set ; R15 = 0, branch to location zero ; subroutine cal to function ; R15 = R14, return to instruction after the BL ; store the address of the instruction after the next one into R14 ready to ; return ; load a 32-bit value into the program counter

B BCC BEQ MOV BL func MOV MOV LDR

Data Processing Instructions Format

31 28 27 26 25 24 21 20 19 16 15 12 11 0

Cond

Opcode S

Rn

Rd

Operand 2

[31:28] Cond : Condition Field [25] I : Immediate Operand

0 : Operand 2 is Register 1 : Operand 2 is an immediate value

[24:21] Opcode : Operation Codes ( Data Processing Instruction ) [20] S : Set condition codes( CPSR effect )

0 : Do not after condition codes 1 : Set condition codes

[19:16] Rn : Source Register Operand 1 (always Register) [15:12] Rd: Destination Register [11:0] Operand 2 : Operand 2 type selection

[11:0] Operand 2 : Operand 2 type selection

0: Register
11 4 3 0

1: immediate value
11 8 7 0

Shift
[11:4] Shift : Shift applied to Rm [3:0] Rm 2nd Operand register

Rm

Rotate

Imm
[11:8] Rotate Shift applied to Imm [7:0] Unsigned 8 bit immediate value

Shift Operation
11 7 6 5 4 11 8 7 6 5 4

Count

Type

Rs

0 Type 1

[11:7] Shift amount 5 bit unsigned integer [6:5] Shift type

[11:7] Shift register Shift amount specified in Bottom-byte of Rs [6:5] Shift type

8 bit immediate value is zero extended to 32 bits,And then subject to a rotate right by twice the value In the rotate field

Op1( Rn )

Operand2 Barrel Shifter

Shift Type Operation

Value 00 01 10 11

Instruction Logical left Logical right Arithmetic right Rotate right

Mnemonic LSL LSR ASR ROR

Rd

ALU

Shift Operations
31 0 31 0

00000

00000

LSL #5
31 0 0 31

LSR #5

00000 0

ASR #5, positive operand

11111 1

ROR #5 ASR #5, negative operand

[24:21] Opcode : Operation Codes

Opcode
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Mnemonic
AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN

Operation
AND Exclusive Subtract Reverse Subtract Add Add with carry Subtract with carry Reverse Subtract with carry Test bits Test bitwise equality Compare Compare Negative Logical (inclusive) OR Mov register or constant Bit Clear Move Not

Action
Rd : = Op1 And Op2 Rd: = Op1 XOR Op2 Rd: = Op1 Op2 Rd: = Op2 Op1 Rd: = Op1 + Op2 Rd: = Op1 + Op2 + C Rd: = Op1 Op2 + C 1 Rd: = Op2 Op1 + C 1 Op1 AND OP2 CPSR Op1 XOR OP2 CPSR Op1 Op2 CPSR Op1 + Op2 CPSR Rd: = Op1 OR Op2 Rd: = Op2 Rd: Op1 AND (NOT Op2) Rd: = NOT Op2

Condition Code Summary

Code Suffix Flags Meaning

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110

EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL

Z Set Z Clear C set C Clear N Set M Clear V Set V Clear C Set and Z Clear C Clear or Z Set N Set and V Set o N Clear and V Clear N Set and V Clear or N Clear and V Set Z Clear and ether N Set and V Set or N Clear and V Clear Z Set or N Set and V Clear or N Clear and V Set ( Ignored )

equal not equal unsigned higher or same unsigned lower negative positive or zero overflow no overflow unsigned higher unsigned lower or same greater or equal less than greater than less than or equal Always

Data Processing Instruction Summary (1)

Arithmetic operations
ADD ADC SUB SUC RSB RSC R0, R1, R2 R0, R1, R2 R0, R1, R2 R0, R1, R2 R0, R1, R2 R0, R1, R2 ; ; ; ; ; ; R0: = R1 + R2 R0: = R1 +R2 + C R0: = R1 R2 R0: = R1 R2 +C -1 R0: = R2 R1 R0: = R2 R1 + C 1

Bit-wise logical Operations

AND ORR EOR BIC R0, R1, R2 R0, R1, R2 R0, R1, R2 R0, R1, R2 ; ; ; ; R0: = R1 and R2 R0: = R1 or R2 R0: = R1 xor R2 R0: = R1 and not R2

Register movement operations

MOV R0, R2 MVN R0, R2 ; R0: = R2 ; R0: = not R2

Data Processing Instruction Summary (2)

Comparison operations
CMP R1, R2 CMN R1, R2 TSTR1, R2 TEQ R1, R2 ; set cc on R1 R2 ; set cc on R1 + R2 ; set cc on R1 and R2 ; set cc on R1 xor R2

Immediate operands
ADD R3, R3, #1 AND R8, R7, #&ff ; R3: = R3 + 1 ; R8: = R7

Shifted register operands

ADD R3, R2, R1, LSL #3 ADD R5, R5, R3, LSL R2 ; R3: = R2 + ( 8 x R1 ) ; R5: = R5 + ( R3 x 2^R2 )

Setting the condition codes

ADDS R2, R2, R10 ADC R3, R3, R1 ; R3: = R2 + ( 8 x R1 ) ; R3: = R2 + ( 8 x R1 )

PSR Transfer Instructions (1)

MRS ( Transfer PSR contents to a register )
31 28 27 23 22 21 16 15 12 11 0

Cond

0 0 0 0 1 0

PS

0 01 1 1 1

Rd

0 0 0 0 0 0 0 0 0 0 0 0

[31:28] Cond : Condition Field [22] PS : Source PSR

0 = CPSR 1 = SPSR_< current mode >

[15:12] Rd : Destination Register

MSR ( Transfer register contents to PSR )

31

28

27

23

22

21

16

15

12

11

Cond

0 0 0 0 1 0

PS

0 01 1 1 1

Rd

0 0 0 0 0 0 0 0 0 0 0 0

[31:28] Cond : Condition Field [22] PS : Destination PSR

0 = CPSR 1 = SPSR_<current mode>

[3:0] Rd : Source Register

PSR Transfer Instructions (2)

MSR ( Transfer register contents to PSR )
31 28 22 26 25 24 23 22 21 12 11 0

Cond

00

10

Pd

1 0 1 0 0 1 1 1 1

Source operand

[31:28] Cond : Condition Field [25] I : Immediate Operand

0 = Source operand is a register 1 = SPSR_<current mode> 0 = CPSR 1 = SPSR_<current mode>

11 4 3 0 11 8 7 0

[22] Pd : Destination PSR

[11:0] Source operand

00000000
[11:4] Source operand is an immediate value [3:0] Source Register

Rm

Rotate

Imm

[11:8] Shift applied to Imm [7:0] Unsigned 8 bit immediate value

PSR Transfer Instructions (3)

Example

The flowing sequence performs a mode change: MSR R0, CPSR ; Take a copy of the CPSR BIC R0, R0, #0x1F ; Clear the mode bits ORR R0, R0, #new_mode ; Select new mode MSR CPSR, R0 ; Write back the modified CPSR The following instruction sets the N,Z,C and V flags: MSR CPSR_flg, #0xF0000000 ; Set all the flags regardless of their ; pervious state ( does not affect any ; control bits)

Multiply and MultiplyAccumulate(MUL, MLA)

31 28 27 22 21 20 19 16 15 12 11 8 7 4 3 0

Cond

0 00000

Rd

Rn

Rs

1 0 0 1

Rm

[31:28] Cond : Condition Field [21] A : Accumulate

0 : Multiply only 1 : Multiply and Accmulate 0 : Do not after condition codes 1 : Set condition codes

[20] S : Set condition codes( CPSR effect )

[19:16] Rd : Destination Register (always Register) [15:12] Rn : Operand Register [11:8] Rs : Operand Register [3:0] Rm : Operand Register

Multiply form

Rd : Rm x Rs Rd : Rm x Rs + Rn

Multiply and Accumulate form

Multiply Long and MultiplyAccumulate Long (MULL, MUAL)

31 28 27 23 22 21 20 19 16 15 12 11 8 7 4 3 0

Cond

0 0 0 0 1

RdHi

RdLo

Rs

1 0 0 1

Rm

[31:28] Cond : Condition Field [21] U : Unsigned

0 : Unsigned 1 : Signed 0 : Multiply only 1 : Multiply and Accmulate 0 : Do not after condition codes 1 : Set condition codes

[21] A : Accumulate

[20] S : Set condition codes( CPSR effect )

[19:16] RdHi : Source Destination Register (always Register) [15:12] RdLo : Source Destination Register (always Register) [11:8] Rs : Operand Register [3:0] Rm : Operand Register

Multiply Long Form

RdHi, RdLo : Rm x Rs RdHi, RdLo : Rm x Rs + RdHi,RdLo

Multiply and Accumulate Long Form

MUL and MLA Instructions Example

Example
R4, R2, R1 R4, R2, R1 R7, R8, R9, R3 R4, R8, R2, R3 ; Set R4 to value of R2 multiplied by R1 ; R4 = R2 x R1, set N and Z flags ; R7 = R8 x R9 + R3 ; R4 = bits 0 to 31 of R2 x R3 ; R8 = bits 32 to 63 of R2 x R3 ; R8, R6 = R0 x R1 ; R8, R5 = R0 x R1 + R8, R5

MUL MULS MLA SMULL

UMULL R6, R8, R0, R1 UMLAL R5, R8, R0, R1

Data transfer instructions Single Data Transfer (LDR, STR)

31 28 27 22 21 20 19 16 15 12 11 8 7 4 3 0

Cond

01

I P U B W

Rn

Rd

Offset

[31:28] Cond : Condition Field [25] I : Immediate [24] P : Pre/Post Indexing Bit

[11:0] Offset

0 = Post: add offset after transfer 1 = Pre: add offset before transfer 0 = Down : Subtract offset from base 1 = Up : add offset to base 0 = Transfer word quantity 1 = Transfer byte quantity 0 = No write-back 1 = Write address into base 0 = Store to memory 1 = Load from memory

11

[23] U : Up/Down Bit

Immediate

[22] B : Byte/Word Bit

[11:0] Unsigned 12-bit Immediate offset

[21] Write-back Bit

11 4 3 0

Shift

Rm

[20] Load/Store Bit

[11:4] Shift applied to Rm [3:0] Offset register

[19:16] Base Register [15:12] Source/Destination Registers

LDR and STR Transfer Mode

LDR{cond}{B} LDR{cond}{B} STR{cond}{B} Rd, address{!} Rd, =expression Rd, address{!} ; Rd:= contents of address ; Rd:= expression ; contents of address := Rd

MODE
[Rn] [Rn, expression] [Rn, Rm] [Rn, Rm, shift cnt] [Rn], expression [Rn], Rm [Rn], Rm, shift cnt Rn

Effective Address
None Pre-indexed Pre-indexed Pre-indexed Post-indexed Post-indexed Post-indexed Rn, expression Rn, Rm Rn, ( Rm shift by cnt ) Rn Rn Rn

Indexing

# Rn : base address register Rm : offset(register), signed value Expression : immediate value(12bit 4095 - +4096 ) Shift : LSL, LSR, ASR,ROR cnt : 1 31 value

LDR and STR Address Mode

Pre-indexed Addressing Mode

Rn : Base Address Rn Offset Offset : 12 bit immediate value or Register value Register Offset : Shift operation (optional)

Example (1)

LDR R5, ThreeCubed ..

Example LDR R0, [R1] LDR R0, [R1, #132] STR R0, [R1, R2] LDR R0, [R1,R2, LSL #2]

ThreeCubed DCD 27 ; LDR R5, [PC, #constant] (2) LDR R0, =12345678 ;LDR R0 [PC, #Literal Pool]

; R1:base , Offset : no ; R1:base , Offset : #132 ; R1:base , Offset : R2 ; R1:base , Offset : R2 << 2

Post-indexed Addressing Mode

Rn : Base Address Register Write-Back Function

; 1. R0 = [R1] 2. R1 = R1 + R2 ; 1. [R1] = R0 2 . R1 = R1 + 20

Example LDR R0, [R1],R2 STR R0, [R1], #20

Relative Addressing Mode

Write-Back

Base address register = Base address register + Offset value Sign : ! Example
LDR LDR MOV R0, =table_end R1, =table R2, #0 ; Write-Back function R2, R2, #1 R0, R1 loop

Loop STR

R2, [R0, #-4]! ADD CMP BNE ALIGN

table % table_end

table_length+4

1000 2 entry , table 1000 table_end 1008 . STR 1008 , -4 R2 1004 4 , Write-Back R0 1004(1008-40 .

Block data transfer (LDM, STM)

31 28 27 25 24 23 23 22 21 19 16 15 0

Cond

100 P U S W L

Rn

Register list

[31:28] Cond : Condition Field [24] P : Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset before transfer 0 = Down : Subtract offset from base 1 = Up : add offset to base 0 = Do not load PSR or user mode 1 = Load PSR or force user mode 0 = No write-back 1 = Write address into base 0 = Store to memory 1 = Load from memory

[23] U : Up/Down Bit

[22] P : PSR & Force User BIt

[21] Write-back Bit

[20] Load/Store Bit

[19:16] Base Register

Multiple register transfer addressing modes

R9 R5 R1 R9 R0 100c16 R9 101816 R9 R5 R1 R0 100c16 101816

100016 STMIA R9!,{R0, R1,R5} 101816

100016 STMIB R9!,{R0, R1,R5} 101816

R9

R5 R1 R0

100c16 R9 R5 R1 100016 R9 R0

100c16

R9

100016

STMDA R9!,{R0, R1,R5}

STMDB R9!,{R0, R1,R5}

The mapping between the stack and block copy views of the load and store multiple instructions
Ascending Full Before Increment After STMIB STMFA STMIA STMEA LDMDB LDMEA LDMDA LDMFA LDMIA LDMFD STMDB STMFD STMDA Empty Descending Full Empty LDMIB LDMED

Before Decrement

After

Directives

Data structure definitions and allocation of space for data Partitioning of files into logical subdivisions Error reporting and control of assembly listing Definition of symbols Conditional and repetitive assembly, and inclusion of subsidiary files.

# directive

The # directive describes space within a storage map that has been defined using the ^ directive Usage

If a storage map is set by a ^directive that specifies a base-register, the base register is implicit in all labels defined by following 3 directives, until the next ^ directive.

Example
^ # 0, R9 4 ; set @ to the address stored in R9 ; increment @ by 4 bytes

Lab #

; set Lab to the address [R9 + 4] ; and then increment @ by 4 bytes

LDR

R0, Lab

; equivalent to LDR R0, [R9, #4]

; @ - the value of the storage location counter

% directive

The % directive reserves a zeroed block of memory.

Example
AREA MyData, DATA, READWRITE 255 ; defines 255 bytes of zeroed store %

Data1

[ or IF directive

The IF directive introduces a condition that is used to decide whether to assemble a sequence of instructions and/or directives Usage

Use IF with ENDIF, and optionally with ELSE, for sequences of instructions and/or directives that are only to be assembled or acted on under a specified condition

Example
[ Version = 1.0 ; code and / or ; directives | ; code and / or ; directives ] ; ENDIF ; ELSE ; IF

ALIGN directive

By default, the ALIGN directive aligns the current location within the code to a word(4byte) boundary Usage

Use ALIGN to ensure that your code is correctly aligned

Example
AREA Example, CODE, READONLY 1 ; instruction ; pc misaligned ; ensures that lable1 addresses the following R5, #0x5 cacheable, CODE, ALIGN=4 ; aligned on 16-byte boundary pc, lr 16 ; aligned only on 4-byte boundary ; now aligned on 16-byte boundary R6, =label1 DCB ALIGN

start LDR

label1

MOV AREA

rout1

; code ; code MOV ALIGN

rout2

; code

Data directive

The DATA directive informs the assembler that a label is a data-in-code label. This means that the label is the address of data within a code segment. Usage

You must use the DATA directive when you define data in a Thumb code area with any of the data-defining directives such as DCD, DCB, and DCW

Example
AREA example, CODE

Thumb_fn ; code ; code MOV Thumb_Data DATA DCB 1, 3, 4 pc, lr

DCB(=) DCW DCD(&) directives

Directives allocates one or more bytes( halfword, word ) of memory Usage

You must use the DATA directive if you use DCB(DCW, DCW) to define labeled data within Thumb code.

Example
DCB AREA DCW DCW C_string, 0 MiscData, DATA, READWRITE -225, 2*number number + 4 1, 5, 20 mem06 glb + 4 ; Defines 3 words containing decimal values 1, 5, and 20 ; Defines 1 word containing the address of the label ; mem06 ; Defines 1 word containing 4 + the value of glb

C_string Data

data1 data2 data3

DCD DCD DCD

GBLA directive

The GBLA directive declares and initializes a global arithmetic variable. The range of values that arithmetic variables may take is the same as that of numeric expressions Usage

Using GBLA for a variable that is already defined re-initializes the variable to 0.

Example
GBLA objectsize 0xff objectsize ; declare the variable name ; set its value ; quote the variable SETA %

Objectsize

GET or INCLUDE directive

The GET directive includes a file within the file being assembled. The included file is assembled. INCLUDE is a synonym for GET Usage

GET is useful for including macro definitions, EQUs, and storage maps in an assembly

Example
AREA GET Example, CODE, READONLY file1.s ; include file1 if it exists ; in the current place GET c:\project\file2.s ; includes files

Instruction Example(1)
AREA READONLY SWI_WriteC SWI_Exit ENTRY START ADR LOOP LDRB CMP SWINE BNE SWI TEXT = &0d, 0 END HelloW, Code, EQU &0 EQU
; declare code area ; output character in R0 ; finish program &11 ; code entry point ; R1 -> Hello World ; get the next byte ; check for text end ; if not end print ; end loop back ; end of execution ; end of program source

R1, TEXT R0, [R1], #1 R0, #0 SWI_WriteC LOOP SWI_Exit Hello World, &0a,

Instruction Example(2)
AREA Blkcpy, Code, READONLY SWI_WriteC EQU &0 SWI_Exit EQU &11 ENTRY ADR R1, TABLE1 ADR R2, TABLE2 ADR R3, T1END LOOP1 LDR R0, [R1], #4 STR R0, [R2], #4 CMP R1, R3 BLT R1, R3 ADR R1, TABLE2 LOOP2 LDRB R0, [R1], #1 CMP R0, #0 SWINE SWI_WriteC BNE LOOP2 SWI SWI_Exit TABLE1 = This is the right string!, &0a, &0d, 0 T1END ALIGN TABLE2 = This is the wrong string!, 0 END ; output character in R0 ; finish program ; code entry point ; R0 -> TABLE1 ; R1 -> TABLE2 ; R3 -> T1END ; get TABLE1 1st word ; copy into TABLE2 ; finished? ; if not, do more ; R1 -> TABLE2 ; get next byte ; check for text end ; if not end, print ; and loop back ; finish ;ensure word alignment

Instruction Example(3)
AREA SWI_WriteC SWI_Exit ENTRY LDR BL SWI VALUE DCD HexOut MOV LOOP MOV CMP ADDGT ADDLE SWI MOV SUBS BNE MOV END Hex_Out, CODE, READONLY EQU &0 EQU &11 R1, VALUE HexOut SWI_Exit &12345678 R2, #8 R0, R1, LSR #28 R0, #9 R0, R0, #A-10 R0, R0, #0 SWI_WriteC R1, R1, LSL #4 R2, R2, #1 LOOP pc, R14 ; output character in R0 ; finish program ; code entry point ; get value to print ; call hexadecimal output ; finish ; test value ; nibble count = 8 ; get top nibble ; 0-9 or A-F ? ; ASCII alphabetic ; ASCII numeric ; print character ; shift left one nibble ; decrement nibble count ; if more do next nibble ; return

Instruction Example(4)
AREA SWI_WriteC SWI_Exit ENTRY BL = ENTRY BL = ALIGN SWI TextOut LDRB CMP SWINE BNE ADD BIC MOV END Text_Out, CODE, READONLY EQU &0 EQU &11 TextOut Test string, &0a, &0d, 0 TextOut Test string, &0a, &0d, 0 SWI_Exit R0, [R14], #1 R0, #0 SWI_WriteC TextOut R14, R14, #3 R14, R14, #3 pc, r14 ; finish ; get next character ; test for end mark ; if not end, print ; and loop ; pass next word boundary ; round back to boundary ; return ; output character in R0 ; finish program ; code entry point ; print following string

Instruction Example(5)
#include <stdio.h> void my_strcpy(char *src, char *dst) { int ch; __asm { loop: LDRB ch, [src], #1 STRB ch, [dst], #1 CMP ch, #0 BNE loop } } int main(void) { char a[]= "hello world!"; char b[20]; __asm { MOV R0, a MOV R1, b BL my_strcpy, {R0, R1}, {}, {} } printf(Original string = %s\n, a); printf(Copied string = s\n, b); return 0; }