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65 NM CMOS Devices For Low Power Applications

This paper analyzes 65nm CMOS devices for low power applications. It compares SOI CMOS and bulk CMOS, concluding that SOI CMOS is better suited for low standby power due to challenges with scaling bulk MOSFETs like high doping and leakage currents. SOI CMOS uses a thin silicon body and buried oxide layer to reduce short channel effects and leakage, making it suitable for low standby power logic chips.

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Hammad Ansari
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83 views1 page

65 NM CMOS Devices For Low Power Applications

This paper analyzes 65nm CMOS devices for low power applications. It compares SOI CMOS and bulk CMOS, concluding that SOI CMOS is better suited for low standby power due to challenges with scaling bulk MOSFETs like high doping and leakage currents. SOI CMOS uses a thin silicon body and buried oxide layer to reduce short channel effects and leakage, making it suitable for low standby power logic chips.

Uploaded by

Hammad Ansari
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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65 nm CMOS devices for Low Power Applications

SUMMARY

This paper analyses the performance of 65nm cmos device for low power applications. A comparison is done between SOI CMOS and BULK CMOS devices which resulted in the conclusion that SOI CMOS is more appropriate for low stand-by power applications. Scaling of cmos devices is done in order to ensure a faster operation. Challenges with scaling of planar bulk MOSFET are high channel doping, Junction leakage, various Short channel effects, and increase in the Source/ Drain series resistance. So due to these challenges SOI MOSFETS and FINFETS seems to be better options. The control of static power dissipation with scaling is the most crucial for low power logic. For this reason transistor leakage current is projected lower. Low power logic is referred to the chips for mobile systems in which leakage current is pulled down by the battery. Two categories in lower power are low operating power and low standby power. Low operating power chips are used for high performance mobile applications. On the other hand LSTP chips are used in cellular telephones and lstp are characterized by operating frequency and low battery capacity and its focus is to have the lowest possible static power dissipation. TCAD device simulator (simulated with process enhancements such as retrograde channel doping and Halo implants to reduce short channel effects) is used to simulate NMOS and PMOS deices at 65nm technology. Estimated leakage current for both devices is about10 nA/mm and therefore these devices are more suitable for Low Operating Power (LOP) chips. In SOI CMOS to reduced SCE a 100nm buried oxide layer implanted in the silicon substrate. To enhance mobility a 50 nm silicon body is incorporated for fully depleted but with minimal doping in SOI devices. To lower the off current and to maintain the drive current a higher doping is implemented in source-drain regions. This minimizes the width of depletion layer and control the sce. The decrease in doping level reduces the drive current. After comparison between SOI CMOS and BULK CMOS it was found out that the light doping is required in SOI CMOS and sce effects are controlled in better manner. Range of 5e+17 was introduced in the source/drain extension regions to control leakage current and sce. Thus it effectively reduces off current. Thus SOI CMOS can be used in low standby power logic chips.

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