VHDL Lab File

Submitted To: Chaman Lal

Submitted By: Gaurav Sehgal ECE 4X (2008-2012) A2305108214

AIM To verify 2input AND gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AND2 IS PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END AND2; ARCHITECTURE AND2_DATAFLOW OF AND2 IS BEGIN Z<= X AND Y; END AND2_DATAFLOW;

OUTPUT

AIM To verify 3input AND gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AND3 IS PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END AND3; ARCHITECTURE AND3_DATAFLOW OF AND3 IS BEGIN Z<= W AND X AND Y; END AND3_DATAFLOW;

OUTPUT

AIM To verify 4input AND gate Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AND4 IS PORT(I:IN STD_LOGIC_VECTOR(0 TO 3); Y:OUT STD_LOGIC); END AND4; ARCHITECTURE AND4_STRUCTURE OF AND4 IS COMPONENT AND3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; BEGIN A3:AND3 PORT MAP (I(0),I(1),I(2),S1); A2:AND2 PORT MAP (I(3),S1,Y); END AND4_STRUCTURE;

OUTPUT

AIM To verify 2input OR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR2 IS PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END OR2; ARCHITECTURE OR2_DATAFLOW OF OR2 IS BEGIN Z<= X OR Y; END OR2_DATAFLOW;

OUTPUT

AIM To verify 3input OR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR3 IS PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END OR3; ARCHITECTURE OR3_DATAFLOW OF OR3 IS BEGIN Z<= W OR X OR Y; END OR3_DATAFLOW;

OUTPUT

AIM To verify 4input OR gate Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR4 IS PORT(I:IN STD_LOGIC_VECTOR(0 TO 3); Y:OUT STD_LOGIC); END OR4; ARCHITECTURE OR4_STRUCTURE OF OR4 IS COMPONENTOR3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; BEGIN O3:OR3 PORT MAP (I(0),I(1),I(2),S1); O2:OR2 PORT MAP (I(3),S1,Y); END OR4_STRUCTURE;

OUTPUT

AIM To verify 2input NAND gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY NAND2 IS PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END NAND2; ARCHITECTURE NAND2_DATAFLOW OF NAND2 IS BEGIN Z<= X NAND Y; END NAND2_DATAFLOW;

OUTPUT

AIM To verify 3input NAND gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY NAND3 IS PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END NAND3; ARCHITECTURE NAND3_DATAFLOW OF NAND3 IS BEGIN Z<= NOT( W AND X AND Y); END NAND3_DATAFLOW;

OUTPUT

AIM To verify 4input NAND gate Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY NAND4 IS PORT(I:IN STD_LOGIC_VECTOR(0 TO 3); Y:OUT STD_LOGIC); END NAND4; ARCHITECTURE NAND4_STRUCTURE OF NAND4 IS COMPONENT NAND3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; COMPONENT NAND2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; BEGIN NA3:NAND3 PORT MAP (I(0),I(1),I(2),S1); NA2:NAND2 PORT MAP (I(3),S1,Y); END NAND4_STRUCTURE;

OUTPUT

AIM To verify 2input XOR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XOR2 IS PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END XOR2; ARCHITECTURE XOR2_DATAFLOW OF XOR2 IS BEGIN Z<= X XOR Y; END XOR2_DATAFLOW;

OUTPUT

AIM To verify 3input XOR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XOR3 IS PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END XOR3; ARCHITECTURE XOR3_DATAFLOW OF XOR3 IS BEGIN Z<= W XOR X XOR Y; END XOR3_DATAFLOW;

OUTPUT

AIM To verify 4input XOR gate Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY X OR4 IS PORT(I:IN STD_LOGIC_VECTOR(0 TO 3); Y:OUT STD_LOGIC); END XOR4; ARCHITECTURE XOR4_STRUCTURE OF XOR4 IS COMPONENT XOR3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; COMPONENT XOR2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; BEGIN XO3:XOR3 PORT MAP (I(0),I(1),I(2),S1); XO2:XOR2 PORT MAP (I(3),S1,Y); END XOR4_STRUCTURE;

OUTPUT

AIM To verify 2input XNOR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XNOR2 IS PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END XNOR2; ARCHITECTURE XNOR2_DATAFLOW OF XNOR2 IS BEGIN Z<= NOT(X XOR Y); END XNOR2_DATAFLOW;

OUTPUT

AIM To verify 3input XNOR gate TOOL REQUIRED FPGA Advantage 7.2

Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XNOR3 IS PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END XNOR3; ARCHITECTURE XNOR3_DATAFLOW OF XNOR3 IS BEGIN Z<= NOT( W XOR X XOR Y); END XNOR3_DATAFLOW;

OUTPUT

AIM To verify 4input XNOR gate Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XNOR4 IS PORT(I:IN STD_LOGIC_VECTOR(0 TO 3); Y:OUT STD_LOGIC); END XNOR4; ARCHITECTURE XNOR4_STRUCTURE OF XNOR4 IS COMPONENT XNOR3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; COMPONENT XNOR2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; BEGIN XNO3:XNOR3 PORT MAP (I(0),I(1),I(2),S1); XNO2:XNOR2 PORT MAP (I(3),S1,Y); END XNOR4_STRUCTURE;

OUTPUT

AIM To verify Half Adder Code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HALF_ADDER IS PORT (A,B:IN STD_LOGIC; SUM,CARRY:OUT STD_LOGIC); END HALF_ADDER; ARCHITECTURE HALF_ADDER_STRUCTURE OF HALF_ADDER IS COMPONENT XOR2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; BEGIN A2:AND2 PORT MAP(A,B,CARRY); XR2:XOR2 PORT MAP(A,B,SUM); END HALF_ADDER_STRUCTURE; OUTPUT

AIM To verify Full Adder Code

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FULL_ADDER IS PORT (A,B,CIN:IN STD_LOGIC; SUM,CARRY:OUT STD_LOGIC); END FULL_ADDER; ARCHITECTURE FULL_ADDER_STRUCTURE OF FULL_ADDER IS COMPONENT XOR3 PORT(W,X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT OR3 PORT(W,X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; SIGNAL S: STD_LOGIC_VECTOR(0 TO 2); BEGIN A1:AND2 PORT MAP(A,B,S(0)); A2:AND2 PORT MAP(B,CIN,S(1)); A3:AND2 PORT MAP(A,CIN,S(2)); XR3:XOR3 PORT MAP(A,B,CIN,SUM); R3: OR3 PORT MAP(S(0),S(1),S(2),CARRY); END FULL_ADDER_STRUCTURE;

OUTPUT

AIM To verify Full Subtractor Code

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FULL_SUBTRACTOR IS PORT (A,B,BIN:IN STD_LOGIC; Difference,Borrow:OUT STD_LOGIC); END FULL_ SUBTRACTOR; ARCHITECTURE FULL_ SUBTRACTOR _STRUCTURE OF FULL_ SUBTRACTOR IS COMPONENT XOR3 PORT(W,X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT XOR2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 PORT(X,Y:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT1 PORT(X:IN STD_LOGIC;Y:OUT STD_LOGIC); END COMPONENT; SIGNAL S: STD_LOGIC_VECTOR(0 TO 4);

BEGIN N1:NOT1 PORT MAP(A,S(0)); A1:AND2 PORT MAP(S1,B,S(1)); XR2: XOR2 PORT MAP(A,B,S(2)); N2:NOT1 PORT MAP (S(2),S(3)); A2:AND2 PORT MAP(BIN,S(3),S(4)); XR3:XOR3 PORT MAP(A,B,BIN,DIFFERENCE); R2: OR2 PORT MAP(S(4),S(1),BORROW); END FULL_ SUBTRACTOR _STRUCTURE;

OUTPUT

AIM To verify 2x1MUX

Code
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX_2X1 IS PORT (I0,I1,S0:IN STD_LOGIC; Y:OUT STD_LOGIC); END MUX_2X1; ARCHITECTURE MUX_BEHAVIOUR OF MUX_2X1 IS BEGIN PROCESS(I0,I1,S0) BEGIN IF(S0='0') THEN Y<=I0; ELSE Y<=I1; END IF; END PROCESS; END MUX_BEHAVIOUR;

OUTPUT

AIM To verify 4x1MUX

TOOL REQUIRED FPGA Advantage 7.2

Code

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX_4X1 IS PORT (I:IN STD_LOGIC_VECTOR(0 TO 3);S:IN STD_LOGIC_VECTOR(0 TO 1); Y:OUT STD_LOGIC); END MUX_4X1; ARCHITECTURE MUX_BEHAVIOUR OF MUX_4X1 IS BEGIN PROCESS(I,S) BEGIN IF(S=00) THEN Y<=I(0); ELSIF(S=01) THEN Y<=I(1); ELSIF(S=10) THEN ` ELSE Y<=I(2);

Y<=I(3); END IF; END PROCESS; END MUX_BEHAVIOUR;

OUTPUT