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    CB4CE

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    This document describes a 4-bit cascadable binary counter design element that can be cleared asynchronously. It provides the supported architectures, an introduction to the counter's functionality, a logic table, and notes on design entry and where to find more information.

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    CB4CE

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    228 views2 pages
    This document describes a 4-bit cascadable binary counter design element that can be cleared asynchronously. It provides the supported architectures, an introduction to the counter's functionality, a logic table, and notes on design entry and where to find more information.

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    This document describes a 4-bit cascadable binary counter design element that can be cleared asynchronously. It provides the supported architectures, an introduction to the counter's functionality, a logic table, and notes on design entry and where to find more information.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    228 views2 pages

    CB4CE

    Uploaded by

    劉成
    This document describes a 4-bit cascadable binary counter design element that can be cleared asynchronously. It provides the supported architectures, an introduction to the counter's functionality, a logic table, and notes on design entry and where to find more information.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    CB4CE

    Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

    Supported Architectures
    This design element is supported in the following architectures: XC9500 CoolRunner-II CoolRunner XPLA3

    Introduction
    This design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Lowto-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Create larger counters by connecting the CEO output of each stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input or use the TC output if it does not. This counter is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net.

    Logic Table
    Inputs CLR 1 0 0 X 0 1 CE X X C 0 No change Inc Qz-Q0 0 No change TC Outputs TC 0 0 CEO CEO

    z = bit width - 1 TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE

    Design Entry Method


    This design element is only for use in schematics.

    For More Information


    See the appropriate CPLD User Guide. See the appropriate CPLD Data Sheets.

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