MS PHD Sample Interview Questionpapers
MS PHD Sample Interview Questionpapers
vcc 1 mA
A B 1 Volt
Rin ? R1
Figure 3: Figure for Problem 3 4. Find the logic equation realized by the circuit shown in Figure 4.
C I0 I1 I2 C I3 4 to 1 MUX F S1 S0 A B
2. Find VCE of the transistor in Figure 2. You may assume that the VBE of the device is 0.7 V, and that the device has a very high .
Figure 4: Figure for Problem 4 5. Refer to Figure 5. The waveform at S is shown. For t < 0, Q = 0. Sketch the waveform at Q for t > 0. The NOR gates have a propogation delay of Td .
Vdd 0 t S
Figure 5: Figure for Problem 5 Figure 2: Figure for Problem 2 6. A reverse biased p+ n diode has a depletion region of width W , and a voltage of V1 volts across the junction. The n region is uniformly doped. Neglect bi , the built in potential of the junction. What is the voltage required across the diode increase the depletion width to 2 W ? 7. Suppose we have in 2s complement form, the binary numbers 10011 and 01011. Determine the product. ( 1 mark)
3. For the circuit shown in Figure 3, mark the inverting and noninverting terminals of the opamp to ensure negative