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    DDR SDRAM Presentation

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    santanu_sinha87
    This document describes the design and implementation of a DDR SDRAM controller for a system on chip. It discusses the architecture of DDR SDRAM, including double data rate interfaces, banks, row and column selects. It also details the design of the memory controller, including resynchronizing data, floorplanning the design, and future work to improve refresh handling and reduce latency.

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    DDR SDRAM Presentation

    Uploaded by

    santanu_sinha87
    121 views21 pages
    This document describes the design and implementation of a DDR SDRAM controller for a system on chip. It discusses the architecture of DDR SDRAM, including double data rate interfaces, banks, row and column selects. It also details the design of the memory controller, including resynchronizing data, floorplanning the design, and future work to improve refresh handling and reduce latency.

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    DDR Coding

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    This document describes the design and implementation of a DDR SDRAM controller for a system on chip. It discusses the architecture of DDR SDRAM, including double data rate interfaces, banks, row and column selects. It also details the design of the memory controller, including resynchronizing data, floorplanning the design, and future work to improve refresh handling and reduce latency.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    121 views21 pages

    DDR SDRAM Presentation

    Uploaded by

    santanu_sinha87
    This document describes the design and implementation of a DDR SDRAM controller for a system on chip. It discusses the architecture of DDR SDRAM, including double data rate interfaces, banks, row and column selects. It also details the design of the memory controller, including resynchronizing data, floorplanning the design, and future work to improve refresh handling and reduce latency.

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    Download as pdf or txt
    of 21

    DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER FOR SYSTEM ON CHIP

    Magnus Sjlander

    2002-12-13

    Contents
    Double Data Rate Interfaces DDR SDRAM Architecture and Functionality DDR Memory Controller Data Resynchronization Floorplan and Place & Route Future Work Conclusion

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    Double Data Rate Interfaces


    New Data Transmissions on rising and falling edge Data Strobe
    SDR

    Advantages Time of Flight Clock Skew Pin Count Bandwidth Disadvantage Synchronization

    Clk Data
    D0 D1 D2 D3 D4 D5 D6 D7

    DDR Clk Data Strobe Data


    D0 D1 D2 D3 D4 D5 D6 D7

    Don't care

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    Four Banks Row and Column Select Lines 1T Memory Cells Sense Amplifiers Global Data Path

    SDRAM Architecture

    2002-12-13 4
    VDD SE* SE BL* BL WL M1 Cs BL* BL CBL Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers

    Row Decoder Row Decoder

    Row Decoder Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Row Decoder

    Central I/O
    Row Decoder Row Decoder Row Decoder Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Row Decoder

    MO/EAB/RTN/D Magnus Sjlander

    DDR SDRAM Architecture


    2n-prefetch Delay Lock Loop
    I/O Control
    64 32

    Input Buffer
    CK, CK

    WEi

    Bank Select

    Data Input Register Serial to Parallel


    64

    DMi

    Refresh Counter Row Buffer

    Row Decoder

    Bank 2 Bank 3 Bank 4

    Output Buffer Strobe Gen.

    Bank 1 Sense AMP 2n-prefetch

    ADDR

    Address Register

    CK, CK

    DQ

    Column Buffer

    Column Decoder Latency and Burst Length

    Programming Register
    WEi

    DLL
    CK, CK DMi

    DQS

    Timing Register
    CK, CK CKE RAS CAS WE DM CS

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    DDR SDRAM Improvements


    SDR SDRAM

    Long Delay in Column Decode and Data Lines Added a Delay Lock Loop to Increase Clock Frequency

    Clk Data
    7 ns Read Data started available D0 D1 7 ns Clock period

    DDR SDRAM Clk


    De l ay

    Delayed Clk Data


    7 ns Read Data started available D0 D1 5 ns Clock period

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    DDR SDRAM Commands


    Same Commands as for Standard SDRAM READ WRITE ACTIVATE PRECHARGE REFRESH MRS (Mode Register Set) Added EMRS (Extended MRS)
    2002-12-13 7

    MO/EAB/RTN/D Magnus Sjlander

    DDR SDRAM Memory Controller


    DDR SDRAM Memory Controller Command Data Command Address APB Buss AHB Buss Write Data AHB Read Data Read Data Read Data Initialize Data Command Address Data Strobe Data Mask Write Data DQeven DQodd DQ Core Memory Controller Command Address DQS DDR SDRAM

    APB

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    Core Memory Controller


    Initialize Initialize Initialization Command Activate/Precharge Command Address Refresh Command Refresh Timing Address Enable DQS Read/Write Command Address

    Address

    Next Address

    Address Open Banks Row Open

    Command

    Address Address Current Address Command Increment Boundary Read Write Command

    2002-12-13

    MO/EAB/RTN/D Magnus Sjlander

    AHB Interface
    AHB Interface Command Address Sample Present Increment Counter Write Data AHB Core Data Addr Read Data Data Data Buffer Data x2 Addr Data

    Command Address AHB Buss

    Core Memory Controller

    Command Address DQS DDR SDRAM DQ

    Data Strobe Data Mask Write Data Read Data DQ Even even Read Data DQ Odd odd

    2002-12-13

    10

    MO/EAB/RTN/D Magnus Sjlander

    Arbiter
    DDR SDRAM Memory Controller

    Command AHB Buss 0 AHB Buss 1 Address Write Data Read Data AHB I Data Strobe Data Mask Write Data Command Address
    Arbiter

    Command Address Core Memory Controller

    Command Address DQS DDR SDRAM DQ

    Command Address Write Data Read Data AHB II

    Command Address Data Mask Write Data Data Strobe Read Data Read Data

    Data Strobe Write Data

    DQeven DQodd

    2002-12-13

    11

    MO/EAB/RTN/D Magnus Sjlander

    Capturing the Data


    Phase Shift the Data Strobe Resynchronize the Data
    Clk Command Address Data Strobe Data
    Don't care
    2002-12-13 12

    NOP

    READ Col n

    NOP

    MO/EAB/RTN/D Magnus Sjlander

    Phase Shift the Data Strobe


    Delay Lock Loop Inverter Delay PCB Line Delay Programmable Delay Line with Temperature Sensing
    Phase Detector and Control Logic

    Data Strobe

    Digital Delay Line

    Data Strobe Delayed 90o

    Programmable Delay Line

    Data Strobe

    Data Strobe Delayed 90o

    Programmable Look Up Table

    Temperature Sensor

    2002-12-13

    13

    MO/EAB/RTN/D Magnus Sjlander

    Synchronization of the Data


    D Q

    Data Even

    One Flip-Flop for each Flank to Sample

    Data Data Strobe

    Data Odd

    Data Strobe Data Data Even Data Odd


    0 1 0 1 2 3 2 3 4 5 4 5 6 7 6 7

    Do not care
    2002-12-13 14

    MO/EAB/RTN/D Magnus Sjlander

    Synchronization of the Data Continued


    Reference Clock Low
    Rising Edge of Data Strobe

    Data Strobe Reference Clk Clk x2 Data Even


    0
    Data Stable

    Reference Clock High


    Rising Edge of Data Strobe

    Data Strobe Reference Clk Clk x2 Data Even


    0
    Data Stable Not stable

    2002-12-13

    15

    MO/EAB/RTN/D Magnus Sjlander

    Synchronization of the Data Continued


    High Clk I
    D QI

    Simplified Phase Detector

    &

    S R

    Phase

    High Clk II

    D QII

    Clk I Clk II QI Q II Phase


    Time Line Time Time Line Line
    2002-12-13 16

    Undefined
    MO/EAB/RTN/D Magnus Sjlander

    Floorplan
    50 m

    AHB I Read, Write and Address Buss


    Data Buffer (AHB I) 155 m

    AHB I Control Signals

    50 m

    Clock Signals DDR Memory Controller APB Signals

    DDR Control Signals Address and Data Buss

    185 m 700 m

    50 m

    AHB II Control Signals


    Data Buffer (AHB II)

    155 m

    AHB II Read, Write and Address Buss


    50 m 35 m 630 m 700 m 20 m 15 m

    AHB Interface region

    2002-12-13

    17

    MO/EAB/RTN/D Magnus Sjlander

    Place & Route


    Data Buffer I ABH I

    Data AHB Buffer II II

    AHB Core AHB x2 APB Arbiter

    Refresh Initialization Current Address Next Address

    RW command Command Timing Open Banks Top Data Out

    2002-12-13

    18

    MO/EAB/RTN/D Magnus Sjlander

    Future Work
    Improved Refresh Handling Attempt to Reduce Initial Latency for Bursts Improved Buffer Handling

    2002-12-13

    19

    MO/EAB/RTN/D Magnus Sjlander

    Conclusion
    Working Implementation Smaller Changes to Improve Performance Highlights Difficulties and Solutions

    2002-12-13

    20

    MO/EAB/RTN/D Magnus Sjlander

    Questions ?

    2002-12-13

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