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Tutorial Sheet 5

1. The delay time for the output of a CMOS inverter to fall from 3.3V to 1.65V with an output load capacitance of 300 fF is calculated to be 0.15 microseconds. 2. For a CMOS inverter with VDD = 5V and a load capacitance of 1 pF, the fall time calculated using the average-current method and differential equation method is determined. 3. The channel widths Wn and Wp of the nMOS and pMOS transistors for a CMOS inverter are designed to meet propagation delay and falling delay specifications for VDD = 3V and a load capacitance of 300fF.

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32 views

Tutorial Sheet 5

1. The delay time for the output of a CMOS inverter to fall from 3.3V to 1.65V with an output load capacitance of 300 fF is calculated to be 0.15 microseconds. 2. For a CMOS inverter with VDD = 5V and a load capacitance of 1 pF, the fall time calculated using the average-current method and differential equation method is determined. 3. The channel widths Wn and Wp of the nMOS and pMOS transistors for a CMOS inverter are designed to meet propagation delay and falling delay specifications for VDD = 3V and a load capacitance of 300fF.

Uploaded by

Ashish Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Technology And Applications - 10B11EC612

Tutorial Sheet 5 1. Consider the CMOS inverter circuit with VDD = 3.3 V. The I-V characteristics of the nMOS transistor are specified as follows: when VGS = 3.3 V, the drain current reaches its saturation level IDSAT = 2 mA for VDS 2.5 V. Assume that the input signal applied to the gate is a step pulse that switches instantaneously from 0 V to 3.3 V. Using the data above, calculate the delay time necessary for the output to fall from its initial value of 3.3V to 1.65V, assuming an output load capacitance of 300 fF. 2. For the CMOS inverter with a power supply voltage of VDD = 5 V, determine the fall time tfall which is defined as the time elapsed between the time point at which Vout = VDD*90% = 4.5 V and the time point at which Vout = VDD *10% = 0.5 V. Use both the average-current method and the differential equation method for calculating tfall. Assume output load capacitance is 1 pF. The nMOS transistor parameters are given as nCox = 20 A/V2 (W/L)n = 10 Vt,n = 1.0 V 3. Consider a CMOS inverter, with the following device parameters: Vt0,n = 0.8 V Vt0,p= -1.0 V Wmin =1.2m Design this CMOS inverter by determining the channel widths Wn and Wp of the nMOS and pMOS transistors, to meet the following performance specifications. Vth = 1.5 V for VDD = 3 V Propagation delay times tPHL 0.2 ns and tPLH 0.15 ns, A falling delay of 0.35 ns for an output transition from 2 V to 0.5 V, Assuming a combined output load capacitance of 300fF and ideal step input.

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