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Design Rules: Jan M. Rabaey

The document discusses design rules for integrated circuits including minimum line widths, distances between layers, transistor layout rules, via and contact rules, select layer rules, and an example CMOS inverter layout.

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Saurabh Chakravarty
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
250 views9 pages

Design Rules: Jan M. Rabaey

The document discusses design rules for integrated circuits including minimum line widths, distances between layers, transistor layout rules, via and contact rules, select layer rules, and an example CMOS inverter layout.

Uploaded by

Saurabh Chakravarty
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design Rules

Jan M. Rabaey

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Cross-Section of CMOS Technology

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Design Rules
Interface between designer and process engineer l Guidelines for constructing process masks l Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)
l

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Process Layers


Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Intra-Layer Design Rules


Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
Metal2

Different Potential 9 Polysilicon 2 Metal1 3


4

Well

3
Digital Integrated Circuits Design Rules Prentice Hall 1995

Transistor Layout
Transistor

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Via s and Contacts


2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Select Layer
2 3 2 1 3 3 Select

Substrate
Digital Integrated Circuits Design Rules

Well
Prentice Hall 1995

CMOS Inverter Layout


GND In V DD A A

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A


Digital Integrated Circuits Design Rules Prentice Hall 1995

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