BEE Small Signl Model
BEE Small Signl Model
1. Bias amplifier in high-gain region Note that the source resistor RS and the load resistor RL are removed for determining the bias point; the small-signal source is ignored, as well. Use the load-line technique to find VBIAS = VBE and IC = ISUP. 2. Determine two-port model parameters
n n
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Common-Base Amplifier
Input current is applied to the emitter (with a bias current source) and the output current is taken from the collector
Use transconductance amplifier form for model (not mandatory) Rin = r, Rout = ro || roc, Gm = gm by inspection
Compare with CS amplifier inferior input resistance superior transconductance about the same output resistance (assuming ro dominates)
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Common-Collector Amplifier
n
Circuit configuration
Biasing: if transistor is on (i.e., not cutoff), then VBIAS - VOUT = 0.7 V. Plot --
Comparison with the CG stage: note the effect of the source resistance on the output resistance if RS is much greater than r, then the output resistance is approximately: Rout r oc [ r o ]
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Two-port model: presence of r makes the analysis more involved than for a common drain
Note 1: both the input and the output resistances depend on the load and source resistances, respectively (note typo in Fig. 8.47 in text) Note 2: this model is approximate and can give erroneous results for extremely low values of RL. However, it is very convenient for hand analysis.
Comparison with CD stage: CCs input resistance: high but not infinity CCs output resistance: generally lower (but watch out for large RS)
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(wait a minute ... where do we find IREF? Assume that one is available!)
2 W i D = I REF + i OUT Cox ( v OUT V Tn ) -----2 L n
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DC Voltage Sources
n
Define a series of bias voltages between the positive and the negative supply voltages.
I REF + i OUT v OUT = V Tn + ------------------------------W C ----- 2 L n ox If ID = 100 A, n = 50 AV-2, (W / L) = 20, VTn = 1 V, then VOUT = 1.45 V for IOUT = 0 A.
n
In practice, output currents are small (or zero), so that the DC bias voltages are set by IREF
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Output current is scaled from IREF by a geometrical ratio: 2 I REF W i OUT = i D 2 = ------ n C ox V Tn + ------------------------------- VTn 2 L 2 W ------ C 2 L 1 n ox ( W L ) 2 I OUT = ------------------- I REF ( W L ) 1
Intuitively, VREF is set by IREF and determines the output current of M2 I REF V REF = V Tn + ------------------------------= V GS 1 = VGS 2 W ----- n Cox 2 L 1 Substituting into the drain current of M2 (and neglecting (1 + nVDS2) term)
2 W C (V i OUT = i D 2 = ----- V Tn) 2 L 2 n ox GS 2
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In order to boost the source resistance, we can study our single-stage building blocks and recognize that a common-gate is attractive, due to its high output resistance
Combine output resistance with DC output current for approximate equivalent circuit ... actual iOUT vs. vOUT characteristics are those of M2 with VGS2 = VREF
Adapting the output resistance for a common gate amplifier, the cascode current source has a source resistance of r oc = ( 1 + g m 4 r o 2 ) r o 4 g m 4 r o 4 r o 2
The model is only valid for vDS = vOUT > vDS(SAT) = VGS - VTn
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n-channel current source sinks current to ground ... how do we source current from the positive supply? Answer: p-channel current sources...?
Ai = -1
By mixing n-channel and p-channel diode-connected devices, we can produce current sinks and sources from a reference current connected to VDD or ground.
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Frequency Response
Key concept: small-signal models for amplifiers are linear and therefore, cosines and sines are solutions of the linear differential equations which arise from R, C, and controlled source (e.g., Gm) networks.
The problem: finding the solutions to the differential equations is TEDIOUS and provides little insight into the behavior of the circuit!
vout(t) R C
1. EECS 20/120: periodic functions can be represented as sums of sinusoids functions at different frequencies. 2. The response of a circuit to a sinusoidal input signal, as a function of the frequency, leads to insights into the behavior of the circuit.
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Phasors
It is much more efficient to work with imaginary exponentials as representing the sinusoidal voltages and currents ... since these functions are solutions of linear differential equations and d- ( e j t ) = j ( e j t ) ---dt How to connect the exponential to the measured function v(t)? Conventionally, v(t) is the real part of the of the imaginary exponential v( t) = v cos ( t + ) Re ( ve
(j t + )
n
) = Re ( ve e
j j t
v(t ) Ve
jt
Ie
j t
j t j t d = C ( Ve ) = j CVe dt
where v is the amplitude and is the phase of the sinusoidal signal v(t). The phasor V is defined as the complex number
j
which implies that the ratio of the phasor voltage to the phasor current through a capacitor (the impedance) is
V = ve
V 1 Z(j ) = --- = ---------I jC Implication: the phasor current is linearly proportional to the phasor voltage, making it possible to solve circuits involving capacitors and inductors as rapidly as resistive networks ... as long as all signals are sinusoidal.
v(t) = Re ( Ve
j t
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Bode plots : magnitude and phase of the phasor ratio: Vout / Vin
Replacing the capacitor by its impedance, 1 / (jC), we can solve for the ratio of the phasors Vout / Vin
range of frequencies is very wide (DC to 1010 Hz, for some amplifiers) therefore, plot frequency axis on log scale range of magnitudes is also very wide: therefore, plot magnitude on log scale Convention: express the magnitude in decibels dB by
V out 1/j C ---------- = ------------------------V in R + 1/j C multiplying by jC/jC leads to V out 1 ---------- = ----------------------1 + j RC V in
Vout V out = 20 log ------------------V in dB V in phase is usually expressed in degrees (rather than radians): V out Im ( Vout V in ) ---------- = atan ----------------------------------V in Re ( Vout V in )
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* Examples:
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