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Module III

The document discusses two programmable peripheral interface chips: the 8255 and 8251. It provides details on the basic operation and mode definitions of the 8255. It also provides programming information for the 8251, including the mode register, command register, status register, and simple serial I/O procedures. Modes for both chips are described at a high level.

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37 views23 pages

Module III

The document discusses two programmable peripheral interface chips: the 8255 and 8251. It provides details on the basic operation and mode definitions of the 8255. It also provides programming information for the 8251, including the mode register, command register, status register, and simple serial I/O procedures. Modes for both chips are described at a high level.

Uploaded by

rafesh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Programmable Peripheral Interface 8255

8255 BASIC OPERATION

BASIC MODE DEFINITIONS AND BUS INTERFACE

MODE DEFINITION

Single Bit Set/Reset Feature

MODE 1 INPUT

MODE 1 OUTPUT

MODE 2 OUTPUT

Programmable Communication Interface 8251

Programming 8251
8251 mode register

Mode register

Number of Stop bits 00: 01: 10: 11: invalid 1 bit 1.5 bits 2 bits

Parity enable 0: disable 1: enable

Baud Rate Syn. Mode x1 clock x16 clock x64 clock

Parity 0: odd 1: even

00: 01: 10: Character length11: 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits

Programming 8251
8251 command register

EH

IR

RTS

ER SBRK RxE

DTR

TxE

command register

TxE: transmit enable DTR: data terminal ready RxE: receiver enable SBPRK: send break character ER: error reset RTS: request to send IR: internal reset EH: enter hunt mode

Programming 8251
8251 status register

DSR

SYNDET

FE

OE

PE

TxEMPTYRxRDY TxRDY

status register

TxRDY: RxRDY: TxEMPTY: PE: OE: FE: SYNDET: DSR:

transmit ready receiver ready transmitter empty parity error overrun error framing error sync. character detected data set ready

Simple Serial I/O Procedures


Read
start

Write
start

Check RxRDY Is it logic 1? Yes No

Check TxRDY Is it logic 1? Yes No

Read data register*


end * This clears RxRDY

Write data register*


end * This clears TxRDY

Mode 0

MODE 1 PROGRAMMABLE ONE SHOT

MODE 2

MODE 3

MODE 4

MODE 5

CONTROL WORD FORMAT

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