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Real Time Clock

This document describes a real time clock (RTC) program that uses a clock signal and reset signal to increment the values of six digit variables representing hours, minutes, and seconds over time. It uses these variable values to set the segments of seven-segment displays to display the current time. Each digit is multiplexed to a common seven-segment display by using a 3-bit counter to select which digit value drives the display outputs.

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Jostin Punnassery
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33 views

Real Time Clock

This document describes a real time clock (RTC) program that uses a clock signal and reset signal to increment the values of six digit variables representing hours, minutes, and seconds over time. It uses these variable values to set the segments of seven-segment displays to display the current time. Each digit is multiplexed to a common seven-segment display by using a 3-bit counter to select which digit value drives the display outputs.

Uploaded by

Jostin Punnassery
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PROGRAM

Real Time Clock:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rtc is
Port (clk : in std_logic;
rst : in std_logic;
sl
: out std_logic_vector(5 downto 0);
atoh : out std_logic_vector(7 downto 0));
end rtc;
architecture Behavioral of rtc is
signal sig2 : std_logic_vector(26 downto 0) := (others => '0');
signal sig3 : std_logic_vector(19 downto 0) := (others => '0');
begin
process(clk, rst)
variable ssdigit1, ssdigit2,
ssdigit3, ssdigit4,
ssdigit5, ssdigit6 : std_logic_vector(7 downto 0) := (others => '0');
variable digit1, digit2,
digit3, digit4,
digit5, digit6
: integer := 0;
begin
if (rst = '0') then
digit1 := 0;
digit2 := 0;
digit3 := 0;
digit4 := 0;
digit5 := 0;
digit6 := 0;
sig2 <= (others => '0');
sig3 <= (others => '0');
elsif rising_edge(clk) then
sig2 <= sig2 + 1;
case sig2(24 downto 23) is
when "00" =>
digit6 := digit6 + 1;
if (digit6 > 9) then

digit6 := 0;
digit5 := digit5 + 1;
if (digit5 > 5) then
digit5 := 0;
digit4 := digit4 + 1;
if (digit4 > 9) then
digit4 := 0;
digit3 := digit3 + 1;
if (digit3 > 5) then
digit2 := digit2 + 1;
digit3 := 0;
if (digit2 > 9) then
digit1 := digit1 + 1;
digit2 := 0;
if ((digit1 >= 2) and (digit2 >= 4)) then
digit1 := 0;
digit2 := 0;
end if;
end if;
end if;
end if;
end if;
end if;
sig2(24 downto 23) <= "01";
when "11" =>
if (sig2(22 downto 19) = "1001") then
sig2 <= (others => '0');
end if;
when others =>
end case;
sig3 <= sig3 + 1;
case sig3(17 downto 15) is
when "000" => sl <= "111110";
case digit1 is
when 0 => ssdigit1 := "00111111";
when 1 => ssdigit1 := "00000110";
when 2 => ssdigit1 := "01011011";
when others => ssdigit1 := "00000000";
end case;
atoh <= ssdigit1;
when "001" => sl <= "111101";
case digit2 is
when 0 => ssdigit2 := "00111111";

when 1 => ssdigit2 := "00000110";


when 2 => ssdigit2 := "01011011";
when 3 => ssdigit2 := "01001111";
when 4 => ssdigit2 := "01100110";
when 5 => ssdigit2 := "01101101";
when 6 => ssdigit2 := "01111101";
when 7 => ssdigit2 := "00000111";
when 8 => ssdigit2 := "01111111";
when 9 => ssdigit2 := "01101111";
when others => ssdigit2 := "00000000";
end case;
atoh <= ssdigit2;
when "011" => sl <= "111011";
case digit3 is
when 0 => ssdigit3 := "00111111";
when 1 => ssdigit3 := "00000110";
when 2 => ssdigit3 := "01011011";
when 3 => ssdigit3 := "01001111";
when 4 => ssdigit3 := "01100110";
when 5 => ssdigit3 := "01101101";
when others => ssdigit3 := "00000000";
end case;
atoh <= ssdigit3;
when "100" => sl <= "110111";
case digit4 is
when 0 => ssdigit4 := "00111111";
when 1 => ssdigit4 := "00000110";
when 2 => ssdigit4 := "01011011";
when 3 => ssdigit4 := "01001111";
when 4 => ssdigit4 := "01100110";
when 5 => ssdigit4 := "01101101";
when 6 => ssdigit4 := "01111101";
when 7 => ssdigit4 := "00000111";
when 8 => ssdigit4 := "01111111";
when 9 => ssdigit4 := "01101111";
when others => ssdigit4 := "00000000";
end case;
atoh <= ssdigit4;
when "110" => sl <= "101111";
case digit5 is
when 0 => ssdigit5 := "00111111";
when 1 => ssdigit5 := "00000110";
when 2 => ssdigit5 := "01011011";

when 3 => ssdigit5 := "01001111";


when 4 => ssdigit5 := "01100110";
when 5 => ssdigit5 := "01101101";
when others => ssdigit5 := "00000000";
end case;
atoh <= ssdigit5;
when "111" => sl <= "011111";
case digit6 is
when 0 => ssdigit6 := "00111111";
when 1 => ssdigit6 := "00000110";
when 2 => ssdigit6 := "01011011";
when 3 => ssdigit6 := "01001111";
when 4 => ssdigit6 := "01100110";
when 5 => ssdigit6 := "01101101";
when 6 => ssdigit6 := "01111101";
when 7 => ssdigit6 := "00000111";
when 8 => ssdigit6 := "01111111";
when 9 => ssdigit6 := "01101111";
when others => ssdigit6 := "00000000";
end case;
atoh <= ssdigit6;
when others => sl <= "111111";
end case;
end if;
end process;
end Behavioral;

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