Introduction to CMOS VLSI Design

Chapter 1: Circuits & Layout

Copyright@David Harris, 2004 Update by Li Chen, 2010

Outline
CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams

1: Circuits & Layout

CMOS VLSI Design

Slide 2

CMOS Gate Design

Activity: Sketch a CMOS NOT gate

1: Circuits & Layout

CMOS VLSI Design

Slide 3

CMOS Gate Design

Activity: Sketch a 4-input CMOS NAND gate

1: Circuits & Layout

CMOS VLSI Design

Slide 4

CMOS Gate Design

Activity: Sketch a 4-input CMOS NOR gate

A B C D Y

1: Circuits & Layout

CMOS VLSI Design

Slide 5

Complementary CMOS
Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network inputs a.k.a. static CMOS
pMOS pull-up network

output
nMOS pull-down network

Pull-up OFF Pull-down OFF Z (float) Pull-down ON 0

Pull-up ON 1 X (crowbar)

1: Circuits & Layout

CMOS VLSI Design

Slide 6

Series and Parallel

nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
a g1 g2 b (a) 0 0 b OFF a 0 0 b (b) b ON 0 1 b OFF a 0 1 b OFF a 1 0 b OFF a 1 0 b OFF a 1 1 b OFF a 1 1 b ON a a

a g1 g2

a g1 b (c) g2 0

a 0 b OFF 0

a 1 b ON 1

a 0 b ON 1

a 1 b ON

a g1 b (d) g2 0

a 0 b ON 0

a 1 b ON 1

a 0 b ON 1

a 1 b OFF

1: Circuits & Layout

CMOS VLSI Design

Slide 7

Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Y Requires parallel pMOS
A

Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

1: Circuits & Layout

CMOS VLSI Design

Slide 8

Compound Gates
Compound gates can do any inverting function Ex: Y = (A B) + (C D) (AND-AND-OR-INVERTER, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D

A (c) C A

B C

1: Circuits & Layout

CMOS VLSI Design

Slide 9

Example: O3AI
Y = (A + B + C) D

1: Circuits & Layout

CMOS VLSI Design

Slide 10

Example: O3AI
Y = (A + B + C) D

A B C D Y D A B C

1: Circuits & Layout

CMOS VLSI Design

Slide 11

Signal Strength
Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network

1: Circuits & Layout

CMOS VLSI Design

Slide 12

Pass Transistors
Transistors can be used as switches
g s d

g s d

1: Circuits & Layout

CMOS VLSI Design

Slide 13

Pass Transistors
Transistors can be used as switches
g s d s g=1 s g s s d g=1 s d g=0 d d 1 Input 0 g=0 g=0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0 strong 1

1: Circuits & Layout

CMOS VLSI Design

Slide 14

Transmission Gates
Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

1: Circuits & Layout

CMOS VLSI Design

Slide 15

Transmission Gates
Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
Input g a gb g a gb b a gb g b a gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Output

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

g b

1: Circuits & Layout

CMOS VLSI Design

Slide 16

Tristates
Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y

EN A Y

EN A EN Y

1: Circuits & Layout

CMOS VLSI Design

Slide 17

Tristates
Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1

EN A Y

EN A EN Y

1: Circuits & Layout

CMOS VLSI Design

Slide 18

Nonrestoring Tristate
Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

EN A EN
1: Circuits & Layout CMOS VLSI Design Slide 19

Tristate Inverter
Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A EN Y EN

1: Circuits & Layout

CMOS VLSI Design

Slide 20

Tristate Inverter
Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A A EN Y EN Y Y A

EN = 0 Y = 'Z'
1: Circuits & Layout

EN = 1 Y=A
Slide 21

CMOS VLSI Design

Multiplexers
2:1 multiplexer chooses between two inputs
S
S 0 0 1 1 D1 X X 0 1 D0 0 1 X X Y

D0 D1

0 Y 1

1: Circuits & Layout

CMOS VLSI Design

Slide 22

Multiplexers
2:1 multiplexer chooses between two inputs
S
S 0 0 1 1 D1 X X 0 1 D0 0 1 X X Y 0 1 0 1

D0 D1

0 Y 1

1: Circuits & Layout

CMOS VLSI Design

Slide 23

Gate-Level Mux Design

Y SD1 + SD0 (too many transistors) = How many transistors are needed?

1: Circuits & Layout

CMOS VLSI Design

Slide 24

Gate-Level Mux Design

Y SD1 + SD0 (too many transistors) = How many transistors are needed? 20
D1 S D0

D1 S D0
1: Circuits & Layout

4 2 4

2 4 2 2

CMOS VLSI Design

Slide 25

Transmission Gate Mux

Nonrestoring mux uses two transmission gates

1: Circuits & Layout

CMOS VLSI Design

Slide 26

Transmission Gate Mux

Nonrestoring mux uses two transmission gates Only 4 transistors

S D0 S D1 S
1: Circuits & Layout CMOS VLSI Design Slide 27

Inverting Mux
Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter
D0 S S S D1 Y S S S D1 D0 S D1 S Y D0 0 Y 1 S

1: Circuits & Layout

CMOS VLSI Design

Slide 28

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects

1: Circuits & Layout

CMOS VLSI Design

Slide 29

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0 Or four tristates
D0 S0 D0 D1 D2 D3 0 D1 1 0 Y 0 1 D3 1 D2 Y S1

1: Circuits & Layout

CMOS VLSI Design

Slide 30

D Latch
When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch

CLK D
Latch

CLK D

Q
Q

1: Circuits & Layout

CMOS VLSI Design

Slide 31

D Latch Design
Multiplexer chooses D or old Q
CLK D 1 0 CLK CLK Q Q D CLK Q Q

CLK

1: Circuits & Layout

CMOS VLSI Design

Slide 32

D Latch Operation
Q D Q D Q Q

CLK = 1

CLK = 0

CLK D Q
1: Circuits & Layout CMOS VLSI Design Slide 33

D Flip-flop
When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK

CLK
D

Flop

Q
Q

1: Circuits & Layout

CMOS VLSI Design

Slide 34

D Flip-flop Design
Built from master and slave D latches
CLK CLK D CLK
Latch

CLK QM Q CLK CLK

CLK QM
Latch

CLK

Q CLK CLK

1: Circuits & Layout

CMOS VLSI Design

Slide 35

D Flip-flop Operation
D QM Q CLK = 0

QM

CLK = 1

CLK D Q

1: Circuits & Layout

CMOS VLSI Design

Slide 36

Race Condition
Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition
CLK1 CLK1
Flop

CLK2 Q1
Flop

CLK2 Q2 Q1 Q2

1: Circuits & Layout

CMOS VLSI Design

Slide 37

Nonoverlapping Clocks
Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead
2 D 2 2 QM 1 1 1 Q

2 1 2

1: Circuits & Layout

CMOS VLSI Design

Slide 38

Gate Layout
Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

1: Circuits & Layout

CMOS VLSI Design

Slide 39

Example: Inverter

1: Circuits & Layout

CMOS VLSI Design

Slide 40

Example: NAND3
Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40

1: Circuits & Layout

CMOS VLSI Design

Slide 41

Stick Diagrams
Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

1: Circuits & Layout

CMOS VLSI Design

Slide 42

Wiring Tracks
A wiring track is the space required for a wire 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track

1: Circuits & Layout

CMOS VLSI Design

Slide 43

Well spacing
Wells must surround transistors by 6 Implies 12 between opposite transistor flavors Leaves room for one wire track

1: Circuits & Layout

CMOS VLSI Design

Slide 44

Area Estimation
Estimate area by counting wiring tracks Multiply by 8 to express in

1: Circuits & Layout

CMOS VLSI Design

Slide 45

Example: O3AI
Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )D

1: Circuits & Layout

CMOS VLSI Design

Slide 46

Example: O3AI
Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )D

1: Circuits & Layout

CMOS VLSI Design

Slide 47

Example: O3AI
Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )D

1: Circuits & Layout

CMOS VLSI Design

Slide 48