Analog Computer Manual

Analog Computi ng
Techni que
by Robert Paz
Chapter 1
Programming Principles and Techniques
1. Analog Computers and Si mulati on
An analog computer can be used to solve various types of problems. It solves them in an
analogous way (pun intended). Two problems or systems are considered analogous if
certain or all of their respective measurable quantities obey the same mathematical equations.
Most general purpose analog computers use an active electrical circuit as the analogous system
because it has no moving parts, a high speed of operation, good accuracy and a high degree of
versatility. Active electrical networks consisting of resistors, capacitors, and op amps
connected together are capable of simulating any linear system since the forward voltage

2 Anal og Computer Pr i nci pl es
transfer characteristics of these networks are analogous to the basic linear mathematical
operations encountered in the systems mathematical model. By using diode function
generators and special circuits which have non-linear voltage transfer characteristics, it is also
possible to simulate nonlinear systems.
The mathematical model of an analog computer programmed to simulate a specific physical
system is identical to the mathematical model of the system. The voltage transfer
characteristics of the electrical networks are analogous to the desired mathematical operations.
The input and output voltages (computer variables) are analogous to the corresponding
mathematical variables (problem variables) of the problem. Because of limitations of the
computer or its associated input/output equipment, it is usually necessary to change the scale
of the computer variables, thus forcing the values of a computer variable to differ from the
corresponding problem variable values. It is important to understand that an analog computer
solution is simply a voltage wave form whose time dependency is the same as that of the
desired variable.
The normal procedure for simulating a system starts with determining the mathematical model
describing the physical quantities of interest. An analog block diagram is made to relate the
sequence of mathematical operations and to aid in scaling the variables. From the analog
block diagram the electrical components are connected together (patched). The computer is
operated and the computer variables observed on a recorder or oscilloscope. Since the output
is a computer variable (voltage wave form) it is necessary to convert the output variable back
to the original problem variable.
2. Solvi ng Di fferenti al Equati ons wi th an Analog Computer.
A typical simulation of a physical system involves a mathematical model consisting of a set of
one or more differential equations and initial conditions on the variables. If the system is
linear, the differential equations are linear and the operations required are 1) summation, 2)
sign inversion, 3) multiplication by a constant, 4) integration and 5) differentiation. For
practical reasons, the integration operation is easier to implement than the differentiation
operation. The reason lies in the fact that computer signals are real voltages and, therefore,
are corrupted by noise to some extent. Since integration has a tendency to average out the
effects of noise (while differentiation will accentuate it), a more precise solution can be
obtained using integration techniques.
Each of these operations may be represented as shown in Figure 1.1 Actual realization of
these will be discussed in the next section.

Chapter 1. Pr ogr ammi ng Pr i nci pl es and Techni ques 3
x(t)
x(t)
1
Sign Inversion
(d)
x(t)
y(t) =
= y(0) +
0
x(t)dt
t
y(0)
Integration (c)
ax(t)
x(t)
a
Multipication by a Constant
(b)
+
+
y(t) =
= x
1
(t) x
2
(t) +x
3
(t)
Summation
(a)
x
1
(t)
x
2
(t)
x
3
(t)
Fi gure 1.1: Basi c Li near Operati ons
As an example, consider the computer solution of the differential equation

dy
dt
y y , ( ) 0 1 (1.1)
Since the analog computer solves the equivalent integral equation, we integrate both sides.

y t y y d
t
( ) ( ) ( ) . +
0
0
t t (1.2)
The definition of integration given in Figure 1.1 would represent equation (1.2) if the input
were the same as the output. This condition can be easily implemented by connecting the
input to the output as shown in Figure 1.2.
t
y(t) =
= y(0) +
0
y(t)dt
y(0)
Fi gure 1.2: Block Di agram Reali zati on of the I ntegral Equati on.
It is important to note that it is not necessary to know the input of the integrator in order to
solve equation (1), but only that the input must be equal to the output at all times. The idea of
feeding an unknown output back to the input to generate a solution is basic to analog

computer solution of differential equations. This is not unreasonable since the differential
equation determines the class of solutions, while the initial conditions determine the specific
solution.
A higher order linear differential equation may be handled by reducing it to a set of firstorder
equations and following a similar procedure. For example,

d y
dt
dy
dt
y y y
2
2
0 0 1 0 0 + + , ( ) , ( ) , (1.3)
may be turned into the set of equations

, ( ) x x x
1 2 1
0 1 (1.4a)

, ( ) x x x x
2 1 2 2
0 0 (1.4b)
where

x y
1
, and

x dy dt
2
. The equivalent integral forms are

x t x x d
t
1 1 2
0
0 ( ) ( ) ( ) +
t t , (1.5a)

x t x x x d
t
2 2 1 2
0
0 ( ) ( ) ( ) ( ) +
[ ]
t t t (1.5b)
Equations (1.5a) and (1.5b) may be implemented using the circuit shown in Figure 1.3.
x
1
(t)
x
1
(0)
(Equation 1.5b) (Equation 1.5a)
x
2
(0)
x
2
(t)
Fi gure 1.3: Ci rcui t Reali zati on of the Second Order Equati on.
3. Physi cal Reali zati on of Li near Operati ons on an Analog Computer.
In section 2, the differential equation was expressed in terms of a set of general mathematical
operation. No attempt was made to discuss how these operations were realized with physical

components. In this section, the basic linear operations of summation, multiplication by a
constant, and integration will be discussed. The operation of sign inversion will be inherent in
the summation and integration operations as a result of construction convenience and
versatility.
(a) The Operational Amplifier (Op Amp).
The operational amplifier is a high gain amplifier with a wide variety of applications. The
amplifier is usually described in terms of its gain, input impedance, output impedance,
bandwidth, and offset characteristics. An operational amplifier usually has two input
terminals. The two input terminals are marked with a (+) to indicate the noninverting input
and a () to indicate the inverting input. An equivalent circuit for an op amp and a standard
symbol are shown in Figure 1.4.
V
1
V
1
V
o
V
o
V
2
V
2
R
in
R
out
(a)
(b)
+
V
g
V
g
=A
v
(V
2
V
1
)
+
Fi gure 1.4: (a) The Ci rcui t Symbol for an Op Amp, (b) An Equi valent Op Amp
Ci rcui t.
(b) Summers and I nverters.
The electrical circuit whose transfer characteristics are analogous to the mathematical
operation of summation is shown in Figure 1.5 ( for an ninput summer). Applying Kirchoffs
current law at the summing junction gives

i i i i
n f a 1
+ + + ... (1.6)
or, in terms of voltages

V V
R
V V
R
V V
R
V
R
x n x
n
o x
f
x
in
1
1

+ + + ... . (1.7)
Note that since

V A V
o v x
, then equation (1.7) can be rewritten


V
R
V
R
V
R
V
A R
n
n
o
f
o
v
1
1
+ + + ... , (1.8)
where

1 1 1 1 1
1
R R R R R
n f in
+ + + + L . (1.9)
V
n
R
1
R
n
V
1
i
1
i
n
V
o
R
in
R
out
+
V
g
R
f i
f
Fi gure 1.5: Summi ng Ampli fi er
By isolating

V
o
, we obtain,

V
R
R
R
A R
V
R
R
R
A R
V
o
f
f
v
f
n
f
v
n

+
_
,
_
,
1
1
1 1
... . (1.10)
Since the op amp has a very high voltage gain (usually >10
5
), we assume that

A
v
. Thus,
equation (1.12) reduces to

V
R
R
V
R
R
V
o
f f
n
n

1
1
... . (1.10)
Usually, analog diagrams are given in terms of symbols which represent the electrical circuit.
For this weighted summation, the analog symbol is shown in Figure 1.6, and we have the
output equation

V K V K V
o n n

1 1
... , (1.11)
and


K
R
R
i n
i
f
i
, , , 1K . (1.12)

V
o
V
1
V
n
K
1
K
n
Fi gure 1.6: Wei ghted Summi ng Ampli fi er

Since the circuit in Figure 1.5 is to be implemented on the analog computer, it is essential that
the summing operation indicated by Figure 1.6 and equations (1.11) and (1.12) be understood
thoroughly.
Note that the inherent sign inversion is a result of the negative voltage gain of the op amp.
Thus, the inverter which inverts the sign of its input is a special case of the summer with only
one input and with

K
1
1 . The transfer characteristic is given by

V V
o

1
. (1.13)
1
10
1
10
1
V
o
V
1
V
2
V
3
V
4
Fi gure 1.7: Analog Di agram for Example 1.1.
Example 1.1: Determine the circuit to produce the output voltage given by

V V V V V
o
+ +
1 2 3 4
10 10 . (1.14)
Solution: An analog diagram (i.e. in terms of symbols) for equation (1.14) is given in Figure
1.7. The circuit diagram which must be patched on the analog computer to realize equation
(1.14) is shown in Figure 1.8.

50k
5k
5k
50k
50k
50k 50k
V
4
V
3
V
2
V
1
V
o
Fi gure 1.8: Electroni c Ci rcui t for Example 1.1.
In an actual amplifier, the output voltage will not be zero when

V
i
and

V
n
are zero. This
effect is called the offset and is usually measured as is shown in the drawing below. The value
of

V
os
required to reduce

V
o
to zero under the conditions shown is called the offset voltage.
Under the conditions shown (

V
o
0), the offset current,

I
os
,
is defined as

I I
x y

. Note
the termination attached to the noninverting input in Figure 1.9.
R
f
V
o
R
n
R
i
V
os
I
x
I
y

R
R R
R R
n
i f
i f
+
Fi gure 1.9: Op Amp Ci rcui t Showi ng the Offset Voltage
In an actual amplifier, the output voltage

V
o
is not normally zero when

V V
x y
. This effect is
often described in terms of the common mode gain (CMG) and the common mode rejection
ratio (CMRR). Measurement of the CMG and CMRR are illustrated in Figure 1.10.

CMRR
kV
V
o
CM
(1.15)

V
o
V
os
Fi gure 1.10: Op Amp Confi gurati on for Determi ni ng CMRR
Operational amplifiers come in many forms. As an example the characteristics of the A 709
( a simple integrated circuit amplifier) are given below.

A
v
45,000

V
os
1 mV (typical for

R
i
< 10k )

I
os
0.2A

R
in
100k

R
out
150
CMRR 90dB
(c) Multiplication by a Constant ; Reference Voltages.
The op amps on the Comdyna GP-6 computer are constructed with 5K and 50k resistors only.
Thus, in order to realize gains (constant multipliers) other than 1/10, 1 and 10, another
technique must be used. The coefficient potentiometer (pot) is a voltage divider which allows
the output voltage to be some fraction of the input voltage. A pot thus has a gain of less than
unity. The electrical circuit diagram and analog computer diagram are shown in Figure 1.11.
The transfer characteristic is given by

V V
o in
a a , . 0 1 (1.16)
V
o
=aV
in
V
o
V
in
V
in
(a)
(b)
a
a

Fi gure 1.11: (a) Ci rcui t Symbol, (b) Analog Computer Symbol for
Potenti ometer.
The gain a is always placed outside the pot with the inside reserved for a pot identification
number. A constant term in a differential equation is obtained by using a dc reference voltage
which is supplied on the computer. Its value is usually the range of the op amps. For the
GP-6, this is 10v. Note that the actual dials for the potentiometer are illustrated in Appendix
A.
Example 1.2: Determine the analog diagram and circuit to implement the equation

V V V
o
+ + 035 524 26
1 2
. . . . (1.17)
Solution: The analog diagram is given in Figure 1.12 and the electrical circuit in Figure 1.13. A
GP-6 wiring diagram is supplied in Figure 1.14 to illustrate the actual connections needed.
1
10
10
1
.350
.524
.260
V
o
V
1
V
2
Fi gure 1.12: Analog Di agram for Example 1.2.
.260
50k
5k
50k
5k
.524
.350
5k
5k
V
2
V
1
V
o
10
Fi gure 1.13: Ci rcui t Di agram for Example 1.2.

SJ
SJ
1
1
1
.1
.1
IC
B
.1B
1
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
2
1 2 3
+
+
COEFFICIENT POT
V1
V2
Fi gure 1.14: GP-6 Wi ri ng Di agram for Example 1.2.
(d) I ntegrators.
Integration is the most important operation available on the analog computer. In fact, analog
computers owe their existence to their ability to integrate rapidly. Integration is different from
inversion and summation because it is time dependent. Integration can be accomplished by
replacing the feedback resistor of the summer with a capacitor. The resulting electrical circuit
for an integrator is shown in Figure 1.15.
C
V
o
V
1
V
n
R
1
R
n
i
1
i
n
V
x
i
f
Fi gure 1.15: Electri cal Ci rcui t for an n- I nput I ntegrator.
Using the same procedure and approximations as used for the summer, the transfer
characteristic for the circuit of Figure 1.15 becomes


V t V
V
R C
V
R C
d
o o
n
n
t
( ) ( )
( )
...
( )
+ +
1
]
1
0
1
1
0
t t
t (1.17)
Again, there is a sign inversion in the integration operation as a result of the negative voltage
gain of the op amp. Note that summation and integration can be performed with a single
amplifier. The analog computer symbol for the integrator is shown in Figure 1.16.
Electronic Switch
V
n
V
1
V
o
V
o
(0)
K
n
K
1
Fi gure 1.16: Analog Computer Di agram for an I ntegrator.
The electronic switch terminal (ES) is used to control the operating modes of the integrator.
The normal modes of operation are the initial condition (IC) mode and the operate (OP)
mode. The IC mode allows the integrator capacitors to be charged to the initial values, while
the OP mode causes the solution to occur. This sequence is shown for the example in Figure
1.17. The switches for the IC, HD, OP, and RO are illustrated in Appendix A.
10v
10v
1 2
t
(a)
(b)
E.S. t =0
10V
+10V
1
V
o
V
o
Fi gure 1.17: (a) Analog Computer Di agram for Example 1.3, (b) Voltage Output
for Example 1.3.
The electronic switch is nothing more than a SPDT switch with one pole grounded. Control
of the electronic switch is made through a switch driver and logic circuits which are usually
controlled by the computer mode control switches on the front panel. It is important to note,
concerning the analog symbol for the integrator, that i)

V
o
( ) 0 must be applied to the IC

terminal to get

+V
o
( ) 0 at the output and ii) the electronic switch, ES, is usually implied and
not shown unless it is used in an unconventional manner.
Circuit diagrams for the integrator are shown in Figure 1.18. In the initial condition state,
illustrated by Figure 1.18a, the capacitor charges to

V
ic
which can be used to represent an
initial condition. When in the OP mode, the output of the system is the negative of the
integral of the input starting from the initial condition. The equivalent circuit under these
conditions is shown in Figure 1.18b. Note that the initial condition part of the circuit is
grounded.
R
R
C
+
V
o
V
ic
V
i
R
i
V
ic
R
R
C
V
o
V
ic
V
i
R
i
(a)
(b)
Fi gure 1.18. (a) I ntegrator Ci rcui t i n I C Mode, (b) I ntegrator Ci rcui t i n OP
Mode.
4. A Systemati c Procedure for Programmi ng Di fferenti al Equati ons
Although the procedure presented in Section 2 may be used to determine the analog diagram
of a linear differential equation, a more systematic version will be developed. This procedure
does not require that a first order integral equation be considered for each integrator, but
instead requires an equation for the highest order derivative. This equation will correspond to
Equation (1.4) in Section 2. There is no essential difference in the theory or results of the two
techniques. Only the steps required differ.
Consider, for purposes of illustration, the second order linear differential equation and initial
conditions,

d x
dt
dx
dt
x x x
2
2
05 4 0 0 0 1 + + . , ( ) , ( ) . (1.18)
If any derivative of a variable is known, then it may be integrated to obtain the variable. In the
case of Equation (18) if the second order derivative (d
2
x/dt
2
) were known, then it could be

integrated once to obtain the first order derivative (-dx/ dt) and a second time to obtain the
variable (x). Note that since the integrator has a sign inversion associated with it, the output
of every odd integration is negative. But Equation (1.18) gives the second order derivative in
terms of the lower ordered derivative. Thus,
(1) If

d x dt
2 2

is known,

dx dtand x may be obtained;
(2) If

dx dt and x are known,

d x dt
2 2
may be obtained.
This circular argument states that only the relationship between the inputs and outputs of the
integrators are known, not the actual values of the inputs and outputs. This should not seem
too strange since a differential equation represents only the class of solutions. The boundary
values or initial conditions are necessary to determine a particular solution. The initial
conditions have not yet been considered.
The programming procedure is then as follows:
(a) Assume that the highest order derivative (

d x dt
2 2
in this case) is known and generate all
lower order derivatives as shown in Figure 1.19. Note that the output should always be x, not
-x, since x is the desired solution.

1
x
x
1
x

Fi gure 1.19: Analog Ci rcui t for a Double I ntegrator
(b) Solve the differential equation for the input to the integrator string and form the indicated
sum.

d x
dt
dx
dt
x
2
2
05 4 + . (1.19)
(Dont forget that the summer also inverts!). See Figure 1.20.
1
1
1
4.0
x
.5
x
x
Fi gure 1.20: Generati ng the Second Deri vati ve.

(c) Combine the results of (a) and (b) using pots, summers and inverters where required. See
Figure 1.21.
(d) Add all the initial conditions. Recall that the applied initial condition should be the
negative of the integrator output at t =0. See Figure 1.21.
1
x
x
1
x
1
1
1
.4
1
-10v
.5
[x(0)]
[x(0)]

Fi gure 1.21: Analog Di agram for the Second-Order System.
Although Figure 1.21 is the final diagram, it is possible to remove the summer by recalling that
the integrator can also be a summer. Inverters must then be inserted or removed from each
feedback loop to take care of the sign inversion. Usually, the form which uses the least
number of elements (pots, amps, etc.) is the preferred form since the probability of a bad lead
or element in the patched problem is lessened. Figure 1.22 represents the same problem as
Figure 1.21, but with the summer removed. Figure 1.23 shows how Figure 1.22 would
actually be wired up on the GP-6.
1
x
x
1
1
1
.4
1
-10v
.5
.1
-10v

Fi gure 1.22: Alternate Di agram, wi th Reduced Number of OpAmps

SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
1 2
1
1
1
.1
SJ
5
1 2 3
7
+
+
COEFFICIENT POT
Fi gure 1.23:. GP-6 Wi ri ng Di agram for Fi gure 1.22
As another example, consider a general third order linear differential equation. The procedure
may be extended for a system of any order. We have

d x
dt
a
d x
dt
a
dx
dt
a x f t
o
3
3
2
2
2
1
+ + + ( ), (1.20)
with initial conditions

x x x x x x
o o o
( ) , ( ) ,( ) 0 0 0 . (1.21)
Using the procedure outlined above:
(a) Form the integrator string
x

x
x
x
1
1 1

Fi gure 1.24: A Thi rd-Order Stri ng of I ntegrators.
(b) Solve for the input to the integrator string and form the indicated sum.


+ +
d x
dt
a
d x
dt
a
dx
dt
a x f t
o
3
3
2
2
2
1
( ), (1.20)
1
1
1
f(t)
x
a
1
x
a
0
x
a
2
x
Fi gure 1.25: Generati ng the Thi rd Deri vati ve.
(c) Combine the results of (a) and (b).
(d) Add the initial conditions and remove the summer since one less amplifier is
required. The result is shown in Figure 1.26.
[x(0)]
1
x
1
1
1
1
1
1
f(t)
1
1
[x(0)]
x

x
x

a
2
a
1
a
0
[x(0)]
Fi gure 1.26: The General Thi rd-Order System.

5. Tri cks wi th Transfer Functi ons
Suppose we have the first-order transfer function

G s
Y s
U s
a
s b
a b ( )
( )
( )
, ,
+
< < 0 10 0 10
This can be drawn in either of the all-integrator diagrams shown in Figure 1.27.
y(t) u(t)
a
b
+

y(t)
u(t)
+

a
b

Fi gure 1.27: Equi valent All-I ntegrator Di agrams
Because the gains are of values less than 10, then nothing more than a 10x input is needed.
Example analog computer diagrams are shown for the two block diagrams as shown in Figure
1.28. We note that the analog computer does very well at implementing a first-order system.
10
10
u(t)
b/10
a/10

y(t)
10
10
u(t)
b/10
a/10

y(t)
(a) (b)
Fi gure 1.28: Analog Computer Fi rst Order Di agrams
Of the two circuits, both have advantages and disadvantages. The circuit (a) has the advantage
that the output comes directly from an op-amp, and can thus be used to drive another circuit.
This circuit is also good if an initial condition,

y( ) 0 , is given. It has the disadvantage that its
input has a pot before entering the op amp. Thus, this circuit will tend to load whatever signal
is driving it. The circuit (b) has the advantage that it does not load the circuit that is driving it,
but has a pot on the output, and is thus not very useful in driving another circuit. Both of
these circuits, however may be used in a higher-order transfer function realization. For
example, if a transfer function has simple real poles and the cascade factorization

G s
a
s p
a
s p
a
s p
n
n
( )
+
_
,
_
,
_
,
1
1
2
2
L
where all the coefficients are of magnitude less than 10, then these circuits may be simply
cascaded (put in series) to form the overall transfer function. Some suggestions to this
approach include
i) Using circuit (b) to implement the first (input) stage, and (a) as the output stage.
ii) Alternating circuits to combine coefficients and thus reduce the number of required
potentiometers.
iii) Using an additional inverter on the output if there are an odd number of poles.
If our transfer function has the partial fraction expansion


G s d
c
s p
c
s p
c
s p
n
n
( ) +
+
+
+
+ +
+
1
1
1
2
2
L
then we may implement this transfer function using the first-order circuits in parallel, with the
output of each entering into a summer. In this case, circuit (b) would be preferable to prevent
loading the input.

20 Anal og Computer Techni que
Chapter 2
Magnitude and Time Scaling Techniques
1. Scali ng
In the solution of the problems described in Chapter 1, no consideration was given to the
magnitudes of the problem variables nor to the time required for solving each problem.
Equipment constraints usually restrict the maximum voltage output of each amplifier to 10
volts. If the problem dictates a large voltage output, amplifier overload occurs and the
solution is invalid. For example, if the problem of calculating a rocket speed were solved on
the GP-6 computer, it would be impossible to relate 1 v on the computer to 1 ft/sec in the real
problem. However, the problem might be solved by relating 1 v on the computer to 1
mile/sec in the problem. We see that the problem must be magnitude scaled so that it will fit
the computer. Similarly, in the same problem an acceleration term might have a maximum
value of 1 ft./sec
2
. Using the basic unit of miles for length as determined for scaling the
velocity would give a voltage of approximately 0.002 v which corresponds to the acceleration
term. This signal is in the noise level of the computer and would yield erroneous results.
Thus, the sample solution of one basic change of units for the entire problem will not always
work. It is necessary to scale up some parts of a problem and scale down other parts.
Time scaling is needed, for example, when we wish to study a basic physical phenomenon
which evolves much faster or much slower than is convenient for the computer operator. If
we wish to study planetary motion, we will not have the time to wait for a complete period of
revolution about the sun. An actual time of one year may be represented by, say, 10 seconds
of computer time. There are other reasons for time scaling, some of which we shall discover
shortly.
2. Magni tude Scali ng Basi c Pri nci ples
Magnitude scaling is needed whenever a problem variable existing as an amplifier output
becomes so large that the amplifier overloads or when the problem variable becomes so small
that the amplifier output noise is the predominant output signal.
Example 2.1. Consider the following differential equation:

Chapter 2. Magni tude and Ti me Scal i ng Techni ques 21

dx
dt
x x + . , ( ) . 1 5 0 0 (2.1)

x
1
1
.5
-10v
.1
1
3
6
Fi gure 2.1: Analog Di agram for Example 2.1
To solve this problem, an analog diagram representing Equation (2.1) is drawn following the
procedures given in Chapter 1. After patching the analog diagram of Figure 2.1, a trial run on
the computer would yield an overload on amplifier 3. The reason is suggested by the
analytical solution of Equation (2.1),

x t e
t
( ) ( )
.
50 1
1
. (2.2)
x(t) volts
50
25
10
Amplier 3 overloads here.
Fi gure 2.2 Theoreti cal Output of the Ci rcui t of Example 2.1.
Clearly, the amplifier overloads because it cannot supply the 50 volts required by the problem.
The basic difficulty stems from the fact that 1 volt on the computer corresponds to 1 unit of
the problem variable (x). Thus, to avoid this difficulty, a different correspondence must be set
up to relate x to the computer voltage (v). Since the maximum value of v is 10 volts, let 5
units of x correspond to 1 volt of v (i.e. v =x/5). Then when x is 50, v will be 10 volts and
the amplifier will not overload. The basic idea to grasp is that the analog computer does not
solve Equation (2.1), but an analogous equation in volts. The analogous equation is


dv
dt
v v + . , ( ) . 1 1 0 0 (2.3)
where v = x/5. The solution of equation (2.3) is

v t e
t
( ) ( )
.
10 1
1
. (2.4)
3. Analog Voltages Normali zed to Uni ts
It is common practice in the literature to redefine the magnitudes of reference voltages and all
associated input and output voltages on an analog computer in terms of a quantity called the
analog unit or just the unit By definition, the maximum voltage obtainable on the
computer is one unit. Thus, for a +10 volt computer, 1 unit = 10 volts. Scaling problems in
terms of units makes the scaled analog diagram machine-independent (i.e. good for 100 v
machines as well as 10 v machines) and sometimes simplifies the scaling of non-linear
problems. In these notes most examples are done in terms of volts rather than units because
we feel this is somewhat simpler, and more intuitive in terms of the actual circuit.
4. A Systemati c Approach to Magni tude Scali ng
In light of the discussion given in Section 2, we can develop a systematic approach to
magnitude scaling. First, consider the example discussed in that section. A statement of the
problem would be: Construct a scaled analog diagram for Equation (2.1) which if patched,
will use the maximum range of the amplifier, but will not cause any amplifier overload.
STEP 1. Draw the unscaled analog diagram. Remember that + 10 volts is the maximum
reference available on the computer. See Figure 2.1 for this.
STEP 2. Estimate the maximum value of each variable appearing as an amplifier output.
Only the amplifier outputs need to be considered since all other elements have a gain which is
less than unity. In this case x(t) is the only amplifier output and its maximum value is known
to be 50. A discussion of methods for estimating maximum values of amplifier outputs will be
presented later.
STEP 3. Define a scaling relationship between each problem variable and the corresponding
computer variable and prepare a scaling table.
For example, if we know | x|
max
=100 ft. we can represent x on the analog computer as some
voltage, v
x
. The voltage, v
x
can vary from -10v to +10v to +10v whereas x can vary from -100

ft. to +100 ft. Therefore, let 10v represent 100 feet. Then 5 volts corresponds to 50 feet, -10
volts to -100 feet and zero volts to zero feet. Therefore, we may write

v
x
x

10
. (2.5)
We call the coefficient (
1
10
), the "level of x," and denote it by L
x
, so that (2.5) may be written
as

v L x
x x
. In general, we may choose

L x
x
10
max
. To achieve best accuracy on the
analog computer, we utilize the full voltage range of the computer. Therefore, 10 is always
used in the numerator of the level equation.
The value of a variable can be computed by reading the voltage of the scaled variable in a
simulation, and then dividing it by the level of that variable:

x v L
x x
.
The scaling table for this problem is shown below.
Problem
Variable
Estimated
Maximum Level
Computer
Variable I.C.
Scaled
I.C.
x 50 1/5 [x/5] 0 [0]
STEP 4. Write the scaled analog equations for each amplifier in terms of the computer
variables (amplifier outputs)defined in Step 3. No other variable should appear in these
equations.
Suppose we wish to find an analog simulation to convert feet to inches. Also suppose a
maximum of 5 ft. will be converted. Let

y
x

number of inches
number of feet
Then

y ax
where
a =12
Clearly we must scale the problem so that we can represent 60 inches, (y
max
), as an analog
voltage. We also know:


V L x V L y
x x y y
, , (2.6)
An analog simulation diagram is shown in Figure 2.3.
G
K
1
V
x
=L
x
x
V
y
=L
y
y
Fi gure 2.3: Scali ng Di agram
Pot #1 is set to some value which we denote by K. Electronically,
(Voltage Out) = (Overall Gain) (Voltage In),
or

L y K G V
y x
.
Substituting for the various voltages,

L y K G L x
y x
.
Therefore,

y
KGL
L
x
x
y
.
Since we must have

a
KGL
L
x
y
,
then Pot #1 must have the setting

K
aL
GL
y
x
. (2.7)
In our example, since

L L
y x

10
60
10
5
2
1
6
, and ,
then


K G
1 6
2
12
1
1 1
/
, . and
We could also have chosen K = .1, and G = 10. Equation (2.7) leads to the general
equation for setting pots:

K
Level Out
Level In
COEF
gain
| |
(2.8)
where
Level Out is the level of the variable immediately following the pot to be set.
Level In is the level of the variable preceding the pot.
COEF relates to the equation to be simulated.
gain is the gain of a summer, inverter or integrator following the pot.
Example 2.2. Simulate y = a x , where a =-3, | x|
max
= 20, and | y|
max
= 40.
Solution: L
x
= 1/2, L
y
= 1/4. A simulation diagram is shown in Figure 2.4.
G
K
1
4
y
x
2
Fi gure 2.4: Scali ng Di agram for Example 2.2.
Thus,

K
G G
_
,
_
,

1 4
1 2
3 15 /
/
.
.
If G were a gain of unity pot 1 would have to be set to 1.5 which is impossible. Therefore,
let G =10 and K =0.15. Finally, we have Figure 2.5.
4
y
x
2
10
.15
1
Fi gure 2.5: Scali ng Di agram for Example 2.2 wi th Gai n Values

Once the maximum values and the level constants have been determined we can define the
computer variables. Let v
x
denote the computer variable corresponding to the problem
variable x. We define,
v
x
= [L
x
x]. (2.9)
Analog Computer variables will always be bracketed in these notes.
Example 2.3. Again consider Equation (2.1). Solving for the derivative we obtain,

dx
dt
x x 5 1 0 0 . , ( ) . (2.10)
To get this equation in terms of the computer variable, multiply and divide each term by

1 L
x
,
which in this case is 5.

d
dt
x x
x
5
5
5 1
5
5
0 0
_
,
_
,
. , ( ) . (2.11)
Regroup the constants so that all variables are computer variables:

5
5
5 5
5 5
0 0
d
dt
x x x
1
]
1

1
]
1

1
]
1
. , ( ) , (2.12)
or

d
dt
x x x
5
1 1
5 5
0 0
1
]
1

1
]
1

1
]
1
. , ( ) . (2.13)
If other amplifiers were present, a similar procedure would be followed for each.
STEP 5. Draw the scaled analog diagram using the equations obtained in step 4. Label all
computer variables on the diagram. The final diagram should have the same form as the
unscaled diagram except for different pot values and amplifier gains. Thus, Equation (2.12)
results in Figure 2.6.


[x/5]
1
1
.1
-10v
.1
1
3
6
Fi gure 2.6: Scaled Di agram
The output of the analog diagram of Figure 2.6 is shown in Figure 2.7. It must be remembered
that [x/5] represents the analog variable in volts. To find the actual value of x, Equation (2.9)
must be used. At t
1
the value of the computer variable [x/5] is measured as 5 volts or 0.5 of a
unit, i.e.,

[ / ] , . x x 5 5 25 or
Constants are realized in analog simulations by patching a
10v reference to a pot set to some

value. To be consistent with the method of magnitude scaling, the pot setting must be found
by the same formula as before. For this purpose we suppose that the level of the 10v
reference is 10, which becomes the level in in the formula.
[x(t)/5] volts
10
5
t
1
Fi gure 2.7: Ti me Response for Example 2.3
When patching an initial condition, the gain is 1, the level is 10, and the level out is the level of
the variable for the initial condition. The coefficient is the value of the variable at t =0. The
following examples will help to illustrate these concepts and show how Equation (2.8) can be
used to find the pot settings.

5. Magni tude Scali ng a Second Order System
We begin this section with an example.
Example 2.4. Simulate the following system and magnitude scale so that no overload occurs
and maximum amplifier range is used.

d x
dt
dx
dt
x x x
2
2
8 25 500 0 40 0 150 + + , ( ) , ( ) (2.14)
and with

x x
max max
, 50 250.
STEP 1. Draw an unscaled analog diagram.

10

1
-1
+10V
+10V 10V
x
x
x
1
2
5
1
2
3
5
4
6
.8
.25
G
1
G
2
G
3
Fi gure 2.8: Unscaled Analog Di agram for Example 2.4.
STEP 2. This step is not necessary since the maximum values are already specified in the
problem statement.
STEP 3. Prepare a scaling table.
Problem
Variable
Estimated
Maximum Level
Computer
Variable IC
Scaled
IC
x
250 1/25

[ ]
x 25
-150 [-6]
x 50 1/5 [x/5] 40 [8]
-2.5 x 125 1/12.5 [-x/5] --- ---

STEP 4. Write the scaled equations for each amplifier. Here is where we illustrate the use of
Equation (2.8). Start with Figure 2.9.

G

x
5
x
25
1
2
1
Fi gure 2.9: Establi shi ng I ntegrator Outputs

K
G G
G
1
1 5
1 25
1 5
5 10

_
,
_
,

/
/
. , . when
Proceeding on, we complete the rest of the diagram,
x
5
x
5
x
25

1

10
-1
+10V
+10V 10V
x
1
2
5
1
2
3
5
4
6
G
1
G
2
G
3
Fi gure 2.10: The Fi nal Scali ng Process
and compute

K
G
G
K
G
G
K K
2
1
1
3
2
2
4 5
1 25
1 25
8
8 10
1 25
1 5
25
5 10
1 5
10
40
1
8
1 25
10
150
1
6
_
,
_
,
_
,
_
,
_
,
_
,
_
,
_
,

/
/
. ,
/
/
. ,
/
. ,
/
.
when
when
KK
G
G
6
3
3
1 25
10
500
2 10

_
,
_
,

/
. , , when

Note that on the Comdyna GP-6 computer resistor values of 5K and 50K and capacitors 2
fd and 20 fd are supplied with each integrator. Thus, any gain value between 0 and 100
may be obtained by proper choice of the input resistor-feedback capacitor combination and by
using a pot.
STEP 5. Draw the scaled analog computer diagram. A patch panel diagram is included in
Fig. 2.12.
10
10
10
.6
.8
.5
.8
.5
.2
x
5
x
5
x
25

1

10
-1
+10V
+10V 10V
x
1
2
5
1
2
3
5
4
6
Fi gure 2.11: A Fully Scaled Di agram
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
1 2
3 4
1
1
1
.1
SJ
5
1
1
1
.1
SJ
6
7 8
X Y
1 2 3
4 5 6
7
8
X Y
MULTIPLIERS
+ + +
COEFFICIENT POTENTIOMETERS
The GP-6 Anal og Computer Patch Panel
Fi gure 2.12: GP-6 Wi ri ng Di agram for the System of Example 2.4

Exampl e 2.5. As another example, magnitude-scale the following problem so that no
overload occurs and maximum amplifier range is used.

d x
dt
dx
dt
x x x
2
2
2 25 0 0 20 0 0 + + , ( ) ,( ) . (2.15)
This example will be worked by a short cut method. Estimated maximum values are,

x x 20 100 , . and (2.16)
Methods to obtain these estimates will be derived in Section 7 of this chapter. Solving for the
highest order derivative,

. x x x 25 2 (2.17)
The level constants are:

L L
x x

10
20
1 2
10
100
1 10 / , /
. (2.18)
Multiplying and dividing Equation (2.17) by the level constants, we obtain

( ) ( )
x
x x

1
]
1

1
]
1
25 2
2
2 10
10
, (2.19)
where

x x 2 10
[ ] [ ]
and are the computer variables. From the initial conditions we obtain,

x x
2
0 10
10
0 0
1
]
1

1
]
1
( ) ,
( ) . (2.20)
In order for

[ ]
x 10 to be the output of an amplifier,

x 10
[ ]
must be its input. Realizing
this, we divide Equation (2.17) by 10 to obtain,

x x x
10
5
2
2
10

1
]
1

1
]
1
. (2.21)
The magnitude-scaled analog computer simulation diagram appears in Figure 2.5.

10
10
.5
.2
.5
x
2
x
2
x
10

1

10
-1
0V 10V
x
1
2
5
3
1
2
Fi gure 2.13: Scaled Di agram for Example 2.5
NOTE: While setting pots in any circuit containing amplifiers, overloads may occur. The
reason for this is that in the POT SET mode of the computer 10 volts is internally applied to the
upper terminal of each potentiometer. If any amplifier has a gain 10 input it is likely to cause
an overload. These overleads can be avoided during the pot setting operation as follows.
Connect a wire between an output junction and the summing junction of each amplifier
output to vanish and solve the overload problem. DO NOT FORGET TO REMOVE THESE
SHORT CIRCUITS before attempting the problem solution. See Figure 2.14 for location of the
short.
SJ
SJ
IC
2
Fi gure 2.14: Short Ci rcui t for Setti ng Potenti ometers
6. Esti mati ng Maxi mum Values i n Fi rst Order Systems
Consider the first-order system

dx
dt
ax aK x x
o
+ , ( ) . 0 (2.22)

The solution of this differential equation is given by

x t e x K e
at at
( ) ( ) ( ) +

0 1 (2.23)
The solution, (2.23), is shown in Figure 2.15a, for 0 < K < x(0), and in Figure 2.15b, for 0
< x(0) < K. Graphing equation (2.23) for other possible combiniations of x(0) and K,
should convince the reader that

| | max{| ( )| ,| | }
max
x x K 0 (2.24)
x(t)
t
K
x(0)
x(t)
t
K
x(0)
(a)
(b)
Fi gure 2.15: Fi rst-Order Ti me Responses, (a) 0 <K <x(0), (b) 0 <x(0) <K
7. Esti mati ng Maxi mum Values i n the Second Order Homogeneous
Underdamped System.
We now consider the system

x x x
n n
+ + 2 0
2
zw w (2.25)
where the initial conditions x(0), and

( ) x 0 are given. We shall suppose that and
n
are
positive (for stability), and also that 0 < 1 (so that the system is underdamped). If =
0, (undamped), the solution of (2.25) is given by

x t x t
x
n
n
( ) ( ) sin
( )
+ +
( )
2
0
0
2
2
w
w q , (2.26)
where

q
w
_
,
tan
( )
( )
1
0
0
x
x
n
. (2.27)
Differentiating (2.26), we get


( ) ( ) cos
( )
x t x t
n
x
n
n
+ +
( )
w w q
w
2
0
0
2
2
. (2.28)
To obtain estimates of the maximum values, we note that when = 0, that

x
x
x x x
n
max
( )
max max
( ) , +
2
0
0
2
2
w
w (2.29)
If the system is underdamped, and <<1 Equations (31) and (32) give pretty good estimates
for the maximum values of | x| and | x
| . If 1, these estimates are conservative.

8. Esti mati ng Maxi mum Values i n the Forced Second Order Underdamped
System
We consider the system

( ), ( ) ( ) x x x u t x x
n n
+ + 2 0 0 0
2
zw w (2.30)
We shall make a rough estimate of the maximum values by assuming

u t Au t
s
( ) ( ) and =0.
The equation becomes

( ), ( ) ( ) x x Au t x x
n s
+ w
2
0 0 0 (2.30)
with the solution

x t t
A
n
n
( ) ( cos )
w
w
2
1 (2.31)
or, by a trig. identity,

x t t
A
n
n
( ) sin
( )
2
2
2
w
w (2.32)
Thus, from (2.32) and by differentiating (2.31), we obtain

x
A
x
A
n
n
max max
, ,
2
2
w w
(2.33)
and thus that

max
x A . These estimated maximum values will again be quite good if the
damping is low (

z 0), but will be conservative if the system is critically damped or
overdamped. How would you estimate max values if the initial conditions are not zero?

9. Ti me Scali ng
Analog simulations can be adjusted to run faster or slower than real time. The time relation is:

t b t , (2.34)
where

t b computer time, real time, scale factor t
A person can physically understand this equation and avoid confusion by remembering the
following sentence:
The computer runs

1 b times as fast as real time.
Time scaling can be achieved by multiplying the gains of each input of every integrator by 1/.
Therefore, we can adjust the previous pot setting formula to take care of magnitude and time
scaling. We simply use a single pot for each input to the integrators such that:

Pot Setting

_
,
_
,
_
,
L
L
COEF
gain
out
in
1
b
. (2.35)
where the 1/ factor is added to the formula only when the pot to be set is patched to the
input of an integrator.
NOTES:
1. There is no time variation on an initial condition, so the 1/ factor should be left
out of the formula to set I.C. pots.
2. There is likewise no time variation for a non-integrating amplifier. Therefore 1/
factor should also be omitted from the formula to set pots at inputs to such an
amplifier.
Example 2.6. Given:

, ( ) ( ) , . . x x x x x + + 10 25 20 0 0 0 25 b (2.36)
Using the results of section 8, we estimate

x
A
x
A
n
n
max max
, ,
2 40
25
20
5
4
2
w w
(2.33)


L L
x x
( ) . , . .
10
25
40
625
10
4
25
First, we draw the integrators.
1
2
1
G
[ 6.25 x ] [ 2.5 x ]
Fi gure 2.16: I ntegrator Di agram for Example 2.6

G
1
625
25
1
25
1

_
,
_
,
Pot Setting for #1

.
. .
.
Therefore, we may choose

G K
1 1
1 1 and . Note that pot #1 may actually be eliminated.
Now the feedback, I.C.s, and constants may be entered onto the diagram (Figure 2.17). Here,

G K G K
2 2 2 2
25
25
10
1
25
4 10 4

_
,
_
,

.
.
( )
.
, , . ,

G K G K
3 3 3 2
25
625
25
1
25
4 10 4

_
,
_
,

.
.
( )
.
, , . ,

G K G K
4 4 4 2
25
10
20
1
25
2 10 2

_
,
_
,

.
( )
.
, , . .

1
-1
+10V
1
2
5
2
3
4
1
G
1
G
2
G
3
K
4
K
2
K
3
[ 2.5x
]
[ 6.25x ]
[ 6.25x ]
Fi gure 2.17: Setti ng the Scali ng Values
Thus we have the final diagram

.2
.4
.4
10
10
10

1
-1
+10V
1
2
5
2
3
4
1 [ 2.5x
]
[ 6.25x ]
[ 6.25x ]
Fi gure 2.18: A Fully Ti me/ Ampli tude Scaled Di agram
10. Summary of Procedures for Developi ng a Scaled Analog Di agram
1. Write the differential equation to be solved in normal form.
2. Estimate maximum values for variables.
3. Determine all levels.
4. Draw all integrators needed. Put a pot between each pair of integrators and set them:

K
L
L gain
out
in
_
,
_
,
_
,
1 1
b
.
5. Fill in the feedback paths setting the pots by:

K
L
L
COEF
gain
out
in
_
,
_
,
_
,
1
b
.
6. Add I.C.'s, setting the pots by:

K
L COEF
out
_
,
_
,
10 1
.
7. Add constants, setting the pots by:

K
L COEF
gain
out
_
,
_
,
_
,
10
1
b
.

11. Repeti ti ve Operati on
At times it is desirable to repeat a solution many times in rapid succession, such as on an
oscilloscope. Without any storage capability, it would be difficult to see details of the solution
unless it is repeatedly swept across the screen at a rate that the eye would not be able to
distinguish each individual sweep. The repetitive operation (RO) mode is available on most
analog computers for this purpose. In order to repeat the solution it is necessary to backup in
time and then repeat the desired time interval. Thus, the time dependent elements
(integrators) must be controlled. Basically, when the computer is placed in the RO mode, the
integrators are internally placed in the IC state for a time period sufficient to charge the
capacitors to the initial condition value and then internally changed to the OP state for the
desired time interval. Then the procedure is repeated.
Repetitive operation requires that a computers integrator time constants be small
enough to permit a high rate of repetitive solutions. Also, a timing unit is required to
alternately place integrators in the IC and OP modes.
When the Mode selector is positioned to RO:
1. The repetitive operation timing unit provides a logic control that alternately changes
integrator modes from initial condition to operate, the length of operate time period
determined by the computer time setting.
2. The repetitive operation time unit provides a ramp output that may be used as the
readout displays time base.
3. High speed repetitive operation capacitors are the summer/integrator amplifiers
integration capacitors.
4. The meter input bus is connected to the rear terminal, meter input.
5. The high ends of all coefficient pots are connected to their patch panel
terminations.
The Comdyna GP-6 provides some special outputs to facilitate the use of an
oscilloscope or xy plotter as an output device both in slow time and repetitive operation.
In slow time mode, computer time and program time are the same. In the repetitive operation
mode, 1 second of computer time corresponds to 2.5 msec real time, a ratio of 400:1. The

computer time selector is calibrated in program seconds, and hence, a setting of 20 would
indicate 20 program seconds. To accurately set this variable output called CTP (compute time
period) has been provided on the x-address switch. This is displayed in the pot set mode by
setting the y/pot address to GND/ x and x to CTP. The DVM will display program
seconds/100 [i.e. .25 means 25 program seconds]. In both cases: during program operation,
setting the x address to TIME will produce a -10 to +10 ramp at the x output on the back of
the computer. This ramp can be used to drive the horizontal (or time) line of any desired
output device. Thus, a display controlled by the computer time base will show exactly the
same output display regardless of the mode of operation. This facility provides a means of
displaying a solution on an oscilloscope during the preliminary design phase.

Chapter 3
Simulation of Transfer Functions
1. Di fferenti al Equati ons and Transfer Functi ons.
The primary usefulness of the analog computer is for simulating systems which can be
modeled by a set of differential equations. A special case to be considered is the simulation of
a system described by a transfer function. A transfer function is the ratio of the Laplace
transform of the output variable to the Laplace transform of the input variable with all initial
conditions equal to zero. Consider a system which is modeled by the differential equation,

d x
dt
a
dx
dt
a x b u b
du
dt
o o
2
2
1 1
+ + + . (3.1)
Here,

x t ( ) is the system output and

u t ( ) is the input. (Note that for a transfer function, the
initial conditions are considered to be zero). Not only does the input appear, but a derivative
of the input is also present. The transfer function describing this equation may be found by
taking the Laplace transform of equation (3.1) and rearranging

s X s a sX s a X s b U s b sU s
o o
2
1 1
( ) ( ) ( ) ( ) ( ) + + + (3.2)
and factoring

( ) ( ) ( ) ( ) s a s a X s b b s U s
o o
2
1 1
+ + + (3.3)
yields

X s
U s
b s b
s a s a
o
o
( )
( )

+
+ +
1
2
1
. (3.4)
Thus, if the differential equation describing a system is given, the transfer function for that
system may be obtained. Also, given the transfer function (e.g. equation (3.4)), the differential
equation (3.1) may be obtained by cross multiplying, taking the inverse Laplace transform, and
rearranging.

Chapter 3. Si mul ati on of Tr ansf er Functi ons 41
Since a transfer function may be converted to a differential equation, then it seems possible to
simulate transfer functions. There are, however, two difficulties that arise. The first difficulty
is that the straight-forward implementation of some differential equations (such as in equation
(3.1)) require the input to be differentiated. This is a problem because the analog computer
does not have a differentiator, and because analog differentiators are inherintly noisy, high
bandwidth devices (unlike integration which is noise resistant).
The second difficulty arises because with a transfer function, usually only the input and the
output are available and of interest. Programming the transfer function does not usually result
in the intermediate derivatives, while programming the differential equation yields all the
intermediate derivatives. Since the intermediate derivatives are not of immediate interest and
programming the differential equation usually requires the use of more amplifiers,
programming the transfer function is preferred.
Transfer function simulation is particularly useful when a problem can be described in terms
of a block diagram. The transfer function representing each block can then be programmed
on the computer and each block connected with the other blocks as dictated by the block
diagram. In this way, the input and output of each block (transfer function) on the computer
can be related to a meaningful physical variable of the system.
2. Programmi ng Transfer Functi ons
The fundamental idea behind any kind of system programming on the analog computer is that
when initial conditions are zero at
t 0, the Laplace variable, s, corresponds to
differentiation in the time domain, and

1 s corresponds to an indefinite integration having
t 0 as its lower limit. Thus, if

l f t F s ( ) ( )
{ }
, then

l
df t
dt
sF s
( )
( )
{ }
, while

l f d
t
F s
s
( )
( )
t t
0
'
. (3.5)
There are many canonical (standard) ways of breaking up a transfer function to obtain an all
integrator realization. An allintegrator realization of a transfer function is a circuit that has
the given transfer function, but that uses only integrators as dynamic elements (no
differentiators). We will not concentrate on all the possible realization, but will focus on one
particular form.
3. The Di rect Programmi ng Techni que

This approach, also called the Solving for the Highest Derivative approach, is one of the
simplest, because it does not require knowledge of any of the system poles or zeros
*
. All the
examples of Chapter 2 used this approach. The difference between what is considered here,
and what was done in Chapter 2 is that it is possible for the transfer functions to have zeros.
(The examples in Chapter 2 had no zeros). We will explain this method by example. Suppose
we have the transfer function:

G s
Y s
U s
a s a s a
s b s b
N s
D s
o
o
( )
( )
( )
( )
( )
,
+ +
+ +
2
2
1
2
2
(3.6)
where

N s a s a s a D s s b s b
o o
( ) , ( ) . + + + +
2
2
1
2
2
(3.7)
This is illustrated in Figure 3.1.
U(s) Y(s)
G(s)
Fi gure 3.1: System Block Di agram
We decompose this system into two systems cascaded as in Figure 3.2.
U(s) Y(s)
X(s)
D(s)
N(s)
1
Fi gure 3.2: Cascaded Equi valent System
Notice that in cascading the two parts of the system, we have created the intermediate
variable,

X s ( ). The transfer function from

U s ( ) to

X s ( ) has no zeros, and thus may be
realized by using the approach of Chapter 2. Thus, we have

X s
U s
s b s b
s X s b X s b sX s U s
o
o
( )
( )
( ) ( ) ( ) ( )
+ +
+
1
2
1
2
1
. (3.8)
Note that in the Laplace domain,

s X s
2
( ) corresponds to the highest derivative of X. Thus,
this highest derivative is given in terms of lower powers of s times

X s ( ) plus the input.
Figure 3.3. shows the all-integrator diagram for this. Note that the time domain and the
Laplace domain variables are shown.
*
This approach gives rise to the controllable canonical form.


1
x
x

1 x
1
1
1
f(t)
b
1
b
0
1
X(s) s X(s)
s
2
X(s)
Fi gure 3.3: AllI ntegrator Di agram for the Fi rst Stage
The remaining tranfer function is given by

Y s
X s
N s a s a s a
o
( )
( )
( ) . + +
2
2
1
Multiplying through by

X s ( ), we obtain

Y s a s X s a sX s a X s
o
( ) ( ) ( ) ( ) + +
2
2
1
. (3.9)
It would appear that because of the s

X s ( ) term and the

s X s
2
( ) term, differentiators would
be needed to obtain the necessary signals. However, these signals appear naturally in the
realization of the transfer function from

U s ( ) to

X s ( ). Figure 3.4 illustrates the full integrator
diagram.
b
1
a
1
a
0
a
2
b
0
s
2
X(s)

1

1
1
1
1
F(s)
1
X(s)
s X(s)
1
1
1
s X(s)
Y(s)
Fi gure 3.4: Complete All-I ntegrator Di agram
From Figure 3.4, three observations may be made. The first is that the output is actually

Y s ( ). To obtain

+Y s ( ), it would be necessary to insert an inverter. The second
observation is the use of the use of the inverter that yields

sX s ( ). Since that signal was
already generated, it is certainly advantageous to use it than to insert another inverter to

generate the same signal. The third observation is that the summing inverter on the input
cannot be incorporated into the first integrator.
4. I ni ti al Condi ti ons
Suppose that we wish to simulate a transfer function, but with initial conditions included.
This is not a well-posed problem, as such, but we can work around that. Suppose that we are
given the transfer function (3.6), but with the initial conditions:

y y y y
o
( ) , ( ) . 0 0
1

(3.10)
In order to incorporate these initial conditions, we need to translate them into the initial
conditions of the actual integrators, and possibly the input.. We see, according to Figure 3.4,

y a x a x a x
a x a x a f b x b x
a a b x a a b x a f
o
o o
o o
( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
( ) ( ) ( )( ) ( )
0 0 0 0
0 0 0 0 0
0 0 0
1 2
1 2 1
2 1 2 1 2

'

+ +
+ +
+
(3.11)
and also that

( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
( ) ( ) ( )
(
y a x a x a x
a x a f b x b x
a f b x b x
b a a
o
o o
o
o
0 0 0 0
0 0 0 0
0 0 0
1 2
1 1
2 1
1

'

'
+ +
+
+

22 1 2 1 1 2 1
1 2 1 2
0 0
0 0
b x a a b b a a b x
a a b f a f
o o
) ( ) ( ) ( )
( ) ( )

( )

+
[ ]

(3.12)
We note that the initial states of the integrators can be rewritten in terms in the initial states of
y and

y, and upon the input and its derivative. Note that when we take the Laplace transform
of a signal, (like

f t ( )), we assume the signal to be zero, and all its derivatives to be zero.
Thus, (3.11) and ( 3.12) simplify down to

y a a b x a a b x
y b a a b x a a b b a a b x
o o
o o o
( ) ( ) ( ) ( )( )
( ) ( ) ( ) ( )
0 0 0
0 0 0
2 1 2 1
1 2 1 2 1 1 2 1

+

( )
+
[ ]
(3.13)
or


y a x a x
y a x a x
( ) ( ) ( )
( ) ( ) ( )
0 0 0
0 0 0
11 12
21 22

+
+
(3.14)
giving us two equations and two unknowns. Thus, we may solve for

x x ( ) ( ) 0 0

and in
terms of

y y ( ) ( ) 0 0

and . We write equations (3.14) as a single matrix equation:

y
y
a a
a a
x
x
x
x
a a
a a
y
y
( )
( )
( )
( )
( )
( )
( )
( )
0
0
0
0
0
0
0
0
11 12
21 22
11 12
21 22
1
1
]
1
1

1
]
1
1
]
1
1
1
]
1
1
1
]
1
1
]
1
1
(3.15)
and thus we obtain

x
y y
( )
( ) ( )
0
0 0
22 12
11 22 12 21
a a
a a a a
(3.17a)

( )
( ) ( )
x
y y
0
0 0
12 22
11 22 12 21
a a
a a a a
(3.17b)
5. Scali ng
The main difference between analog diagrams which simulate transfer functions and analog
diagrams which simulate differential equations is that the amplifier inputs of the former are not
simple derivatives, but are actually sums of problem variables. This makes scaling somewhat
more difficult, but recalling our scaling principles will always enable us to muddle through!

46 Appendi x A
APPENDIX A
1. The GP6 Di splay Panel
C
O
M
D
Y
N
A

G
P
6
Y
3
Y
4
X
1
X
2
O
V
L
D
1
2
3
4
5
6
R
O
O
P
H
D
I
C
8
7
6 5 4 3 2 1
Y
2
Y
1
X

A
D
D
R
E
S
S
Y
/
P
O
T

A
D
D
R
E
S
S
7 8 +

R
E
F

R
E
F
G
N
D
/
X
T
I
M
E
C
T
P
+

R
E
F

R
E
F
G
N
D
4
0
3
0
2
0
1
0
O
F
F
5
0
6
0
7
0
8
0
9
0
P
O
T

S
E
T
O
P
R
C
O
M
P
U
T
E

T
I
M
E
M
O
D
E

S
E
L
E
C
T
O
R
C
O
E
F
F
I
C
I
E
N
T

P
O
T
E
N
T
I
O
M
E
T
E
R
S
1
0
0
6 5 4 3 2 1
D
/
A
C
o
n
v
e
r
t
e
r
A
/
D
C
o
n
v
e
r
t
e
r
A
m
p
l
i
f
i
e
r
S
a
t
u
r
a
t
i
o
n
I
n
d
i
c
a
t
o
r
P
o
t
e
n
t
i
o
-
m
e
t
e
r
D
i
a
l
A
/
D

C
o
n
v
e
r
t
e
r
S
e
l
e
c
t
o
r
M
o
d
e
S
e
l
e
c
t
o
r

S
w
i
t
c
h
e
s
O
n
I
n
d
i
c
a
t
o
r

Appendi x A 47
2. The GP6 Patch Panel
S
J
S
J
1 1
1
.
1
.
1
I
C
B
.
1
B
S
W
O
P
S
J
S
J
1 1
1
.
1
.
1
I
C
B
.
1
B
S
W
O
P
S
J
S
J
1 1
1
.
1
.
1
I
C
B
.
1
B
S
W
O
P
S
J
S
J
1 1
1
.
1
.
1
I
C
B
.
1
B
S
W
O
P
1
2
3
4
1 1
1
.
1
S
J
5
.
1 1
1
.
1
S
J
6
7
8
X
Y
1
2
3
4
5
6
7
8
X
Y
M
U
L
T
I
P
L
I
E
R
S
+
C
O
E
F
F
I
C
I
E
N
T

P
O
T
E
N
T
I
O
M
E
T
E
R
S

48 Appendi x A
3. Patch Panel Components.
Patch panel graphics represent networks as they are applied in normal analog computer
programming. Amplifiers 1 thru 6 may be used as summers or high gain operational
amplifiers; amplifiers 1 thru 4 have electronic switch networks and may also be programmed
as integrators. Amplifiers 7 and 8 are exclusively inverters. Potentiometers 1 thru 6 are
attenuators. Potentiometers 7 and 8 have their bottom ends open and may be used as voltage
dividers or attenuators. Multiplier networks have current output; with one amplifier each may
be used as a multiplier, divider, squarer or squareroot extractor.
The following is a description of patch panel symbols:
SYMBOL DESCRI PTI ON
Positive reference, considered unity for normalized
programming. (Actual amplitude is 10 volts).
Negative reference,
(Actual amplitude is 10 volts).
5
High gain operational amplifier
1
High gain operational amplifier
with electronic switch
7
Inverter
SJ
The summing junction for amplifiers 1 thru 6. (Active for
amplifiers 1 thru 4 when a logic 1 is applied to the SW
switch control jack or when there is no switch control
patching.)
SJ
Alternate summing junction for amplifiers 1 thru 4. (Active
when a logic 0 is applied to the SW switch control jack).
1
Standard input summing resistor, normalized to a unity value
to simplify programming. (Actual value is 50 k)
.1
Summing input resistor that has a value one tenth the
standard (Actual value is 50 k)
B
Standard integrating capacitor input, normalized so that the 1
resistor and the B capacitor combination produces a one
second time constant as referred to programming time scales.
(Actual value is 20 fd in the slow time mode and .05 fd in
the repetitive operation mode.)
.1B
Integrating capacitor input that has a value one tenth the
standard (Actual value is 2 fd in the slow time mode and
.005 fd in the repetitive operation mode.)

Appendi x A 49
SJ
IC
Resistor input to the SJ summing junction. Amplifier
becomes an inverter when SJ is active. Normally used for
integrator initial conditions. Input and feedback resistors
may be used for summer operations. Input and feedback
resistors may be used for summer operation by patching SJ
to SJ. (Actual value of input and feedback resistor is 50 k)
Attenuator, with input and wiper indicated by standard
electrical symbol.
Voltage divider; top, bottom and wiper indicated by standard
electrical symbol. Bottom must be patched to ground for
attenuator operation. (Potentiometer value is 5 k)
System Ground.
X Y Multiplier network. Produces a current proportional to the
product of the inputs X and Y; normalized so that when
connected to the summing junction of an operational
amplifier with a 1 resistor feedback, and with reference
applied to X and Y, the amplifier output equals the
reference.
SW
Electronic switch control input. With a logic 0 (ground, or
positive voltage) the SJ summing junction of the above
amplifier is active and SJ shuts off. With a logic 1 (5 thru
15 volts) SJ is active and SJ shuts off, the SJ summing
junction is active but the summing resistor network is
disconnected. HD logic is used for normal integrator hold
mode operation.
OP
The computers operate bus; provides integrator mode logic
(slow time, repetitive operation or slave) as selected by the
operator. Normal integrator operation requires that the OP
bus be patched to the SW switch control input.

50 Appendi x B
APPENDIX B: WI RI NG BASI C LI NEAR COMPONENTS
FUNCTI ON OPERATI ON PATCHI NG
Summer
Amplifiers 1 4
1
1
10
10
A
B
C
D
V
o

V A B C D
o
= + + + ( ) 10 10
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
1
B
C
D
A
V
o
Summer
Amplifiers 5 &
6
.1
A
B
C
.1
.1
V
o

V A B C
o
= + + . ( ) 1
1
1
1
.1
SJ
5
A
C
B V
o
Attenuator
Pots 1 6
A
K
V
o

V KA K
o
= , . 0 1
A
V
o
Attenuator
Pots 7 & 8
A
K
V
o

V KA K
o
= , . 0 1
7
A
V
o

Appendi x B 51
FUNCTI ON OPERATI ON PATCHI NG
Voltage Divider
Pots 7 & 8
A
B
K
V
o

V KA K B
o
= +
( )
1
7
A
B
V
o
Inverter
Amplifiers 7 &
8
A
1 V
o

V A
o
=
7 A
V
o
Integrator
Amplifiers 1 4

1
1
B
A
F
C
D
E
10
10
1
V
o

V A B C D E F d
o
t
= + + + +
( )
10 10
0
t
SJ
SJ
1
1
1
.1
.1
IC
B
.1B
SW OP
1
B
C
D
E
F
A
V
o

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Analog Computi ng

Fi gure 1.6: Wei ghted Summi ng Ampli fi er

Fi gure 1.26: The General Thi rd-Order System.

10v reference to a pot set to some

| . If 1, these estimates are conservative.

Fi gure 2.16: I ntegrator Di agram for Example 2.6

Pot Setting for #1

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