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Why Nmos Pass Strong Zero 1826

MOS transistors can act as switches, with nMOS transistors conducting when the gate is high and pMOS transistors conducting when the gate is low. Basic logic gates like NAND and NOR can be constructed from networks of nMOS and pMOS transistors. However, nMOS networks alone do not make strong logic signals due to the voltage threshold drop across transistors. Transmission gates that use complementary nMOS and pMOS pairs allow both strong 1s and 0s to pass.

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Nitin Kala
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425 views9 pages

Why Nmos Pass Strong Zero 1826

MOS transistors can act as switches, with nMOS transistors conducting when the gate is high and pMOS transistors conducting when the gate is low. Basic logic gates like NAND and NOR can be constructed from networks of nMOS and pMOS transistors. However, nMOS networks alone do not make strong logic signals due to the voltage threshold drop across transistors. Transmission gates that use complementary nMOS and pMOS pairs allow both strong 1s and 0s to pass.

Uploaded by

Nitin Kala
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE 4253/6253 Lecture Notes

August 25, 1998

page 1

MOS Transistors as Switches


G (gate) D (drain) S (source) nMOS transistor: Closed (conducting) when Gate = 1 (Vdd, 5V) Open (non-conducting) when Gate = 0 (ground, 0V)

pMOS transistor: Closed (conducting) when Gate = 0 (ground, 0V) D Open (non-conducting) when Gate = 1 (Vdd, 5V)

For n MOS switch, source is typically tied to ground and is used to pull-down signals:
Out when Gate = 1, Out = 0, (OV) G S when Gate = 0, Out = Z (high impedance)

For pMOS switch, source is typically tied to Vdd, used to pull signals up:
S G Out

when Gate = 0, Out = 1 (Vdd) when Gate = 1, Out = Z (high impedance)

Note: The MOS transistor is a symmetric device. This means that the drain and source terminals are interchangeable. For a conducting nMOS transistor, VDS > 0V; for the pMOS transistor, VDS < 0V (or VSD > 0V).

EE 4253/6253 Lecture Notes

August 25, 1998

page 2

The CMOS Inverter


Truth Table Vdd I 0 1 I Out I Out Out 1 0

Rin GND

Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no current path between Vdd and GND exists (the output is usually tied to the gate of another MOS transistor which has a very high input impedance). Power is dissipated as "I" transistions from 0 1 and 1 0 and a momentory current path exists between Vdd and GND. Power is also dissipated in the charging and discharging of gate capacitances.

EE 4253/6253 Lecture Notes

August 25, 1998

page 3

Parallel Connection of Switches


Y Y = 0, if A or B = 1 A B A+B

Y = 1 if A or B = 0 A B A+B Y

Series Connection of Switches


Y A

Y = 0, if A and B = 1

A B

Y = 1, if A and B = 0

B Y

A B

EE 4253/6253 Lecture Notes

August 25, 1998

page 4

NAND Gate Design


p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table (NAND): AB 00 01 10 11 1 1 1 0

K-map (NAND):
A B 0 1 0 1 1 1 1 0

NAND circuit example:


Vdd

Ptree = A + B Ntree = A B Y B A B Y

EE 4253/6253 Lecture Notes

August 25, 1998

page 5

NOR Gate Design


p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table: AB 00 01 10 11 1 0 0 0

K-map:
A B 0 1 0 1 0 1 0 0

NOR circuit example:


Vdd

A Ptree = A B Ntree = A + B B Y

A B

EE 4253/6253 Lecture Notes

August 25, 1998

page 6

What logic gate is this?


Vdd

A Y = 1 when A B Y = 0 when A + B B Y

Answer: AND function, but poor design! Why? nMOS switches cannot pass a logic "1" without a threshold voltage (VT) drop. where VT = 0.7V to 1.0V (i.e.,
VDD G VDD D S VDD - VT

threshold voltage will vary) output voltage = 4.3V to 4.0V, a weak "1"

EE 4253/6253 Lecture Notes

August 25, 1998

page 7

The nMOS transistor will stop conducting if VGS < VT. Let VT = 0.7V,
G 5V S D 0V 5V D ? 0V ?

As source goes from 0V 5V, VGS goes from 5V 0V. When VS > 4.3V, then VGS < VT, so switch stops conducting. VD left at 5V - VT = 5V - 0.7V = 4.3V or Vdd - VT.

What about nMOS in series?


5V 5V 5V 5V

0V 5V

0V 4.3V

0V 4.3V

0V 4.3V

0V Vdd - VT 5V - 0.7V 4.3V

Only one threshold voltage drop across series of nMOS transistors

EE 4253/6253 Lecture Notes

August 25, 1998

page 8

For pMOS transistor, VT is negative. pMOS transistor will conduct if |VGS| > |VTp| (VSG > |VTp|), or VGS < VTp
0V G 5V S D

VTp = -0.7V VGS = 0V - 5V = -5V

conducting

VGS < VTp or |VGS| > |VTp| -5V < -0.7V 5V > 0.7V

How will pMOS pass a "0"? When |VGS| < |VTp|, stop conducting
G 0V 5V 0V S D 5V ? D ?

So when |VGS | < |-0.7V|, VD will go from 5V 0.7V , a weak "0"

How are both a strong "1" and a strong "0" passed? Transmission gate pass transistor configuration

When I = 1,
A B

B = strong 1, if A = 1; B = strong 0, if A = 0

When I = 0, non-conducting

EE 4253/6253 Lecture Notes

August 25, 1998

page 9

About that AND Gate...


Vdd No!!! Poorly designed AND (circuit designer fired) B Y

Instead use this,


A B Y Vdd

Y B

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