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Testing & Verification of VLSI Circuits Assignment No. 2: Unit 4

The document outlines assignment questions for a course on testing and verification of VLSI circuits. It contains 16 questions across 6 units. The questions cover topics like ad-hoc DFT methods, scan design rules, signature registers, BIST for RAM, BILBO, boundary scan architecture, TAP controller state diagram, fault dictionary diagnosis, diagnostic trees, test wrappers, system-on-chip test architecture, binary decision trees, random pattern generation, Roth's D-algorithm, asynchronous circuit test generation, and complexity of testing sequential vs combinational logic.

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89 views2 pages

Testing & Verification of VLSI Circuits Assignment No. 2: Unit 4

The document outlines assignment questions for a course on testing and verification of VLSI circuits. It contains 16 questions across 6 units. The questions cover topics like ad-hoc DFT methods, scan design rules, signature registers, BIST for RAM, BILBO, boundary scan architecture, TAP controller state diagram, fault dictionary diagnosis, diagnostic trees, test wrappers, system-on-chip test architecture, binary decision trees, random pattern generation, Roth's D-algorithm, asynchronous circuit test generation, and complexity of testing sequential vs combinational logic.

Uploaded by

bushra_shakeel_1
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Testing & Verification of VLSI Circuits Assignment No.

2
UNIT 4
Q. 1 Q. 2 Q. 3 Q. 4 Q. 5 Q. 6 Explain various design practices for Ad-Hoc DFT methods. Explain various scan design rules. What is signature register? Explain BIST for RAM with signature register How Built-in Logic Block Observation (BILBO) can be used as PRPG as well as MISR? Explain with neat diagram. Describe boundary scan architecture with the help of neat diagram. Explain TAP controller with the help of state diagram.

UNIT 5
Q. 7 How you will diagnose the following circuit using fault dictionary? Describe.

Q. 8

How you will diagnose the following circuit using diagnostic tree? Describe.

Q. 9 Q. 10 Q. 11 Q. 12

What is core? Explain test-wrapper with the help of block diagram. Draw and explain test architecture for SoC . Explain the steps carried out for test design of the system.

UNIT 6
For the circuit shown in figure, draw the binary decision tree and binary decision diagram and explain both in brief.

Q. 13 Q. 14 Q. 15 Q. 16

Explain Random Pattern Generation method with the help of flow chart. Describe Roths D-Algorithm in brief by listing all definitions (steps). Draw a test generation model for asynchronous circuits and explain it. Why testing sequential logic is more complex than that of combinational logic? Justify.

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