VHDL Programming Styles

1.

Structural
- define explicit components and the connections between them - like a text version of a schematic

2.

Data Flow
-assign expressions to signals -can include when and select statements

3.

Behavioural/Algorithmic
- write an algorithm that describes the circuits output - may not be synthesizable - may lead to a very large inefficient circuit

2 to 4 decoder
EN IN1 IN0 Y3 Y2 Y1 Y0 IN0 Y0

IN1

Y1

Y2

Y3 EN

-- 2 to 4 decoder, structural style; library IEEE; use IEEE.std_logic_1164.all; entity dec2to4 is port ( IN0, IN1, EN Y0, Y1, Y2, Y3 end entity dec2to4;

DO NOT USE AT THE GATE LEVEL

: in std_logic; -- 2 bit coded input plus enable; : out std_logic); -- 4 bit decoded output

architecture dec2to4_s of dec2to4 is signal IN0_L, IN1_L : std_logic; Begin U1: inv port map (IN0_L, IN0); U2: inv port map (IN1_L, IN1); U3: and3 port map (Y0, IN0_L, IN1_L, EN); U4: and3 port map (Y1, IN0, IN1_L, EN); U5: and3 port map (Y2, IN0_L, IN1, EN); U6: and3 port map (Y3, IN0, IN1, EN); end architecture dec2to4_s;

Will not work in Quartus but you will see this in generic VHDL texts.

-- 2 to 4 decoder, dataflow style -- 2 bit coded input plus enable; 4 bit decoded output -- if EN is 0, then output is 0000, else if EN is 1 -Input Output -00 0001 -01 0010 -10 0100 -11 1000 library IEEE; use IEEE.std_logic_1164.all; entity dec2to4 is port ( IN0, IN1, EN Y0, Y1, Y2, Y3 end entity dec2to4;

: in std_logic; : out std_logic);

architecture dec2to4_df of dec2to4 is begin Y0 <= not IN0 and not IN1 and EN; Y1 <= IN0 and not IN1 and EN; Y2 <= not IN0 and IN1 and EN; Y3 <= IN0 and IN1 and EN; end architecture dec2to4_df;

Selected signal assignment

signal assigned one of several values based on a selection criterion

WITH expression SELECT signal_name <= expression WHEN constant value, expression WHEN constant value;

when clause must be included for every possible value of the selection signal since std_logic signal values include Z, U, -, etc, use keyword OTHERS to account for non-listed cases

-- 2 to 4 decoder, behavioural style -- using selected signal assignment library IEEE; use IEEE.std_logic_1164.all; entity dec2to4 is port ( IN0, IN1, EN Y end entity dec2to4;

: in std_logic; : out std_logic_vector (3 downto 0));

architecture dec2to4_b of dec2to4 is signal ENA : std_logic_vector (2 downto 0); begin ENA <= EN & IN1 & IN0; -- concatenate inputs with ENA select Y <= "0001" when "100", "0010" when "101", "0100" when "110", "1000" when "111", "0000" when others; end architecture dec2to4_b;

Process looks like software programming

in architecture body encloses a set of sequential statements (everything else is concurrent) if, case, and loop constructs can only appear inside a process

Process syntax
[process_label:] PROCESS (sensitivity list) variable declarations BEGIN simple signal assignments variable assignments IF CASE LOOP END PROCESS [process_label];

IF
IF condition THEN ; ELSE ; END IF; IF condition1 THEN ; ELSIF condition2 THEN ; ELSE ; END IF;

CASE
CASE expression IS WHEN constant value1 => statement; ; WHEN constant value2 => statement; ; END CASE; when clauses must cover all the cases; can use OTHERS

-- 2 to 4 decoder, behavioural style; uses process; same library and entity

architecture dec2to4_b2 of dec2to4 is signal Inputs : std_logic_vector (1 downto 0); begin Inputs <= IN1 & IN0; process (Inputs,EN) begin if EN = '1' then case Inputs is when "00" => Y <= "0001"; when "01" => Y <= "0010"; when "10" => Y <= "0100"; when "11" => Y <= "1000"; when others => Y <= "0000"; end case; else Y <= "0000"; end if; end process; end architecture dec2to4_b2;

case Inputs is when "00" => Y <= "0001"; when "01" => Y <= "0010"; when "10" => Y <= "0100"; when "11" => Y <= "1000"; when others => Y <= "0000"; end case;

Process operation recap

when there is a change in the value of any signal in the process sensitivity list, process becomes active once active, statements in process are evaluated sequentially any assignments in the process are not visible outside the process until all statements have been evaluated

Revisit two vats & a buzzer

library ieee; use ieee.std_logic_1164.all;
vat 0
>30C >25C low level >30C >25C low level

entity vat_buzzer is port (v0over25, v0over30, v0low, v1over25, v1over30, v1low, sel : in std_logic; buzzer : out std_logic ); end entity vat_buzzer;

0 1

buzzer

+V

vat 1

select vat 1 select vat 0

architecture alternate of vat_buzzer is begin buzzer <= v0low or (v0over30 or not v0over25) when sel = 0' else v1low or (v1over30 or not v1over25); end architecture behavior;