VHDL Tutorial

What does HDL stand for?

HDL is short for Hardware Description Language

(VHDL VHSIC Hardware Description Language) (Very High Speed Integrated Circuit)

Why use an HDL?

Question: How do we know that we have not made a mistake when we manually draw a schematic and connect components to implement a function?
Answer: By describing the design in a high-level (=easy to understand) language, we can simulate our design before we manufacture it. This allows us to catch design errors, i.e., that the design does not work as we thought it would. Simulation guarantees that the design behaves as it should.

How does the simulation work?

What is the output of C?

The two-phase simulation cycle

1) Go through all functions. Compute the next value to appear on the output using current input values and store it in a local data area (a value table inside the function). 2) Go through all functions. Transfer the new value from the local table inside to the data area holding the values of the outputs (=inputs to the next circuit)

Cycle-based simulators

Go through all functions using current inputs and compute next output

Update outputs & increase time with 1 delay unit

Event-based Simulators

Go through all functions whose inputs has changed and compute next output

Update outputs & increase time with 1 delay unit

Event-based simulators with event queues

Go through all functions whose inputs has changed and compute value and time for next output change

Increase time to first scheduled event & update signals

VHDL Simulation Cycle

VHDL uses a simulation cycle to model the stimulus and response nature of digital hardware.

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VHDL Delay Models

Delay is created by scheduling a signal assignment for a future time. Delay in a VHDL cycle can be of several types Inertial

Transport
Delta

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Inertial Delay
Default delay type Allows for user specified delay Absorbs pulses of shorter duration than the specified delay

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Transport Delay
Must be explicitly specified by user Allows for user specified delay Passes all input transitions with delay

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Delta Delay

Delta delay needed to provide support for concurrent operations with zero delay
The order of execution for components with zero delay is not clear

Scheduling of zero delay devices requires the delta delay

A delta delay is necessary if no other delay is specified A delta delay does not advance simulator time One delta delay is an infinitesimal amount of time The delta is a scheduling device to ensure repeatability

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Example Delta Delay

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How do we write code?

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Basic Form of VHDL Code

Every VHDL design description consists of at least one entity / architecture pair, or one entity with multiple architectures. The entity section is used to declare I/O ports of the circuit. The architecture portion describes the circuits behavior. A behavioral model is similar to a black box. Standardized design libraries are included before entity declaration.

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Standard Libraries
Include library ieee; before entity declaration. ieee.std_logic_1164 defines a standard for designers to use in describing interconnection data types used in VHDL modeling. ieee.std_logic_arith provides a set of arithmetic, conversion, comparison functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector. Ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and comparison functions for std_logic_vector. See all available packages at
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http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html

Entity Declaration
An entity declaration describes the interface of the component. Avoid using Alteras primitive names which can be found at

c:/altera/91/quartus/common/help/webhelp/master.htm#
PORT clause indicates input and output ports. An entity can be thought of as a symbol for a component.

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Port Declaration
PORT declaration establishes the interface of the object to the outside world. Three parts of the PORT declaration
Name
Any identifier that is not a reserved word.

Mode
In, Out, Inout, Buffer

Data type
Any declared or predefined datatype.

Sample PORT declaration syntax:

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Architecture Declaration
Architecture declarations describe the operation of the component. Many architectures may exist for one entity, but only one may be active at a time. An architecture is similar to a schematic of the component.

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Modeling Styles

There are three modeling styles:

Behavioral (Sequential) Data flow Structural
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VHDL Hierarchy

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Sequential vs Concurrent Statements

VHDL provides two different types of execution: sequential and concurrent. Different types of execution are useful for modeling of real hardware.
Supports various levels of abstraction.

Sequential statements view hardware from a programmer approach. Concurrent statements are orderindependent and asynchronous.
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Sequential Style

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Data flow Style

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Structural Style

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Sequential Style Syntax

Assignments are executed sequentially inside processes.

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Sequential Statements
{Signal, Variable} assignments Flow control
if <condition> then <statments> [elsif <condition> then <statments>] else <statements> end if; for <range> loop <statments> end loop; while <condition> loop <statments> end loop; case <condition> is
when <value> => <statements>; when <value> => <statements>; when others => <statements>;

Wait on <signal> until <expression> for <time>;

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Data Objects
There are three types of data objects:
Signals
Can be considered as wires in a schematic. Can have current value and future values.

Variables and Constants

Used to model the behavior of a circuit. Used in processes, procedures and functions.

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Constant Declaration
A constant can have a single value of a given type. A constants value cannot be changed during the simulation. Constants declared at the start of an architecture can be used anywhere in the architecture. Constants declared in a process can only be used inside the specific process.
CONSTANT constant_name : type_name [ : = value]; CONSTANT rise_fall_time : TIME : = 2 ns; CONSTANT data_bus : INTEGER : = 16;

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Variable Declaration

Variables are used for local storage of data. Variables are generally not available to multiple components or processes. All variable assignments take place immediately. Variables are more convenient than signals for the storage of (temporary) data.

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Signal Declaration

Signals are used for communication between components. Signals are declared outside the process. Signals can be seen as real, physical signals. Some delay must be incurred in a signal assignment.

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Signal Assignment
A key difference between variables and signals is the assignment delay.

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Variable Assignment

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IF vs CASE statement Syntax

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FOR vs WHILE statement Syntax

For is considered to be a combinational circuit by some synthesis tools. Thus, it cannot have a wait statement to be synthesized.

While is considered to be an FSM by some synthesis tools. Thus, it needs a wait statement to be synthesized.

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WAIT statement Syntax

The wait statement causes the suspension of a process statement or a procedure. wait [sensitivity_clause] [condition_clause] [timeout_clause]; Sensitivity_clause ::= on signal_name
wait wait wait on CLOCK; Clock = 1;

Condition_clause ::= until boolean_expression

until for

Timeout_clause ::= for time_expression

150 ns;

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Sensitivity-lists vs Wait-on - statement

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Concurrent Process Equivalents

All concurrent statements correspond to a process equivalent. U0: q <= a xor b after 5 ns;
is short hand notation for U0: process begin q <= a xor b after 5 ns; wait on a, b; end process;
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Structural Style
Circuits can be described like a netlist. Components can be customized. Large, regular circuits can be created.

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Structural Statements

Structural VHDL describes the arrangement and interconnection of components.

Behavioral descriptions, on the other hand, define responses to signals.

Structural descriptions can show a more concrete relation between code and physical hardware. Structural descriptions show interconnects at any level of abstraction.
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Structural Statements
The component instantiation is one of the building blocks of structural descriptions. The component instantiation process requires component declarations and component instantiation statements. Component instantiation declares the interface of the components used in the architecture.

At instantiation, only the interface is visible.

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The internals of the component are hidden.

Component Declaration
The component declaration declares the interface of the component to the architecture. Necessary if the component interface is not declared elsewhere (package, library).

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Component Instantiation

The instantiation statement maps the interface of the component to other objects in the architecture.

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Component Instantiation Syntax

The instantiation has 3 key parts
Name Component type Port map

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Component Libraries

Component declarations may be made inside packages.

Components do not have to be declared in the architecture body

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entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vec

Generics
Generics allow the component to be customized upon instantiation. Generics pass information from the entity to the architecture. Common uses of generics
Customize timing Alter range of subtypes Change size of arrays
ENTITY adder IS GENERIC(n: natural :=2); PORT( A: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); B: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); C: OUT STD_LOGIC; SUM: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0) ); END adder;

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Technology Modeling
One use of generics is to alter the timing of a certain component. It is possible to indicate a generic timing delay and then specify the exact delay at instantiation.

The example above declares the interface to a component named inv. The propagation time for high-to-low and low-to-high transitions can be specified later.
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Structural Statements
The GENERIC MAP is similar to the PORT MAP in that it maps specific values to generics declared in the component.

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Generate Statement
Structural for-loops: The GENERATE statement
Some structures in digital hardware are repetitive in nature. (RAM, ROM, registers, adders, multipliers, ) VHDL provides the GENERATE statement to automatically create regular hardware. Any VHDL concurrent statement may be included in a GENERATE statement, including another GENERATE statement.

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Generate Statement Syntax

All objects created are similar. The GENERATE parameter must be discrete and is undefined outside the GENERATE statement.

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Example: Array of AND-gates

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VHDL Data Types

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Predefined Data Types

bit (0 or 1) bit_vector (array of bits) integer real time (physical data type)

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Integer
Integer
Minimum range for any implementation as defined by standard: -2,147,483,647 to 2,147,483,647 Integer assignment example

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Real
Real
Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38 Real assignment example

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Enumerated
Enumerated
User defined range Enumerated example

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Physical
Physical
Can be user defined range Physical type example

Time units are the only predefined physical type in VHDL.

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Array
Array
Used to collect one or more elements of a similar type in a single construct. Elements can be any VHDL data type.

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Record
Record
Used to collect one or more elements of different types in a single construct. Elements can be any VHDL data type. Elements are accessed through field name.

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Subtype
Subtype
Allows for user defined constraints on a data type. May include entire range of base type. Assignments that are out of the subtype range result in error. Subtype example

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Natural and Positive Integers

Integer subtypes:
Subtype Natural is integer range 0 to integerhigh; Subtype Positive is integer range 1 to integerhigh;

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Boolean, Bit and Bit_vector

type Boolean is (false, true); type Bit is (0, 1); type Bit_vector is array (integer range <>) of bit;

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Char and String

type Char is (NUL, SOH, , DEL);

128 chars in VHDL87 256 chars in VHDL93

type String is array (positive range <>) of Char;

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IEEE Predefined data types

type Std_ulogic is (U, X, 0, 1, Z, W, L, H, -);
U -- Uninitialized X -- Forcing unknown 0 -- Forcing zero 1 -- Forcing one Z -- High impedance W -- Weak Unknown L -- Weak Low H -- Weak High - -- Dont care

type std_logic is resolved std_ulogic; type std_logic_vector is array (integer range <>) of std_logic;

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Assignments

constant a: integer := 523; signal b: bit_vector(11 downto 0);

b <= 000000010010; b <= B000000010010; b <= B0000_0001_0010; b <= X012; b <= O0022;

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Vector & Array assignments

subtype instruction: bit_vector(31 downto 0); signal regs: array(0 to 15) of instruction;
regs(2) <= regs(0) + regs(1); regs(1)(7 downto 0) <= regs(0)(11 downto 4);

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Alias Statement

Signal instruction: bit_vector(31 downto 0);

Alias op1: bit_vector(3 downto 0) is instruction(23 downto 20); Alias op2: bit_vector(3 downto 0) is instruction(19 downto 16); Alias op3: bit_vector(3 downto 0) is instruction(15 downto 12); Op1 <= 0000; Op2 <= 0001; Op3 <= 0010; Regs(bit2int(op3)) <= regs(bit2int(op1)) + regs(bit2int(op2));
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Type Conversion (Similar Base)

Similar but not the same base type:

signal i: integer; signal r: real;

i <= integer(r); r <= real(i);

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Type Conversion (Same Base)

Same base type: type a_type is array(0 to 4) of bit; signal a:a_type; signal s:bit_vector(0 to 4);
a<=00101 -- Error, is RHS a bit_vector or an a_type? a<=a_type(00101); -- type qualifier a<=a_type(s); -- type conversion

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Type Conversion (Different Base)

Different base types: Function int2bits(value:integer;ret_size:integer) return bit_vector; Function bits2int(value:bit_vector) return integer:
signal i:integer; signal b:bit_vector(3 downto 0) i<=bits2int(b); b<=int2bits(i,4);
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Built-In Operators

Logic operators
AND, OR, NAND, NOR, XOR, XNOR (XNOR in VHDL93 only!!)

Relational operators
=, /=, <, <=, >, >=

Addition operators
+, -, &

Multiplication operators
*, /, mod, rem

Miscellaneous operators
**, abs, not
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Simulate Design using Quartus II

Alteras Quartus II is a PLD design software suitable for high-density FPGA designs. Schematic Editor, VHDL/Verilog Editor, Waveform Simulator.

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