CPS 104 Computer Organization and Programming Lecture- 22: Single Cycle Datapath, Control

March 1, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

CPS104 Lec22.1

GK Spring 2004

Admin.

Homework-4 is Due. Homework-5: Posted, Due March15, in Class u Do homework-5 this week as preparation for the midterm exam. Midterm Exam March 5th. u In Class u 1 hour u Closed books u Covers all material including Data-path. u Bring SPIM manual and/or Common MIPS Instructions. Wednesday March 3, Review Session u Bring questions about ANY topic we covered in the course.
GK Spring 2004

CPS104 Lec22.2

Review: Putting it All Together: A Single Cycle Datapath

We have everything except control signals.

Branch Rd RegDst Rt Rs 5 5 busA 32 0 Mux ALU Rt Jump Clk Instruction Fetch Unit

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5 ALUctr

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16

Data In 32 Clk

16

Data Memory

ALUSrc
CPS104 Lec22.3

ExtOp

GK Spring 2004

Review: RTL: The ADD Instruction

31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

add rd, rs, rt

u

mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4

Fetch the instruction from memory The actual operation

Calculate the next instructions address

CPS104 Lec22.4

GK Spring 2004

Instruction Fetch Unit at the Beginning of Add / Subtract

Fetch the instruction from Instruction memory: Instruction <- mem[PC] u This is the same for all instructions
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = previous Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = previous Zero = previous

CPS104 Lec22.5
GK Spring 2004

The Single Cycle Datapath during Add and Subtract

31 op

26 rs

21 rt

16 rd

11 shamt

6 funct

R[rd] <- R[rs] + / - R[rt]

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit ALUctr = ?

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ? 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec22.6

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Add and Subtract

31 op

26 rs

21 rt

16 rd

11 shamt

6 funct

R[rd] <- R[rs] + / - R[rt]

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add or Sub

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 1

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 0

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

ALU

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 0
CPS104 Lec22.7

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Add and Subtract

PC <- PC + 4 u This is the same for all instructions except: Branch and Jump
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = ?

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = ? Zero = ?
CPS104 Lec22.8
GK Spring 2004

Instruction Fetch Unit at the End of Add and Subtract

PC <- PC + 4 u This is the same for all instructions except: Branch and Jump
30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = 0

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = 0 Zero = x
CPS104 Lec22.9
GK Spring 2004

The Single Cycle Datapath during Or Immediate

31 op

26 rs

21 rt

16 immediate

R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0 ALUctr = ?

RegWr = ? 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec22.10

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Or Immediate

31 op

26 rs

21 rt

16 immediate

R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 0

1 Mux 0 ALUctr = Or

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 0

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

ALU

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 1
CPS104 Lec22.11

ExtOp = 0

GK Spring 2004

The Single Cycle Datapath during Load

31 op

26 rs

21 rt

16 immediate

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = ? Rd Rt Rs 5 5 Jump = ? Clk Rt Instruction Fetch Unit ALUctr = ? Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ? 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = ?

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = ? 0 Mux

ALU

32 WrEn Adr

Mux Data In 32 Clk

1 32

imm16

16

Data Memory

ALUSrc = ?
CPS104 Lec22.12

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Load

31 op

26 rs

21 rt

16 immediate

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = 0 Rd Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = 0

1 Mux 0

RegWr = 1 5 busW 32 Clk

Rt Zero

Rs

Rd

Imm16 MemtoReg = 1

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux

ALU

32 WrEn Adr

Mux Data In 32 Clk

1 32

imm16

16

Data Memory

ALUSrc = 1
CPS104 Lec22.13

ExtOp = 1

GK Spring 2004

The Single Cycle Datapath during Store

31 op

26 rs

21 rt

16 immediate

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = Rd Rt Jump = Clk Instruction Fetch Unit ALUctr Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst =

1 Mux 0 5 Rs Rt 5 5

RegWr = busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg =

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc =
CPS104 Lec22.14

ExtOp =

GK Spring 2004

The Single Cycle Datapath during Store

31 op

26 rs

21 rt

16 immediate

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = 0 Rd Rt Jump =0 Clk Instruction Fetch Unit ALUctr Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst =x

1 Mux 0 Rs Rt 5 5

RegWr = 0 5 busW 32 Clk

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg =x

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr =1 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc =1
CPS104 Lec22.15

ExtOp = 1

GK Spring 2004

The Single Cycle Datapath during Branch

31 op

26 rs

21 rt

16 immediate

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = ? Rd Rt Rs 5 5 5 Zero ALU MemWr = ? 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = ? Data Memory Jump = ? Clk Rt Instruction Fetch Unit ALUctr =? Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = ?

1 Mux 0

RegWr = ?

Rt

Rs

Rd

Imm16 MemtoReg = ?

busW 32 Clk

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

32

Mux

imm16

16

CPS104 Lec22.16

ExtOp = ?

GK Spring 2004

The Single Cycle Datapath during Branch

31 op

26 rs

21 rt

16 immediate

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = 1 Rd Rt Rs 5 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Subtract Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = x

1 Mux 0

RegWr = 0

Rt Zero ALU

Rs

Rd

Imm16 MemtoReg = x

busW 32 Clk

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

MemWr = 0 0 Mux 32

32 WrEn Adr

Mux Data In 32 Clk

imm16

16

Data Memory

ALUSrc = 0
CPS104 Lec22.17

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Branch

31 op

26 rs

21 rt

16 immediate

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux Jump = ? 1 0 32 Adder SignExt 30 Assume Zero = 1 to see the interesting case. Branch = ? Zero = 1
GK Spring 2004

30 00 Mux

Addr<31:2> Addr<1:0> Instruction Memory

1 30

Instruction<31:0>

imm16 16 Instruction<15:0>

CPS104 Lec22.18

Instruction Fetch Unit at the End of Branch

31 op

26 rs

21 rt

16 immediate

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux Jump = 0 1 0 32 Adder SignExt 30 Assume Zero = 1 to see the interesting case. Branch = 1 Zero = 1
GK Spring 2004

30 00 Mux

Addr<31:2> Addr<1:0> Instruction Memory

1 30

Instruction<31:0>

imm16 16 Instruction<15:0>

CPS104 Lec22.19

The Single Cycle Datapath during Jump

31 op

26 target address

Nothing to do! Make sure control signals are set correctly!

Branch = 0 Rd Rt Rs 5 5 Zero ALU MemWr = 0 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = x Data Memory Jump = 1 Clk Rt Instruction Fetch Unit ALUctr = x Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

RegDst = x

1 Mux 0

RegWr = 0 5 busW 32 Clk

Rt

Rs

Rd

Imm16 MemtoReg = x

busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

32

Mux

imm16

16

CPS104 Lec22.20

ExtOp = x

GK Spring 2004

Instruction Fetch Unit at the End of Jump

31 op

26 target address

PC <- PC<31:28> concat target<25:0> concat 00

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump = 1

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch = X Zero = x
CPS104 Lec22.21
GK Spring 2004

A Summary of the Control Signals

See Appendix A func 10 0000 10 0010 We Dont Care :-) op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 Branch 0 0 0 0 0 1 x Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add Subtract xxx 31 R-type I-type J-type op op op 26 rs rs 21 rt rt target address 16 rd 11 shamt immediate 6 funct 0 add, sub ori, lw, sw, beq jump
GK Spring 2004

CPS104 Lec22.22

The Concept of Local Decoding

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:0> 00 0000 R-type 1 0 0 1 0 0 0 x R-type 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 x 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx

op 6

Main Control

func 6 ALUop N

ALU Control (Local)

ALUctr 3 ALU

CPS104 Lec22.23

GK Spring 2004

The Encoding of ALUop

op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3

In this exercise, ALUop has to be 2 bits wide to represent: u (1) R-type instructions u I-type instructions that require the ALU to perform:

(2) Or, (3) Add, and (4) Subtract

To implement the full MIPS ISA, ALUop hat to be 3 bits to represent: u (1) R-type instructions u I-type instructions that require the ALU to perform:

(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type R-type 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 jump Subtract xxx xxx 0 01
GK Spring 2004

beq

ALUop (Symbolic) ALUop<2:0>

CPS104 Lec22.24

The Decoding of the func Field

op 6 Main Control func 6 ALUop N ori Or 0 10 16 rt rd ALUctr ALU Control (Local) lw Add 0 00 11 shamt ALUctr<2:0> 000 001 010 110 111 ALUctr 3

ALUop (Symbolic) ALUop<2:0> 31 R-type funct<5:0> 10 0000 10 0010 10 0100 10 0101 10 1010 op 26

R-type R-type 1 00 21 rs

sw Add 0 00 6

jump Subtract xxx xxx 0 01 0 funct ALU Operation Add Subtract And Or Set-on-less-than
GK Spring 2004

beq

Instruction Operation add subtract and or set-on-less-than

ALU

CPS104 Lec22.25

The Truth Table for ALUctr

R-type ALUop (Symbolic) R-type ALUop<2:0> 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01

funct<3:0> 0000 0010 0100 0101 1010

Instruction Op. add subtract and or set-on-less-than

ALUop bit<2> bit<1> bit<0> 0 0 0 0 x 1 0 1 x 1 x x 1 x x 1 x x 1 x x 1 x x

func bit<3> bit<2> bit<1> bit<0> x x x x x x x x x x x x 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0

ALU Operation Add Subtract Or Add Subtract And Or Set on <

ALUctr bit<2> bit<1> bit<0> 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1

CPS104 Lec22.26

GK Spring 2004

The Logic Equation for ALUctr<2>

ALUop bit<2> bit<1> bit<0> 0 x 1 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> x x x x 0 0 1 0 1 0 1 0 ALUctr<2> 1 1 1

This makes func<3> a dont care

ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

CPS104 Lec22.27

GK Spring 2004

The Logic Equation for ALUctr<1>

ALUop bit<2> bit<1> bit<0> 0 0 0 0 x 1 1 x x 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<1> x x x x 1 x x x x 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1

ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0>

CPS104 Lec22.28

GK Spring 2004

The Logic Equation for ALUctr<0>

ALUop bit<2> bit<1> bit<0> 0 1 x 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<0> x x x x 1 0 1 0 1 1 1 0 1 0 1

ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPS104 Lec22.29

GK Spring 2004

The ALU Control Block

func 6 ALUop 3 ALU Control (Local) ALUctr 3

ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0>

ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPS104 Lec22.30

GK Spring 2004

The Truth Table for the Main Control

op 6 RegDst ALUSrc Main Control

:
ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0

func 6

ALU Control (Local)

ALUctr 3

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0>

CPS104 Lec22.31

00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 x 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 GK Spring 2004

The Truth Table for RegWrite

op RegWrite

00 0000 R-type 1

00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 1 0 0 0

RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0>(R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>(ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>(lw)

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump RegWrite

CPS104 Lec22.32

GK Spring 2004

PLA Implementation of the Main Control

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump

RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> GK Spring 2004

CPS104 Lec22.33

Putting it All Together: A Single Cycle Processor

ALUop op Main Control 6 Instr<31:26> Rd RegDst RegDst ALUSrc 3 func Instr<5:0> 6 ALU Control ALUctr 3

:
Rt Rs Rt 5 5

Branch Jump Clk Instruction Fetch Unit

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5 ALUctr busA 32 0 Mux ALU

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16 Instr<15:0> 16

Data In 32 Clk

Data Memory

ALUSrc
CPS104 Lec22.34

ExtOp

GK Spring 2004

Worst Case Timing: lw $1, $2(offset)

Clk PC Old Value Rs, Rt, Rd, Op, Func Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Old Value Old Value Delay through Extender & Mux Old Value Old Value Data Memory Access Time Old Value New
GK Spring 2004

ALUctr ExtOp ALUSrc MemtoReg RegWr busA busB Addres s busW CPS104 Lec22.35

Instruction Memoey Access Time New Value Delay through Control Logic New Value New Value New Value New Value

New Value Register File Access Time New Value New Value ALU Delay

Register Write Occurs

New Value

Drawback of this Single Cycle Processor

Long cycle time: u Cycle time must be long enough for the load instruction:
PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew

Cycle time is much longer than needed for all other instructions

CPS104 Lec22.36

GK Spring 2004