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Half and Full Adder Implementation in Verilog (DSD)

The document describes different implementations of half adders and full adders in Verilog code with varying delays. It includes truth tables and testbenches for half adders and full adders built using half adders, gates, and with different delay values. Code snippets and descriptions are provided for half adders and full adders with no delay, #1 delay, and #3 delay. Waveforms are also shown for some of the implementations.

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waqasahmadz
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© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
309 views

Half and Full Adder Implementation in Verilog (DSD)

The document describes different implementations of half adders and full adders in Verilog code with varying delays. It includes truth tables and testbenches for half adders and full adders built using half adders, gates, and with different delay values. Code snippets and descriptions are provided for half adders and full adders with no delay, #1 delay, and #3 delay. Waveforms are also shown for some of the implementations.

Uploaded by

waqasahmadz
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Half adder

Truth table
A B SUM CARRY
0
0
1
1

0
1
0
1

0
1
1
0

Half adder code with no delay

Half adder testbench

module ha(sum,cout,a,b);
input a,b;
output sum,cout;
xor (sum,a,b);
and (cout,a,b);
endmodule

module testha;
reg a,b;
wire sum,cout;
ha h0(sum,cout,a,b);
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
endmodule

WAVE FORM

0
0
0
1

Description

Half adder code with #1 delay


Code
module ha(sum,cout,a,b);
input a,b;
output sum,cout;
xor#1 (sum,a,b);
and#1 (cout,a,b);
endmodule

Description

Half adder code with #3 delay


module ha(sum,cout,a,b);
input a,b;
output sum,cout;
xor#3 (sum,a,b);

and#3 (cout,a,b);
endmodule

WAVE FORM

Description

--------------------------------------------------------------------------------------------

Full adder code using half adders with no delay


A

0
0
0
0
1

0
0
1
1
0

Cin SUM CARRY


0
1
0
1
0

0
1
1
0
1

0
0
0
1
0

1
1
1

0
1
1

1
0
1

Full adder code with no delay

Testbench

module fl(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire w1,w2,w3;
ha a1(w1,w2,a,b);
ha a2(sum,w3,w1,cin);
or (cout,w2,w3);
endmodule

module testfl;
reg a,b,cin;
wire sum,cout;
fl f0(sum,cout,a,b,cin);
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#5 a=1'b0;b=1'b0;cin=1'b1;
#5 a=1'b0;b=1'b1;cin=1'b0;
#5 a=1'b0;b=1'b1;cin=1'b1;
#5 a=1'b1;b=1'b0;cin=1'b0;
#5 a=1'b1;b=1'b0;cin=1'b1;
#5 a=1'b1;b=1'b1;cin=1'b0;
#5 a=1'b1;b=1'b1;cin=1'b1;
end
endmodule

Description

0
0
1

1
1
1

Full adder code using half adders with #1 delay


module fl(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire w1,w2,w3;
ha a1(w1,w2,a,b);
ha a2(sum,w3,w1,cin);
or#1 (cout,w2,w3);
endmodule

Full adder code using half adders with #3 delay


module fl(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire w1,w2,w3;
ha a1(w1,w2,a,b);
ha a2(sum,w3,w1,cin);
or#3 (cout,w2,w3);
endmodule

--------------------------------------------------------------------------------------------

Full adder code using gates with no delay


Full adder code
module fulladder(sum,carry,a,b,cin);
input a,b,cin;
output sum,carry;
wire w1,w2,w3;
xor (w1,a,b);
xor(sum,w1,cin);
and(w2,w1,cin);
and(w3,a,b);
or(carry,w2,w3);
endmodule

Testbench
module testfulladder;
reg a,b,cin;
wire sum,carry;
fulladder f0(sum,cout,a,b,cin);
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#5 a=1'b0;b=1'b0;cin=1'b1;
#5 a=1'b0;b=1'b1;cin=1'b0;
#5 a=1'b0;b=1'b1;cin=1'b1;
#5 a=1'b1;b=1'b0;cin=1'b0;
#5 a=1'b1;b=1'b0;cin=1'b1;
#5 a=1'b1;b=1'b1;cin=1'b0;
#5 a=1'b1;b=1'b1;cin=1'b1;
end
endmodule

Full adder code using gates with #1 delay


module fulladder(sum,carry,a,b,cin);
input a,b,cin;
output sum,carry;
wire w1,w2,w3;
xor#1(w1,a,b);
xor#1(sum,w1,cin);
and#1(w2,w1,cin);
and#1(w3,a,b);
or#1(carry,w2,w3);
endmodule

Full adder code using gates with #3 delay


module fulladder(sum,carry,a,b,cin);
input a,b,cin;

output sum,carry;
wire w1,w2,w3;
xor#3(w1,a,b);
xor#3(sum,w1,cin);
and#3(w2,w1,cin);
and#3(w3,a,b);
or#3(carry,w2,w3);
endmodule

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