APPLICATION

NOTE
AP-248
Septembei 1987
Using The 8096
IRA HORDEN
MCO APPLICATIONS FNOINFFR
Order Number 270061-002
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev-
er including infringement of any patent or copyright for sale and use of Intel products except as provided in
Intels Terms and Conditions of Sale for such products
Intel retains the right to make changes to these specifications at any time without notice Microcomputer
Products may have minor variations to this specification known as errata
Other brands and names are the property of their respective owners
Since publication of documents referenced in this document registration of the Pentium OverDrive and
iCOMP trademarks has been issued to Intel Corporation
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
product order
Copies of documents which have an ordering number and are referenced in this document or other Intel
literature may be obtained from
Intel Corporation
PO Box 7641
Mt Prospect IL 60056-7641
or call 1-800-879-4683
COPYRIGHT INTEL CORPORATION 1996
Using The 8096
CONTENTS PAGE
10 INTRODUCTION 1
20 8096 OVERVIEW 1
21 General Description 1
211 CPU Section 2
212 IO Features 4
22 The Processor Section 4
221 Operations and Addressing
Modes 4
222 Assembly Language 7
223 Interrupts 8
23 On-Chip IO Section 10
231 TimerCounters 10
232 HSI 11
233 HSO 12
234 Serial Port 13
235 A to D Converter 16
236 PWM Register 17
30 BASIC SOFTWARE EXAMPLES 19
31 Using the 8096s Processing
Section 19
311 Table Interpolation 19
312 PLM-96 22
32 Using the IO Section 24
321 Using the HSI Unit 24
322 Using the HSO Unit 25
323 Using the Serial Port in
Mode 1 29
324 Using the A to D 31
40 ADVANCED SOFTWARE
EXAMPLES 31
41 Simultaneous IO Routines under
Interrupt Control 31
42 Software Serial Port Using the
HSIO Unit 34
43 Interfacing an Optical Encoder to
the HSI Unit 39
50 HARDWARE EXAMPLE 51
51 EPROM Only Minimum
System 51
52 Port Reconstruction 53
60 CONCLUSION 54
70 BIBLIOGRAPHY 54
CONTENTS PAGE
APPENDICES
Appendix A Basic Software
Examples A-1
A1 Table Lookup 1 A-1
A2 Table Lookup 2 A-3
A3 PLM-96 Code with Expansion A-5
A4 Pulse Measurement A-11
A5 Enchanced Pulse Measurement A-13
CONTENTS PAGE
A6 PWM Using the HSO A-15
A7 Serial Port A-19
A8 A to D Converter A-21
Appendix B HSO and A to D Under
Interrupt Control B-1
Appendix C Software Serial Port C-1
Appendix D Motor Control Program D-1
Figures
2-1 8096 Block Diagram 1
2-2 Memory Map 2
2-3 SFR Layout 3
2-4 Major IO Functions 4
2-5 Instruction Summary 5
2-6 Instruction Format 7
2-7 Interrupt Sources 8
2-8 Interrupt Vectors and Priorities 8
2-9 Interrupt Structure Block
Diagram 9
2-10 The PSW Register 10
2-11 HSI Unit Block Diagram 11
2-12 HSI Mode Register 11
2-13 HSO Command Register 12
2-14 HSO Block Diagram 12
2-15 Serial Port ControlStatus
Register 13
2-16 Baud Rate Formulas 14
2-17 Baud Rate Values for 10 11 12
MHz 15
2-18 Multiprocessor Communication 16
2-19 A to D ResultCommand
Register 17
2-20 PWM Output Waveforms 18
2-21 PWM to Analog Conversion
Circuitry 18
3-1 Using the HSIO to Monitor Rotating
Machinery 28
3-2 Serial Port Level Conversion 30
4-1 10-Bit Asynchronous Frame 35
4-2 Optical Encoder and Waveforms 39
4-3 Filtered Encoder Waveforms 40
4-4 Schematic of Optical Encoder to
8096 Interface 41
4-5 Motor Driver Circuitry 41
4-6 Mode State Diagram 44
4-7 Motor Control Modes 49
5-1 Minimum System Configuration 52
Listings
3-1 Include File DEMO96INC 19
3-2 ASM-96 Code for Table Lookup
Routine 1 20
3-3 ASM-96 Code for Table Lookup
Routine 1 21
3-4 PLM-96 Code for Table Lookup
Routine 1 23
3-5 32-Bit Result Multiply Procedure for
PLM-96 23
3-6 Measuring Pulses Using the HSI
Unit 24
3-7 Enhanced HSI Pulse Measurement
Routine 25
3-8 Generating a PWM with the HSO 26
3-9 Changes to Declarations for HSO
Routine 27
3-10 Driver Module for HSO PWM
Program 27
3-11 Using the Serial Port in Mode 1 29
3-12 Scanning the A to D Channels 31
4-1 Using Multiple IO Devices 32
4-2 Software Serial Port
Declarations 35
4-3 Software Serial Port Interface
Routines 36
4-4 Software Serial Port Initialization
Routine 36
4-5 Software Serial Port Transmit
Process 37
4-6 Receive Process 37
4-7 Motor Control HSO0 Timer
Routine 42
4-8 Motor Control HSI Data Available
Routine 44
4-9 Motor Control Mode 1 Routines 45
4-10 Motor Control Mode 0 Routines 46
4-11 Motor Control Software Timer 1
Routine 47
4-12 Motor Control Next Position
Lookup 49
4-13 Motor Control Timer Interrupt
Routine 50
4-14 Motor Control Software Timer
Interrupt Handler 50
4-15 Motor Control Software Timer 2
Routine 51
AP-248
10 INTRODUCTION
High speed digitaI signaIs aie fiequentIy encounteied in
modein contioI appIications. In addition, theie is often
a iequiiement foi high speed 16-bit and 32-bit piecision
in caIcuIations. The MCS-96 pioduct Iine, geneiicaIIy
iefeiied to as the 8096, is designed to be used in appIi-
cations which iequiie high speed caIcuIations and fast
I/O opeiations.
The 8096 is a 16-bit miciocontioIIei with dedicated
I/O subsystems and a compIete set of 16-bit aiithmetic
instiuctions incIuding muItipIy and divide opeiations.
This Ap-note wiII biiefIy desciibe the 8096 in section 2,
and then give shoit exampIes of how to use each of its
key featuies in section 3. The concIuding sections fea-
tuie a few exampIes which make use of seveiaI chip
featuies simuItaneousIy and some haidwaie connection
suggestions. Fuithei infoimation on the 8096 and its
use is avaiIabIe fiom the souices Iisted in the bibIiogia-
phy.
20 8096 OVERVIEW
21 General Description
UnIike miciopiocessois, miciocontioIIeis aie geneiaIIy
optimized foi specific appIications. InteIs 8048 was op-
timized foi geneiaI contioI tasks whiIe the 8051 was
optimized foi 8-bit math and singIe bit booIean opeia-
tions. The 8096 has been designed foi high speed/high
peifoimance contioI appIications. Because it has been
designed foi these appIications the 8096 aichitectuie is
diffeient fiom that of the 8048 oi 8051.
Theie aie two majoi sections of the 8096, the CPU
section and the I/O section. Fach of these sections can
be subdivided into functionaI bIocks as shown in Figuie
2-1.
2700611
Figure 2-1 8096 Block Diagram
1
AP-248
211 CPU SECTION
The CPU of the 8096 uses a 16-bit ALU which opeiates
on a 256-byte iegistei fiIe instead of an accumuIatoi.
Any of the Iocations in the iegistei fiIe can be used foi
souices oi destinations foi most of the instiuctions.
This is caIIed a iegistei to iegistei aichitectuie. Many
of the instiuctions can aIso use bytes oi woids fiom
anywheie in the 64K byte addiess space as opeiands. A
memoiy map is shown in Figuie 2-2.
In the Iowei 24 bytes of the iegistei fiIe aie the iegistei-
mapped I/O contioI Iocations, aIso caIIed SpeciaI
Function Registeis oi SFRs. These iegisteis aie used to
contioI the on-chip I/O featuies. The iemaining 232
bytes aie geneiaI puipose RAM, the uppei 16 of which
can be kept aIive using a Iow cuiient powei-down
mode.
2700612
Figure 2-2 Memory Map
2
AP-248
Figuie 2-3 shows the Iayout of the iegistei mapped
I/O. Some of these iegisteis seive two functions, one if
they aie iead fiom and anothei if they aie wiitten
to. Moie infoimation about the use of these iegisteis is
incIuded in the desciiption of the featuies which they
contioI.
2700613
Figure 2-3 SFR Layout
3
AP-248
212 IO FEATURES
Many of the I/O featuies on the 8096 aie designed to
opeiate with IittIe CPU inteivention. A Iist of the majoi
I/O functions is shown in Figuie 2-4. The Watchdog
Timei is an inteinaI timei which can be used to ieset
the system if the softwaie faiIs to opeiate piopeiIy. The
PuIse-Width-ModuIation (PWM) output can be used as
a iough D to A, a motoi diivei, oi foi many othei
puiposes. The A to D conveitei (ADC) has 8 muIti-
pIexed inputs and 10-bit iesoIution. The seiiaI poit has
seveiaI modes and its own baud iate geneiatoi. The
High Speed I/O section incIudes a 16-bit timei, a 16-bit
countei, a 4-input piogiammabIe edge detectoi, 4 soft-
waie timeis, and a 6-output piogiammabIe event genei-
atoi. AII of these featuies wiII be desciibed in section
2.3.
22 The Processor Section
221 OPERATIONS AND ADDRESSING MODES
The 8096 has 100 instiuctions, some of which opeiate
on bits, some on bytes, some on woids and some on
Iongs (doubIe woids). AII of the standaid IogicaI and
aiithmetic functions aie avaiIabIe foi both byte and
woid opeiations. Bit opeiations and Iong opeiations aie
piovided foi some instiuctions. Theie aie aIso fIag ma-
nipuIation instiuctions as weII as jump and caII instiuc-
tions. A fuII set of conditionaI jumps has been incIuded
to speed up testing foi vaiious conditions.
Bit opeiations aie piovided by the Jump Bit and Jump
Not Bit instiuctions, as weII as by immediate masking
of bytes. These bit opeiations can be peifoimed on any
of the bytes in the iegistei fiIe oi on any of the speciaI
function iegisteis. The fast bit manipuIation of the
SFRs can piovide iapid I/O opeiations.
A symmetiic set of byte and woid opeiations make up
the majoiity of the 8096 instiuction set. The assembIy
Ianguage foi the 8096 (ASM-96) uses a B suffix on a
mnemonic to indicate a byte opeiation, without this
suffix a woid opeiation is indicated. Many of these op-
eiations can have one, two oi thiee opeiands. An exam-
pIe of a one opeiand instiuction wouId be:
NOT Value1 Value1 e 1s complement (Value1)
A two opeiand instiuction wouId have the foim:
ADD Value2Value1 Value2 e Value2 a Value1
A thiee opeiand instiuction might Iook Iike:
MUL Value3Value2Value1
Value3 e Value2

Value1
The thiee opeiand instiuctions combined with the ieg-
istei to iegistei aichitectuie aImost eIiminate the neces-
sity of using tempoiaiy iegisteis. This iesuIts in a fastei
piocessing time than machines that have equivaIent in-
stiuction execution times, but use a standaid aichitec-
tuie.
Long (32-bit) opeiations incIude shifts, noimaIize, and
muItipIy and divide. The woid divide is a 32-bit by 16-
bit opeiation with a 16-bit quotient and 16-bit iemain-
dei. The woid muItipIy is a woid by woid muItipIy
with a Iong iesuIt. Both of these opeiations can be done
in eithei the signed oi unsigned mode. The diiect un-
signed modes of these instiuctions take onIy 6.5 micio-
seconds. A noimaIize instiuction and sticky bit fIag
have been incIuded in the instiuction set to piovide
haidwaie suppoit foi the softwaie fIoating point pack-
age (FPAL-96).
Major IO Functions
High Speed Input Unit Provides Automatic Recording of Events
High Speed Output Unit Provides Automatic Triggering of Events and Real-Time Interrupts
Pulse Width Modulation Output to Drive Motors or Analog Circuits
A to D Converter Provides Analog Input
Watchdog Timer Resets 8096 if a Malfunction Occurs
Serial Port Provides Synchronous or Asynchronous Link
Standard IO Lines Provide Interface to the External World when other Special Features
are not needed
Figure 2-4 Major IO Functions
4
AP-248
Mnemonic
Oper-
Operation (Note 1)
Flags
Notes
ands Z N C V VT ST
ADDADDB 2 D wD a A u
ADDADDB 3 D wB a A u
ADDCADDCB 2 D wD a A aC v u
SUBSUBB 2 D wD bA u
SUBSUBB 3 D wB bA u
SUBCSUBCB 2 D wD bA a C b1 v u
CMPCMPB 2 D bA u
MULMULU 2 D D a 2 wD

A 2
MULMULU 3 D D a 2 wB

A 2
MULBMULUB 2 D D a 1 wD

A 3
MULBMULUB 3 D D a 1 wB

A 3
DIVU 2 D w(D D a 2)A D a 2 wremainder u 2
DIVUB 2 D w(D D a 1)A D a 1 wremainder u 3
DIV 2 D w(D D a 2)A D a 2 wremainder u 2
DIVB 2 D w(D D a 1)A D a 1 wremainder u 3
ANDANDB 2 D wD and A 0 0
ANDANDB 3 D wB and A 0 0
ORORB 2 D wD or A 0 0
XORXORB 2 D wD (excl or) A 0 0
LDLDB 2 D wA
STSTB 2 A wD
LDBSE 2 D wA D a 1 wSIGN(A) 3 4
LDBZE 2 D wA D a 1 w0 3 4
PUSH 1 SP wSP b2 (SP) wA
POP 1 A w(SP) SP wSP a 2
PUSHF 0 SP wSP b2 (SP) wPSW 0 0 0 0 0 0
PSW w0000H I w0
POPF 0 PSW w(SP) SP wSP a 2 I w
SJMP 1 PC wPC a 11-bit offset 5
LJMP 1 PC wPC a 16-bit offset 5
BR (indirect) 1 PC w(A)
SCALL 1 SP wSP b2 (SP) wPC 5
PC wPC a 11-bit offset
LCALL 1 SP wSP b2 (SP) wPC 5
PC wPC a 16-bit offset
RET 0 PC w(SP) SP wSP a 2
J (conditional) 1 PC wPC a 8-bit offset (if taken) 5
JC 1 Jump if C e 1 5
JNC 1 Jump if C e 0 5
JE 1 Jump if Z e 1 5
Figure 2-5 Instruction Summary
NOTES
1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and A
must conform to the alignment rules for the required operand type D and B are locations in the register file A can be
located anywhere in memory
2 D D a 2 are consecutive WORDS in memory D is DOUBLE-WORD aligned
3 D D a 1 are consecutive BYTES in memory D is WORD aligned
4 Changes a byte to a word
5 Offset is a 2s complement number
5
AP-248
Mnemonic
Oper-
Operation (Note 1)
Flags
Notes
ands Z N C V VT ST
JNE 1 Jump if Z e 0 5
JGE 1 Jump if N e 0 5
JLT 1 Jump if N e 1 5
JGT 1 Jump if N e 0 and Z e 0 5
JLE 1 Jump if N e 1 or Z e 1 5
JH 1 Jump if C e 1 and Z e 0 5
JNH 1 Jump if C e 0 or Z e 1 5
JV 1 Jump if V e 1 5
JNV 1 Jump if V e 0 5
JVT 1 Jump if VT e 1 Clear VT 0 5
JNVT 1 Jump if VT e 0 Clear VT 0 5
JST 1 Jump if ST e 1 5
JNST 1 Jump if ST e 0 5
JBS 3 Jump if Specified Bit e 1 5 6
JBC 3 Jump if Specified Bit e 0 5 6
DJNZ 1 D wD b1 if D
i
0 then
PC wPC a 8-bit offset 5
DECDECB 1 D wD b1 u
NEGNEGB 1 D w0 bD u
INCINCB 1 D wD a 1 u
EXT 1 D wD D a 2 wSign (D) 0 0 2
EXTB 1 D wD D a 1 wSign (D) 0 0 3
NOTNOTB 1 D wLogical Not (D) 0 0
CLRCLRB 1 D w0 1 0 0 0
SHLSHLBSHLL 2 C wmsb Isb w0 u 7
SHRSHRBSHRL 2 0 xmsb Isb xC 0 7
SHRASHRABSHRAL 2 msb xmsb Isb xC 0 7
SETC 0 C w1 1
CLRC 0 C w0 0
CLRVT 0 VT w0 0
RST 0 PC w2080H 0 0 0 0 0 0 8
DI 0 Disable All Interrupts (I w0)
EI 0 Enable All Interrupts (I w1)
NOP 0 PC wPC a 1
SKIP 0 PC wPC a 2
NORML 2 Left Shift Till msb e 1 D wshift count 0 7
TRAP 0 SP wSP b2 (SP) wPC
PC w(2010H) 9
Figure 2-5 Instruction Summary (Continued)
NOTES
1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and A
must conform to the alignment rules for the required operand type D and B are locations in the register file A can be
located anywhere in memory
5 Offset is a 2s complement number
6 Specified bit is one of the 2048 bits in the register file
7 The L (Long) suffix indicates double-word operation
8 Initiates a Reset by pulling RESET low Software should re-initialize all the necessary registers with code starting at
2080H
9 The assembler will not accept this mnemonic
6
AP-248
One opeiand of most of the instiuctions can be used
with any one of six addiessing modes. These modes
inciease the fIexibiIity and oveiaII execution speed of
the 8096. The addiessing modes aie: iegistei-diiect, im-
mediate, indiiect, indiiect with auto-inciement, and
Iong and shoit indexed.
The fastest instiuction execution is gained by using ei-
thei iegistei diiect oi immediate addiessing. Registei-
diiect addiessing is simiIai to noimaI diiect addiessing,
except that onIy addiesses in the iegistei fiIe oi SFRs
can be addiessed. The indexed mode is used to diiectIy
addiess the iemaindei of the 64K addiess space. Imme-
diate addiessing opeiates as wouId be expected, using
the data foIIowing the opcode as the opeiand.
Both of the indiiect addiessing modes use the vaIue in a
woid iegistei as the addiess of the opeiand. If the indi-
iect auto-inciement mode is used then the woid iegistei
is inciemented by one aftei a byte access oi by two aftei
a woid access. This mode is paiticuIaiIy usefuI foi ac-
cessing Iookup tabIes.
Access to any of the Iocations in the 64K addiess space
can be obtained by using the Iong indexed addiessing
mode. In this mode a 16-bit 2s compIement vaIue is
added to the contents of a woid iegistei to foim the
addiess of the opeiand. By using the zeio iegistei as the
index, ASM96 (the assembIei) can accept diiect ad-
diessing to any Iocation. The zeio iegistei is Iocated at
0000H and aIways has a vaIue of zeio. A shoit indexed
mode is aIso avaiIabIe to save some time and code. This
mode uses an 8-bit 2s compIement numbei as the offset
instead of a 16-bit numbei.
222 ASSEMBLY LANGUAGE
The muItipIe addiessing modes of the 8096 make it easy
to piogiam in assembIy Ianguage and piovide an exceI-
Ient inteiface to high IeveI Ianguages. The instiuctions
accepted by the assembIei consist of mnemonics foI-
Iowed by eithei addiesses oi data. A Iist of the mne-
monics and theii functions aie shown in Figuie 2-5.
The addiesses oi data aie given in diffeient foimats
depending on the addiessing mode. These modes and
foimats aie shown in Figuie 2-6.
AdditionaI infoimation on 8096 assembIy Ianguage is
avaiIabIe in the MCS-96 Macio AssembIei Useis
Ouide, Iisted in the bibIiogiaphy.
270061B3
Figure 2-6 Instruction Format
7
AP-248
2700614
Figure 2-7 Interrupt Sources
223 INTERRUPTS
The fIexibiIity of the instiuction set is caiiied thiough
into the inteiiupt system. Theie aie 20 diffeient intei-
iupt souices that can be used on the 8096. The 20
souices vectoi thiough 8 Iocations oi inteiiupt vectois.
The vectoi names and theii souices aie shown in Fig-
uie 2-7, with theii Iocations Iisted in Figuie 2-8. Con-
tioI of the inteiiupts is handIed thiough the Inteiiupt
Pending Registei (INT
-
PFNDINO), the Inteiiupt
Mask Registei (INT
-
MASK), and the I bit in the
PSW (PSW.9). Figuie 2-9 shows a bIock diagiam of the
inteiiupt stiuctuie. The INT
-
PFNDINO iegistei
contains bits which get set by haidwaie when an intei-
iupt occuis. If the inteiiupt mask iegistei bit foi that
souice is a 1 and PSW.9
e
1, a vectoi wiII be taken to
the addiess Iisted in the inteiiupt vectoi tabIe foi that
Vector
Source
Location
Priority
(High (Low
Byte) Byte)
Software 2011H 2010H Not Applicable
Extint 200FH 200EH 7 (Highest)
Serial Port 200DH 200CH 6
Software Timers 200BH 200AH 5
HSI0 2009H 2008H 4
High Speed 2007H 2006H 3
Outputs
HSI Data 2005H 2004H 2
Available
AD Conversion 2003H 2002H 1
Complete
Timer Overflow 2001H 2000H 0 (Lowest)
Figure 2-8 Interrupt Vectors and Priorities
8
AP-248
souice. When the vectoi is taken the INT
-
PFNDINO
bit is cIeaied. If moie than one bit is set in the INT
-
PFNDINO iegistei with the coiiesponding bit set in
the INT
-
MASK iegistei, the Inteiiupt with the high-
est piioiity shown in Figuie 2-8 wiII be executed.
The softwaie can make the haidwaie inteiiupts woik in
aImost any fashion desiied by having each ioutine iun
with its own setup in the INT
-
MASK iegistei. This
wiII be cIeaiIy seen in the exampIes in section 4 which
change the piioiity of the vectois in softwaie. The
2700615
Figure 2-9 Interrupt Structure Block Diagram
9
AP-248
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Z N V VT C I ST INT

MASK
WHERE
Z is the zero flag It is set when the result of an operation is zero
N is the negative flag It is set to the algebraically correct sign of the result regardless of overflows
V is the overflow flag It is set if an overflow occurs
VT is the overflow trap flag It is set when the VT flag is set and cleared by JVT JNVT or CLRVT
C is the carry flag It is set if a carry was generated by the prior operation
I is the global interrupt enable bit
ST is the sticky bit It is set during a right shift if a one was shifted into and then out of the carry flag
INT

MASK is the interrupt mask register and contains bits which individually enable the 8 interrupt vectors
Figure 2-10 The PSW Register
PSW (shown in Figuie 2-10), stoies the INT
-
MASK
iegistei in its Iowei byte so that the mask iegistei can
be pushed and popped aIong with the machine status
when moving in and out of ioutines. The action of
pushing fIags cIeais the PSW which incIudes PSW.9,
the inteiiupt enabIe bit. Theiefoie, aftei a PUSHF in-
stiuction inteiiupts aie disabIed. In most cases an intei-
iupt seivice ioutine wiII have the basic stiuctuie shown
beIow.
INT VECTOR
PUSHF
LDB INT MASK xxxxxxxxB
EI
-
- Insert service routine here
-
POPF
RET
The PUSHF instiuction saves the PSW incIuding the
oId INT
-
MASK iegistei. The PSW, incIuding the in-
teiiupt enabIe bit aie Ieft cIeaied. If some inteiiupts
need to be enabIed whiIe the seivice ioutine iuns, the
INT
-
MASK is Ioaded with a new vaIue and intei-
iupts aie gIobaIIy enabIed befoie the seivice ioutine
continues. At the end of the seivice ioutine a POPF in-
stiuction is executed to iestoie the oId PSW. The RFT
instiuction is executed and the code ietuins to the de-
siied Iocation. AIthough the POPF instiuction can en-
abIe the inteiiupts the next instiuction wiII aIways exe-
cute. This pievents unnecessaiy buiIding of the stack by
ensuiing that the RFT aIways executes befoie anothei
inteiiupt vectoi is taken.
23 On-Chip IO Section
AII of the on-chip I/O featuies of the 8096 can be ac-
cessed thiough the speciaI function iegisteis, as shown
in Figuie 2-3. The advantage of using iegistei-mapped
I/O is that these iegisteis can be used as the souices oi
destinations of CPU opeiations. Theie aie seven majoi
I/O functions. Fach one of these wiII be consideied
with a section of code to exempIify its usage. The fiist
section coveied wiII be the High Speed I/O, (HSIO),
subsystem. This section incIudes the High Speed Input
(HSI) unit, High Speed Output (HSO) unit, and the
Timei/Countei section.
231 TIMERCOUNTERS
The 8096 has two time bases, Timei 1 and Timei 2.
Timei 1 is a 16-bit fiee iunning timei which is incie-
mented eveiy 8 state times. (A state time is 3 osciIIatoi
peiiods, oi 0.25 micioseconds with a 12 MHz ciystaI.)
10
AP-248
2700616
Pulse measurement with 20 msec resolution
Input transitions trigger the recording of the reference
Timer (16-bit) and triggered input(s) (4-bit)
Figure 2-11 HSI Unit Block Diagram
Its vaIue can be iead at any time and used as a iefei-
ence foi both the HSI section and the HSO section.
Timei 1 can cause an inteiiupt when it oveifIows, and
cannot be modified oi stopped without iesetting the
entiie chip. Timei 2 is ieaIIy an event countei since it
uses an exteinaI cIock souice. Like Timei 1, it is 16-bits
wide, can be iead at any time, can be used with the
HSO section, and can geneiate an inteiiupt when it
oveifIows. ContioI of Timei 2 is Iimited to inciement-
ing it and iesetting it. Specific vaIues can not be wiitten
to it.
AIthough the 8096 has onIy two timeis, the timei fIexi-
biIity is equaI to a unit with many timeis thanks to the
HSIO unit. The HSI enabIes one to measuie times of
exteinaI events on up to foui Iines using Timei 1 as a
timei base. The HSO unit can scheduIe and execute
inteinaI events and up to six exteinaI events based on
the vaIues in eithei Timei 1 oi Timei 2. The 8096 aIso
incIudes sepaiate, dedicated timeis foi the baud iate
geneiatoi and watchdog timei.
232 HSI
The HSI unit can be thought of as a message takei
which iecoids the Iine which had an event and the time
at which the event occuiied. Foui types of events can
tiiggei the HSI unit, as shown in the HSI bIock dia-
giam in Figuie 2-11. The HSI unit can measuie puIse
widths and iecoid times of events with a 2
2700617
Where each 2-bit mode control field
defines one of 4 possible modes
00 8 positive transitions
01 Each positive transition
10 Each negative transition
11 Every transition (positive and negative)
Figure 2-12 HSI Mode Register
11
AP-248
miciosecond iesoIution. It can Iook foi one of foui
events on each of foui Iines simuItaneousIy, based on
the infoimation in the HSI Mode iegistei, shown in
Figuie 2-12. The infoimation is then stoied in a seven
IeveI FIFO foi Iatei ietiievaI. Whenevei the FIFO con-
tains infoimation, the eaiIiest entiy is pIaced in the
hoIding iegistei. When the hoIding iegistei is iead, the
next vaIid piece of infoimation is Ioaded into it. Intei-
iupts can be geneiated by the HSI unit at the time the
hoIding iegistei is Ioaded oi when the FIFO has six oi
moie entiies.
233 HSO
Just as the HSI can be thought of as a message takei,
the HSO can be thought of as a message sendei. At
times deteimined by the softwaie, the HSO sends mes-
2700618
Figure 2-13 HSO Command Register
2700619
Figure 2-14 HSO Block Diagram
12
AP-248
sages to vaiious devices to have them tuin on, tuin off,
stait piocessing, oi ieset. Since the piogiammed times
can be iefeienced to eithei Timei 1 oi Timei 2, the
HSO makes the two timeis Iook Iike many. Foi exam-
pIe, if seveiaI events have to occui at specific times, the
HSO unit can scheduIe aII of the events based on a
singIe timei. The events that can be scheduIed to occui
and the foimat of the command wiitten to the HSO
Command iegistei aie shown in Figuie 2-13.
The softwaie timeis Iisted in the figuie aie actuaIIy 4
softwaie fIags in I/O Status Registei 1 (IOS1). These
fIags can be set, and optionaIIy cause an inteiiupt, at
any time based on Timei 1 oi Timei 2. In most cases
these timeis aie used to tiiggei inteiiupt ioutines which
must occui at ieguIai inteivaIs. A muItitask piocess
can easiIy be set up using the softwaie timeis.
A CAM (Content AddiessabIe Memoiy) fiIe is the
main component of the HSO. This fiIe stoies up to
eight events which aie pending to occui. Fveiy state
time one Iocation of the CAM is compaied with the
two timeis. Aftei 8 state times, (two micioseconds with
a 12 MHz cIock), the entiie CAM has been seaiched
foi time matches. If a match occuis the specified event
wiII be tiiggeied and that Iocation of the CAM wiII be
made avaiIabIe foi anothei pending event. A bIock dia-
giam of the HSO unit is shown in Figuie 2-14.
234 Serial Port
ContioIIing a device fiom a iemote Iocation is a simpIe
task that fiequentIy iequiies additionaI haidwaie with
many piocessois. The 8096 has an on-chip seiiaI poit to
ieduce the totaI numbei of chips iequiied in the system.
27006110
NOTE
TI and RI are cleared when SP

CON is read
Figure 2-15 Serial Port ControlStatus Register
13
AP-248
The seiiaI poit is simiIai to that on the MCS-51 piod-
uct Iine. It has one synchionous and thiee asynchio-
nous modes. In the asynchionous modes baud iates of
up to 187.5 Kbaud can be used, whiIe in the synchio-
nous mode iates up to 1.5 Mbaud aie avaiIabIe. The
chip has a baud iate geneiatoi which is independent of
Timei 1 and Timei 2, so using the seiiaI poit does not
take away any of the HSI, HSO oi timei fIexibiIity oi
functionaIity.
ContioI of the seiiaI poit is piovided thiough the
SPCON/SPSTAT (SeiiaI Poit CONtioI/SeiiaI Poit
STATus) iegistei. This iegistei, shown in Figuie 2-15,
has some bits which aie iead onIy and otheis which aie
wiite onIy. AIthough the functionaIity of the poit is
simiIai to that of the 8051, the names of some of the
modes and contioI bits aie diffeient. The way in which
the poit is used fiom a softwaie standpoint is aIso
sIightIy diffeient since RI and TI aie cIeaied aftei each
iead of the iegistei.
The foui modes of the seiiaI poit aie iefeiied to as
modes 0, 1, 2 and 3. Mode 0 is the synchionous mode,
and is commonIy used to inteiface to shift iegisteis foi
I/O expansion. In this mode the poit outputs a puIse
tiain on the TXD pin and eithei tiansmits oi ieceives
data on the RXD pin. Mode 1 is the standaid asyn-
chionous mode, 8 bits pIus a stop and stait bit aie sent
oi ieceived. Modes 2 and 3 handIe 9 bits pIus a stop and
stait bit. The diffeience between the two is, that in
Mode 2 the seiiaI poit inteiiupt wiII not be activated
unIess the ninth data bit is a one, in Mode 3 the intei-
iupt is activated whenevei a byte is ieceived. These two
modes aie commonIy used foi inteipiocessoi communi-
cation.
Using XTAL1
Mode 0
Baud
Rate
e
XTAL1 frequency
4(Ba1)
B i 0
Others
Baud
Rate
e
XTAL1 frequency
64(Ba1)
Using T2CLK
Mode 0
Baud
Rate
e
T2CLK frequency
B
B i 0
Others
Baud
Rate
e
T2CLK frequency
16B
B i 0
Note that B cannot equal 0 except when using
XTAL1 in other than mode 0
Figure 2-16 Baud Rate Formulas
Baud iates foi aII of the modes aie contioIIed thiough
the Baud Rate iegistei. This is a byte wide iegistei
which is Ioaded sequentiaIIy with two bytes, and intei-
naIIy stoies the vaIue as a woid. The Ieast significant
byte is Ioaded to the iegistei foIIowed by the most sig-
nificant. The most significant bit of the baud vaIue de-
teimines the cIock souice foi the baud iate geneiatoi. If
the bit is a one, the XTAL1 pin is used as the souice, if
it is a zeio, the T2 CLK pin is used. The foimuIas
shown in Figuie 2-16 can be used to caIcuIate the baud
iates. The vaiiabIe B is used to iepiesent the Ieast
significant 15 bits of the vaIue Ioaded into the baud iate
iegistei.
The baud iate iegistei vaIues foi common baud iates
aie shown in Figuie 2-17. These vaIues can be used
when XTAL1 is seIected as the cIock souice foi seiiaI
modes othei than Mode 0. The peicentage deviation
fiom theoieticaI is Iisted to heIp assess the ieIiabiIity of
a given setup. In most cases a seiiaI Iink wiII woik if
theie is Iess than a 2.5% diffeience between the baud
iates of the two systems. This is based on the assump-
tion that 10 bits aie tiansmitted pei fiame and the Iast
bit of the fiame must be vaIid foi at Ieast six-eights of
the bit time. If the two systems deviate fiom theoieticaI
by 1.25% in opposite diiections the maximum toIei-
ance of 2.5% wiII be ieached. Theiefoie, caution must
be used when the baud iate deviation appioaches
1.25% fiom theoieticaI. Note that an XTAL1 fiequen-
cy of 11.0592 MHz can be used with the tabIe vaIues
foi 11 MHz to piovide baud iates that have 0.0 peicent
deviation fiom theoieticaI. In most appIications, how-
evei, the accuiacy avaiIabIe when using an 11 MHz
input fiequency is sufficient.
SeiiaI poit Mode 1 is the easiest mode to use as theie is
IittIe to woiiy about except initiaIization and Ioading
and unIoading SBUF, the SeiiaI poit BUFfei. If paiity
is enabIed, (i.e., PFN
e
1), 7 bits pIus even paiity aie
used instead of 8 data bits. The paiity caIcuIation is
done in haidwaie foi even paiity. Modes 2 and 3 aie
simiIai to Mode 1, except that the ninth bit needs to be
contioIIed and iead. It is aIso not possibIe to enabIe
paiity in Mode 2. When paiity is enabIed in Mode 3 the
ninth bit becomes the paiity bit. If paiity is not enabIed,
(i.e., PFN
e
0), the TB8 bit contioIs the state of the
ninth tiansmitted bit. This bit must be set piioi to each
tiansmission. On ieception, if PFN
e
0, the RB8 bit
indicates the state of the ninth ieceived bit. If paiity is
enabIed, (i.e., PFN
e
1), the same bit is caIIed RPF
(Receive Paiity Fiioi), and is used to indicate a paiity
eiioi.
14
AP-248
XTAL1 Frequency
e
120 MHz
Baud Rate Baud Register Value Percent Error
192K 8009H
a
240
9600 8013H
a
240
4800 8026H
b
016
2400 804DH
b
016
1200 809BH
b
016
300 8270H 000
XTAL1 Frequency
e
110 MHz
192K 8008H
a
054
9600 8011H
a
054
4800 8023H
a
054
2400 8047H
a
054
1200 808EH
b
016
300 823CH
a
001
XTAL1 Frequency
e
100 MHz
192K 8007H
b
170
9600 800FH
b
170
4800 8020H
a
138
2400 8040H
b
016
1200 8081H
b
016
300 8208H
a
003
Figure 2-17 Baud Rate Values for 10 11 12 MHz
The softwaie used to communicate between piocessois
is simpIified by making use of Modes 2 and 3. In a basic
piotocoI the ninth bit is caIIed the addiess bit. If it is set
high then the infoimation in that byte is eithei the ad-
diess of one of the piocessois on the Iink, oi a com-
mand foi aII the piocessois. If the bit is a zeio, the byte
contains infoimation foi the piocessoi oi piocessois
pieviousIy addiessed. In standby mode aII piocessois
wait in Mode 2 foi a byte with the addiess bit set.
When they ieceive that byte, the softwaie deteimines if
the next message is foi them. The piocessoi that is to
ieceive the message switches to Mode 3 and ieceives
the infoimation. Since this infoimation is sent with the
ninth bit set to zeio, none of the piocessois set to Mode
2 wiII be inteiiupted. By using this scheme the oveiaII
CPU time iequiied foi the seiiaI poit is minimized.
A typicaI connection diagiam foi the muIti-piocessoi
mode is shown in Figuie 2-18. This type of communica-
ton can be used to connect peiipheiaIs to a desk top
computei, the axis of a muIti-axis machine, oi any oth-
ei gioup of miciocontioIIeis jointIy peifoiming a task.
15
AP-248
27006111
Figure 2-18 Multiprocessor Communication
Mode 0, the synchionous mode, is typicaIIy used foi
inteifacing to shift iegisteis foi I/O expansion. The
softwaie to contioI this mode invoIves the RFN (Re-
ceivei FNabIe) bit, the cIeaiing of the RI bit, and wiit-
ing to SBUF. To tiansmit to a shift iegistei, RFN is set
to zeio and SBUF is Ioaded with the infoimation. The
infoimation wiII be sent and then the TI fIag wiII be set.
Theie aie two ways to cause a ieception to begin. The
fiist is by causing a iising edge to occui on the RFN
bit, the second is by cIeaiing RI with RFN
e
1. In
eithei case, RI is set again when the ieceived byte is
avaiIabIe in SBUF.
235 A to D CONVERTER
AnaIog inputs aie fiequentIy iequiied in a miciocon-
tioIIei appIication. The 8097 has a 10-bit A to D con-
veitei that can use any one of eight input channeIs. The
conveisions aie done using the successive appioxima-
tion method, and iequiie 168 state times (42 miciosec-
onds with a 12 MHz cIock.)
The iesuIts aie guaianteed monotonic by design of the
conveitei. This means that if the anaIog input voItage
changes, even sIightIy, the digitaI vaIue wiII eithei stay
the same oi change in the same diiection as the anaIog
input. When doing piocess contioI aIgoiithms, it is fie-
quentIy the changes in inputs that aie iequiied, not the
absoIute accuiacy of the vaIue. Foi this ieason, even if
the absoIute accuiacy of a 10-bit conveitei is the same
as that of an 8-bit conveitei, the 10-bit monotonic con-
veitei is much moie usefuI.
Since most of the anaIog inputs which aie monitoied by
a miciocontioIIei change veiy sIowIy ieIative to the 42
miciosecond conveision time, it is acceptabIe to use a
capacitive fiItei on each input instead of a sampIe and
hoId. The 8097 does not have an inteinaI sampIe and
hoId, so it is necessaiy to ensuie that the input signaI
does not change duiing the conveision time. The input
to the A/D must be between ANOND and VRFF.
ANOND must be within a few miIIivoIts of VSS and
VRFF must be within a few tenths of a voIt of VCC.
Using the A to D conveitei on the 8097 can be a veiy
Iow softwaie oveihead task because of the inteiiupt and
HSO unit stiuctuie. The A to D can be staited by the
HSO unit at a pieset time. When the conveision is com-
pIete it is possibIe to geneiate an inteiiupt. By using
these featuies the A to D can be iun undei compIete
inteiiupt contioI. The A to D can aIso be diiectIy
16
AP-248
AD Command Register
27006112
AD Result Register
27006113
Figure 2-19 A to D ResultCommand Register
contioIIed by softwaie fIags which aie Iocated in the
AD
-
RFSULT/AD
-
COMMAND Registei, shown
in Figuie 2-19.
236 PWM REGISTER
AnaIog outputs aie just as impoitant as anaIog inputs
when connecting to a piece of equipment. Tiue digitaI
to anaIog conveiteis aie difficuIt to make on a micio-
piocessoi because of aII of the digitaI noise and the
necessity of pioviding an on chip, ieIativeIy high cui-
ient, iaiI to iaiI diivei. They aIso take up a faii amount
of siIicon aiea which can be bettei used foi othei fea-
tuies. The A to D conveitei does use a D to A, but the
cuiients invoIved aie veiy smaII.
Foi many appIications an anaIog output signaI can be
iepIaced by a PuIse Width ModuIated (PWM) signaI.
This signaI can be easiIy geneiated in haidwaie, and
takes up much Iess siIicon aiea than a tiue D to A. The
signaI is a vaiiabIe duty cycIe, fixed fiequency wave-
foim that can be integiated to piovide an appioxima-
tion to an anaIog output. The fiequency is fixed at a
peiiod of 64 micioseconds foi a 12 MHz cIock speed.
ContioIIing the PWM simpIy iequiies wiiting the de-
siied duty cycIe vaIue (an 8-bit vaIue) to the PWM
Registei. Some typicaI output wavefoims that can be
geneiated aie shown in Figuie 2-20.
Conveiting the PWM signaI to an anaIog signaI vaiies
in difficuIty, depending upon the iequiiements of the
system. Some systems, such as motois oi switching
powei suppIies actuaIIy iequiie a PWM signaI, not a
tiue anaIog one. Foi many othei cases it is necessaiy
onIy to ampIify the signaI so that it switches iaiI-to-iaiI,
and then fiItei it. Switching iaiI-to-iaiI means that the
output of the ampIifiei wiII be a iefeience vaIue when
the input is a IogicaI one, and the output wiII
17
AP-248
be zeio when the input is a IogicaI zeio. The fiItei can
be a simpIe RC netwoik oi an active fiItei. If a Iaige
amount of cuiient is needed a buffei is aIso iequiied.
Foi Iow output cuiients, (Iess than 100 micioamps oi
so), the ciicuit shown in Figuie 2-21 can be used.
The RC netwoik deteimines how quiet the output is,
but the quietei the output, the sIowei it can change.
The design of high accuiacy voItage foIIoweis and ac-
tive fiIteis is beyond the scope of this papei, howevei
many books on the subject aie avaiIabIe.
27006114
Figure 2-20 PWM Output Waveforms
27006115
This resistor limits Rise Time to reduce spikes and high frequency noise
Figure 2-21 PWM to Analog Conversion Circuitry
18
AP-248
30 BASIC SOFTWARE EXAMPLES
The exampIes in this section show how to use each I/O
featuie individuaIIy. FxampIes of using moie than one
featuie at a time aie desciibed in section 4. AII of the
exampIes in this ap-note aie set up to be used as Iisted.
If iun thiough ASM96 they wiII Ioad and iun on an
SBF-96. In oidei to insuie that the piogiams woik, the
stack pointei is initiaIized at the beginning of each pio-
giam. If the piogiams aie going to be used as moduIes
of othei piogiams, the stack pointei initiaIization
shouId onIy be used at the beginning of the main pio-
giam.
To avoid iepetitive decIaiations the incIude fiIe DF-
MO96.INC, shown in Listing 3-1, is used. ASM-96
wiII inseit this fiIe into the code fiIe whenevei the diiec-
tive INCLUDF DFMO96.INC is used. The fiIe con-
tains the definitions foi the SFRs and othei vaiiabIes.
The incIude statement has been pIaced in aII of the ex-
ampIes. It shouId be noted that some of the Iab-
eIs in this fiIe aie diffeient fiom those in the fiIe
8096.INC that is piovided in the ASM-96 package.
31 Using the 8096s Processing
Section
311 TABLE INTERPOLATION
A good way of incieasing speed foi many piocessing
tasks is to use tabIe Iookup with inteipoIation. This can
eIiminate Iengthy caIcuIations in many aIgoiithms. Fie-
quentIy it is used in piogiams that geneiate sine wave-
foims, use exponents in caIcuIations, oi iequiie some
non-Iineai function of a given input vaiiabIe. TabIe
Iookup can aIso be used without inteipoIation to detei-
mine the output state of I/O devices foi a given state of
a set of input devices. The pioceduie is aIso a good
exampIe of 8096 code as it uses many of the softwaie
featuies. Two ways of making a Iookup tabIe aie de-
sciibed, one way uses moie caIcuIation time, the second
way uses moie tabIe space.
27006116
Listing 3-1 Include File DEMO96INC
19
AP-248
In both methods the pioceduie is simiIai. VaIues of a
function aie stoied in memoiy foi specific input vaIues.
To compute the output function foi an input that is not
Iisted, a Iineai appioximation is made based on the
neaiest inputs and neaiest outputs. As an exampIe, con-
sidei the tabIe beIow.
If the input vaIue was one of those Iisted then theie
wouId be no piobIem. UnfoitunateIy the ieaI woiId is
nevei so kind. The input numbei wiII piobabIy be 259
oi something simiIai. If this is the case Iineai inteipoIa-
tion wouId piovide a ieasonabIe iesuIt. The foimuIa is:
Delta Out e
UpperOutput-Lower Output
Upper Input-Lower Input
(Actual Input-Lower Input)
Actual Output e Lower Output a Delta Out
For the value of 259 the solution is
Delta Out e
900-400
300-200
(259-200) e
500
100
59 e 5 59 e 295
Actual Output e 400 a 295 e 695
To make the aIgoiithm easiei, (and theiefoie fastei), it
is appiopiiate to Iimit the iange and accuiacy of the
function to onIy what is needed. It is aIso advantageous
to make the input step (Uppei Input-Lowei Input)
equaI to a powei of 2. This aIIows the substitution of
muItipIe iight shifts foi a divide opeiation, thus speed-
ing up thioughput. The 8096 aIIows muItipIe aiithmetic
iight shifts with a singIe instiuction pioviding a veiy
fast divide if the divisoi is a powei of two.
Foi the puipose of an exampIe, a piogiam with a 12-bit
output and an 8-bit input has been wiitten. An input
step of 16 (24) was seIected. To covei the input iange
17 woids aie needed, 255/16
a
1 woid to handIe vaI-
ues in the Iast 15 bytes of input iange. AIthough onIy
12 bits aie iequiied foi the output, the 16-bit aichitec-
tuie offeis no penaIty foi using 16 instead of 12 bits.
The piogiam foi this exampIe, shown in Listing 3-2,
uses the definitions and equates fiom Listing 3-1, onIy
the additionaI equates and definitions aie shown in the
code.
Input Value Relative Table Address Table Value
100 0001H 100
200 0002H 400
300 0003H 900
400 0004H 1600
27006117
Listing 3-2 ASM-96 Code for Table Lookup Routine 1
20
AP-248
27006118
Listing 3-2 ASM-96 Code for Table Lookup Routine 1 (Continued)
If the function is known at the time of wiiting the soft-
waie it is aIso possibIe to caIcuIate in advance the
change in the output function foi a given change in the
input. This method can save a divide and a few othei
instiuctions at the expense of doubIing the size of the
Iookup tabIe. Theie aie many appIications wheie time
is ciiticaI and code space is oveiIy abundant. In these
cases the code in Listing 3-3 wiII woik to the same
specifications as the pievious exampIe.
27006119
Listing 3-3 ASM-96 Code For Table Lookup Routine 2
21
AP-248
27006120
Listing 3-3 ASM-96 Code for Table Lookup Routine 2 (Continued)
By making use of the second Iookup tabIe, one woid of
RAM was saved and 16 state times. In most cases this
time savings wouId not make much of a diffeience, but
when pushing the piocessoi to the Iimit, micioseconds
can make oi bieak a design.
312 PLM-96
InteI piovides high IeveI Ianguage suppoit foi most of
its micio piocessois and miciocontioIIeis in the foim of
PL/M. SpecificaIIy, PL/M iefeis to a famiIy of Ian-
guages, each simiIai in syntax, but speciaIized foi the
device foi which it geneiates code. The PL/M syntax is
simiIai to PL/1, and is easy to Ieain. PLM-96 is the
veision of PL/M used foi the 8096. It is veiy code
efficient as it was wiitten specificaIIy foi the MCS-96
famiIy. PLM-96 most cIoseIy iesembIes PLM-86, aI-
though it has bit and I/O functions simiIai to PLM-51.
One Iine of PL/M-code can take the pIace of many
Iines of assembIy code. This is advantageous to the pio-
giammei, since code can usuaIIy be wiitten at a set
numbei of Iines pei houi, so the Iess Iines of code that
need to be wiitten, the fastei the task can be compIeted.
If the fiist exampIe of inteipoIation is consideied, the
PLM-96 code wouId be wiitten as shown in Listing 3-4.
Note that veision 1.0 of PLM-96 does not suppoit 32-
bit iesuIts of 16 by 16 muItipIies, so the ASM-96 pioce-
duie DMPY is used. Pioceduie DMPY, shown in
Listing 3-5, must be assembIed and Iinked with the
compiIed PLM-96 piogiam using RL-96, the ieIocatoi
and Iinkei. The command Iine to be used is:
RL96 PLMFX1.OBJ, DMPY.OBJ, PLM96.LIB &
to PLMOUT.OBJ ROM (2080H-3FFFH)
22
AP-248
27006121
Listing 3-4 PLM-96 Code For Table Lookup Routine 1
27006122
Listing 3-5 32-Bit Result Multiply Procedure For PLM-96
23
AP-248
Using PLM, code iequiies Iess Iines, is much fastei to
wiite, and easiei to maintain, but may take sIightIy
Iongei to iun. Foi this exampIe, the assembIy code gen-
eiated by the PLM-96 compiIei takes 56.75 miciosec-
onds to iun instead of 30.75 micioseconds. If PLM-96
peifoimed the 32-bit iesuIt muItipIy instead of using
the ASM-96 ioutine the PLM code wouId take 41.5
micioseconds to iun. The actuaI code Iistings aie
shown in Appendix A.
32 Using the IO Section
321 USING THE HSI UNIT
One of the most fiequent uses of the HSI is to measuie
the time between events. This can be used foi fiequency
deteimination in Iab instiuments, oi speed/acceIeiation
infoimation when connected to puIse type encodeis.
The code in Listing 3-6 can be used to deteimine the
high and Iow times of the signaIs on two Iines. This
code can be easiIy expanded to 4 Iines and can aIso be
modified to woik as an inteiiupt ioutine.
FiequentIy it is aIso desiied to keep tiack of the num-
bei of events which have occuiied, as weII as how often
they aie occuiiing. By using a softwaie countei this
featuie can be added to the above code. This code de-
pends on the softwaie iesponding to the change in Iine
state befoie the Iine changes again. If this cannot be
guaianteed then it may be necessaiy to use 2 HSI Iines
foi each incoming Iine. In this case one HSI Iine wouId
Iook foi faIIing edges whiIe the othei Iooks foi iising
edges. The code in Listing 3-7 incIudes both the countei
featuie and the edge detect featuie.
The uses foi this type of ioutine aie aImost endIess. In
instiumentation it can be used to deteimine fiequency
on input Iines, oi peihaps baud iate foi a seIf adjusting
seiiaI poit. Section 4.2 contains an exampIe of making a
softwaie seiiaI poit using the HSI unit. Inteifacing to
some foim of mechanicaIIy geneiated position infoima-
tion is a veiy fiequent use of the HSI. The appIications
in this categoiy incIude motoi contioI, piecise position-
ing (piint heads, disk diives, etc.), engine contioI and
27006123
Listing 3-6 Measuring Pulses Using The HSI Unit
24
AP-248
tiansmission contioI. The HSI unit is used extensiveIy
in the exampIe in section 4.3.
322 USING THE HSO UNIT
AIthough the HSO has many uses, the best exampIe is
that of a muItipIe PWM output. This piogiam, shown
in Listing 3-8, is simpIe enough to be easiIy undeistood,
yet it shows how to use the HSO foi a task which can
be compIex. In oidei foi this piogiam to opeiate, an-
othei piogiam needs to set up the on and off time vaii-
abIes foi each Iine. The piogiam aIso iequiies that a
HSO Iine not change so quickIy that it changes twice
between consecutive ieads of I/O Status Registei 0,
(IOS0).
A veiy eye catching exampIe can be made by having the
piogiam output wavefoims that vaiy ovei time. The
diivei ioutine in Listing 3-10 can be Iinked to the above
piogiam to piovide this function. Linking is accom-
pIished using RL96, the ieIocatabIe Iinkei foi the 8096.
Infoimation foi using RL96 can be found in the
MCS-96 UtiIities Useis Ouide, Iisted in the bibIiogia-
phy. In oidei foi the piogiam to Iink, the iegistei dec-
27006124
Listing 3-7 Enhanced HSI Pulse Measurement Routine
25
AP-248
27006125
Listing 3-8 Generating a PWM with the HSO
26
AP-248
Iaiation section (i.e., the section between RSFO and
CSFO) in Listing 3-8 must be changed to that in
Listing 3-9.
The diivei ioutine simpIy changes the duty cycIe of the
wavefoim and sets the second HSO output to a fie-
quency twice that of the fiist one. A sIightIy diffeient
diivei ioutine couId easiIy be the basis foi a switching
powei suppIy oi a vaiiabIe fiequency/vaiiabIe voItage
motoi diivei. The Iisting of the diivei ioutine is shown
in Listing 3-10.
27006126
Listing 3-9 Changes to Declarations for HSO Routine
27006127
Listing 3-10 Driver Module for HSO PWM Program
27
AP-248
27006128
Listing 3-10 Driver Module for HSO PWM Program (Continued)
Since the 8096 needs to keep tiack of events which of-
ten iepeat at set inteivaIs it is convenient to be abIe to
have Timei 2 act as a piogiammabIe moduIo countei.
Theie aie seveiaI ways of doing this. The fiist is to
piogiam the HSO to ieset Timei 2 when Timei 2
equaIs a set vaIue. A softwaie timei set to inteiiupt at
Timei 2 equaIs zeio couId be used to ieIoad the CAM.
This softwaie method takes up two Iocations in the
CAM and does not synchionize Timei 2 to the exteinaI
woiId.
To synchionize Timei 2 exteinaIIy the T2 RST (Timei
2 ReSeT) pin can be used. In this way Timei 2 wiII get
ieset on each iising edge of T2 RST. If it is desiied to
have an inteiiupt geneiated and time iecoided when
Timei 2 gets ieset, the signaI foi its ieset can be taken
fiom HSI.0 instead of T2RST. The HSI.0 pin has its
own inteiiupt vectoi which functions independentIy of
the HSI unit.
Anothei option avaiIabIe is to use the HSI.1 pin to
cIock Timei 2. By using this appioach it is possibIe to
use the HSI to measuie the peiiod of events on the
input to Timei 2. If both of the HSI pins aie used
instead of the T2RST and T2CLK pins the HSIO unit
can keep tiack of speed and position of the iotating
device with veiy IittIe softwaie oveihead. This type of
setup is ideaI foi a system Iike the one shown in Figuie
3-1, and simiIai to the one used in section 4.3.
In this system a sequence of events is iequiied based on
the position of the geai which iepiesents any piece of
iotating machineiy. Timei 2 hoIds the count of the
numbei of tooth edges passed since the index maik. By
using HSI.1 as the input to Timei 2, instead of T2
CLK, it is possibIe to deteimine tooth count and time
infoimation thiough the HSI. Fiom this infoimation
instantaneous veIocity and acceIeiation can be caIcuIat-
ed. Having the tooth edge count in Timei 2 means
27006129
Figure 3-1 Using the HSIO to Monitor Rotating Machinery
28
AP-248
that the HSO unit can be used to initiate the desiied
tasks at the appiopiiate tooth count. The inteiiupt iou-
tine initiated by HSI.0 can be used to peifoim any soft-
waie task iequiied eveiy ievoIution. In this system, the
oveihead which wouId noimaIIy iequiie extensive soft-
waie has been done with the haidwaie on the 8096,
thus making moie softwaie time avaiIabIe foi contioI
piogiams.
323 USING THE SERIAL PORT IN MODE 1
Mode 1 of the seiiaI poit suppoits the basic asynchio-
nous 8-bit piotocoI and is used to inteiface to most
CRTs and piinteis. The exampIe in Listing 3-11 shows
a simpIe ioutine which ieceives a chaiactei and then
tiansmits the same chaiactei. The code is set up so that
minoi modifications couId make it iun on an inteiiupt
basis. Note that it is necessaiy to set up some fIags as
initiaI conditions to get the ioutine to iun piopeiIy. If it
was desiied to send 7 bits of data pIus paiity instead of
8 bits of data the PFN bit wouId be set to a one. Intei-
piocessoi communication, as desciibed in section 2.3.4,
can be set up by simpIy adding code to change RB8 and
the poit mode to the Iisting beIow. The haidwaie
shown in Figuie 3-2 can be used to conveit the Iogic
IeveI output of the 8096 to g12 oi 15 voIt IeveIs to
connect to a CRT. This ciicuit has been found to woik
with most RS-232 devices, aIthough it does not con-
foim to stiict RS-232 specifications. If tiue RS-232
confoimance is iequiied then any standaid RS-232
diivei can be used.
27006130
Listing 3-11 Using the Serial Port in Mode 1
29
AP-248
27006131
Listing 3-11 Using the Serial Port in Mode 1 (Continued)
27006132
Figure 3-2 Serial Port Level Conversion
30
AP-248
324 USING THE A TO D
The code in Listing 3-12 makes use of the softwaie fIags
to impIement a non-inteiiupt diiven ioutine which
scans A to D channeIs 0 thiough 3 and stoies them as
woids in RAM. An inteiiupt diiven ioutine is shown in
section 4.1. When using the A to D it is impoitant to
aIways iead the vaIue using the byte iead commands,
and to give the conveitei 8 state times to stait conveit-
ing befoie ieading the status bit.
Since theie is no sampIe and hoId on the A to D con-
veitei it may be desiiabIe to use an RC fiItei on each
input. A 100X iesistoi in seiies with a 0.22 uf capacitoi
to giound has been used successfuIIy in the Iab. This
ciicuit gives a time constant of aiound 22 micioseconds
which shouId be Iong enough to get iid of most noise,
without oveiIy sIowing the A to D iesponse time.
40 ADVANCED SOFTWARE
EXAMPLES
Using the 8096 foi appIications which consist onIy of
the biief exampIes in the pievious section does not
ieaIIy make use of its fuII capabiIities. The foIIowing
exampIes use some of the code bIocks fiom the pievious
section to show how seveiaI I/O featuies can be used
togethei to accompIish a piacticaI task. Thiee exampIes
wiII be shown. The fiist is simpIy a combination of sev-
eiaI of the section 3 exampIes iun undei an inteiiupt
system. Next, a softwaie seiiaI poit using the HSIO
unit is desciibed. The concIuding exampIe is one of in-
teifacing the HSI unit to an opticaI encodei to contioI a
motoi.
41 Simultaneous IO Routines under
Interrupt Control
A foui channeI anaIog to PWM conveitei can easiIy be
made using the 8096. In the exampIe in Listing 4 ana-
Iog channeIs aie iead and 3 PWM wavefoims aie gen-
eiated on the HSO Iines and one on the PWM pin.
Fach anaIog channeI is used to set the duty cycIe of its
associated output pin. The inteiiupt system keeps the
whoIe piogiam humming, pioviding time foi a back-
giound task which is simpIy a 32 bit softwaie countei.
To show which ioutines aie executing and in which
27006133
Listing 3-12 Scanning the A to D Channels
31
AP-248
oidei, Poit 1 output pins aie used to indicate the cui-
ient status of each task. The actuaI code Iisting is in-
cIuded in Appendix B.
The initiaIization section, shown in Listing 4-1a, cIeais
a few vaiiabIes and then Ioads the fiist set of on and off
times to the HSO unit. Note that 8 state times must
be waited between consecutive Ioads of the HSO. If this
is not done it is possibIe to oveiwiite the contents of the
CAM hoIding iegistei. An A/D inteiiupt is foiced by
setting the bit in the Inteiiupt Pending iegistei. This
causes the fiist A/D inteiiupt to occui just aftei the
Inteiiupt Mask iegistei is set and inteiiupts aie en-
abIed.
Listing 4-1 Using Multiple IO Devices
27006134
Listing 4-1a Initializing the A to D to PWM Program
32
AP-248
27006135
Listing 4-1a Initializing the A to D to PWM program (Continued)
27006136
Listing 4-1b Interrupt Driven HSO Routine
33
AP-248
27006137
Listing 4-1c Interrupt Driven A to D Routine
The HSO ioutine shown in Listing 4-1b is sIightIy dif-
feient than the one in section 3. AII of the HSO Iines
tuin on at the same time, onIy the tuin-off-time is vai-
ied between Iines. This action is what is most common-
Iy iequiied foi muItipIe PWM outputs and simpIifies
the softwaie. A compaiison is made between Timei1
and the next HSO tuin on time at the beginning of the
ioutine. If the next tuin on time has passed, then the
on-times aie Ioaded into the CAM, otheiwise the off
times aie Ioaded.
The maximum numbei of events in the CAM at any
given time is 7. This occuis when the fiist Iine to tuin
off does so, causing the off-times foi aII of the Iines to
be Ioaded. Foi two of the Iines theie wiII be an offtime,
an on-time, and the just Ioaded off-time. The othei Iine
(the one that just tuined off) wiII have onIy the on-time
and the just Ioaded off-time.
A/D conveisions aie peifoimed by the code in Listing
4-1c about eveiy 60 micioseconds, 42 foi the convei-
sion, the iest foi oveihead. The A/D ioutine sets up the
HSO and PWM on and off times. Since the A/D
has a ten bit output, the most significant 8 bits aie
iounded up oi down based on the Ieast significant two
bits.
42 Software Serial Port Using the
HSIO Unit
Theie aie many systems which iequiie moie than one
seiiaI poit, an exampIe is a system which must commu-
nicate with othei computeis and have an additionaI
poit foi a IocaI consoIe. If the on-boaid UART is being
used as an intei-piocessoi Iink, the HSIO unit can be
used to inteiface the 8096 to an additionaI asynchio-
nous Iine.
Figuie 4-1 shows the foimat of a standaid 10-bit asyn-
chionous fiame. The stait bit is used to synchionize the
ieceivei to the tiansmittei, at the Ieading edge of the
START bit the ieceivei must set up its timing Iogic to
sampIe the incoming Iine in the centei of each bit. FoI-
Iowing the stait bit aie the eight data bits which aie
tiansmitted Ieast significant bit fiist. The STOP bit is
set to the opposite state of the START bit to guai-
34
AP-248
27006138
Figure 4-1 10-bit Asynchronous Frame
antee that the Ieading edge of the START bit wiII cause
a tiansition on the Iine, it aIso piovides foi a dead time
on the Iine so that the ieceivei can maintain its syn-
chionization.
The iemaindei of this section wiII show how a fuII-du-
pIex asynchionous poit can be buiIt fiom the HSIO
unit. Theie aie foui sections to this code:
1. Inteiface ioutines. These ioutines piovide a pioce-
duiaI inteiface between the inteiiupt diiven coie of
the softwaie seiiaI poit and the iemaindei of the ap-
pIication softwaie.
2. InitiaIization ioutine. This ioutine is caIIed duiing
the initiaIization of the oveiaII system and sets up the
vaiious vaiiabIes used by the softwaie poit.
3. Tiansmit ISR. This ioutine iuns as an ISR (inteiiupt
seivice ioutine) in iesponse to an HSO inteiiupt in-
teiiupt. Its function is to seiiaIize the data passed to
it by the inteiface ioutines.
4. Receive ISRs. Theie aie two ISRs invoIved in the
ieceive piocess. One of them iuns in iesponse to an
HSI inteiiupt and is used to synchionize the ieceive
piocess at the Ieading edge of the stait bit. The sec-
ond ieceive ISR iuns in iesponse to an HSO geneiat-
ed softwaie timei inteiiupt, this ioutine is scheduIed
to iun at the centei of each bit and is used to deseii-
aIize the incoming data.
The ioutines shaie the set of vaiiabIes that aie shown in
Listing 4-2. These vaiiabIes shouId be accessed onIy by
the ioutines which make up the softwaie seiiaI poit.
27006139
Listing 4-2 Software Serial Port Declarations
35
AP-248
The tabIe aIso shows the decIaiations foi the com-
mands issued to the HSO unit. In this exampIe HSI.2 is
used foi ieceive data and HSO.5 is used foi tiansmit
data, aIthough othei HSI and HSO Iines couId have
been used.
The inteiface ioutines aie shown in Listing 4-3. Data is
passed to the poit by pushing the eight-bit chaiactei
into the stack and caIIing char

out, which waits foi

any in-piocess tiansmission to compIete and stoies the
chaiactei into the vaiiabIe serial

out. As the data is

stoied the START and STOP bits aie added to the data
bits. The ioutine charin is caIIed when the appIica-
tion softwaie iequiies a chaiactei fiom the poit. The
data is ietuined in the ax iegistei in confoimance to
PLM 96 caIIing conventions. The ioutine csts can be
caIIed to deteimine if a chaiactei is avaiIabIe at the poit
befoie caIIing char

in. (If no chaiactei is avaiIabIe

char

in wiII wait indefiniteIy).

The initiaIization ioutine is shown in Listing 4-4. This
ioutine is caIIed with the iequiied baud iate in the
27006140
Listing 4-3 Software Serial Port Interface Routines
27006141
Listing 4-4 Software Serial Port Initialization Routine
36
AP-248
stack, it caIcuIates the bit time fiom the baud iate and
stoies it in the vaiiabIe baud

count in units of TIM-

FR1 ticks. An HSO command is issued which wiII initi-
ate the tiansmit piocess and then the iemaindei of the
vaiiabIes owned by the poit aie initiaIized. The ioutine
init

receive is caIIed to setup the HSI unit to Iook foi

the Ieading edge of the START bit.
The tiansmit piocess is shown in Listing 4-5. The HSO
unit is used to geneiate an output command to the
tiansmit pin once pei bit time. If the serial

out iegis-
tei is zeio a MARK (idIe condition) is output. If the
serial

out iegistei contains data then the Ieast sig-

nificant bit is output and the iegistei shifted iight one
pIace. The fiaming infoimation (START and STOP
bits) aie appended to the actuaI data by the inteiface
ioutines. Note that this ioutine wiII be executed once
pei bit time whethei oi not data is being tiansmitted. It
wouId be possibIe to use this ioutine foi additionaI Iow
iesoIution timing functions with minimaI oveihead.
The ieceive piocess consists of an initiaIization ioutine
and two inteiiupt seivice ioutines, hsi

isr and soft-

ware

timer

isr. The Iistings of these ioutines aie

shown in Listings 4-6a,4-6b, and 4-6c iespectiveIy. The
27006142
Listing 4-5 Software Serial Port Transmit Process
Listing 4-6 Receive Process
27006143
Listing 4-6a Software Serial Port Receive Initialization
37
AP-248
27006144
Listing 4-6b Software Serial Port Start Bit Detect
27006145
Listing 4-6c Software Serial Port Data Reception
38
AP-248
stait is detected by the hsi

isr which scheduIes a soft-

waie timei inteiiupt in one-haIf of a bit time. This fiist
sampIe is used to veiify that the START bit has not
ended piematuieIy (a piotection against a noisy Iine).
The softwaie timei seivice ioutine uses the vaiiabIe
rcve

state to deteimine whethei it shouId check foi a

vaIid START bit, deseiiaIize data, oi check foi a vaIid
STOP bit. When a compIete chaiactei has been ie-
ceived it is moved to the ieceive buffei and init

receive
is caIIed to set up the ieceive piocess foi the next chai-
actei. This ioutine is aIso caIIed when an eiioi (e.g.,
invaIid START bit) is detected.
Appendix C contains the compIete Iisting of the iou-
tines and the simpIe Ioop which was used to initiaIize
them and veiify theii opeiation. The test was iun foi
seveiaI houis at 9600 baud with no appaient maIfunc-
tion of the poit.
43 Interfacing an Optical Encoder to
the HSI Unit
OpticaI encodeis aie among one of the moie popuIai
devices used to deteimine position of iotating equip-
ment. These devices output two puIse tiains with edges
that occui fiom 2 to 4000 times a ievoIution.
FiequentIy theie is a thiid Iine which geneiates one
puIse pei ievoIution foi indexing puiposes. Figuie 4-2
shows a six Iine encodei and typicaI wavefoims. As can
be seen, the two wavefoims piovide the abiIity to detei-
mine both position and diiection. Since a miciocontioI-
Iei can peifoim ieaI time caIcuIations it is possibIe to
deteimine veIocity and acceIeiation fiom the position
and time infoimation.
Inteifacing to the encodei can be an inteiesting piob-
Iem, as it iequiies connecting mechanicaIIy geneiated
eIectiicaI signaIs to the HSI unit. The piobIems aiise
because it is difficuIt to obtain the exact natuie of the
signaIs undei aII conditions.
The equipment used in the Iab was a Pittman 9400 se-
iies geaimotoi with a 600 Iine opticaI encodei fiom
Veinitech. The encodei has to be caiefuIIy attached to
the shaft to minimize any iunout oi endpIay. Foitu-
nateIy, Pitmann has staited maiketing theii motois
with baII beaiings and opticaI encodeis aIieady in-
staIIed. It is iecommended that the encodei be mounted
to the motoi using the exact specifications of the encod-
ei manufactuiei and/oi a good machine shop.
27006146
Inside track generates Phase A Outside track generates Phase B
Figure 4-2 Optical Encoder and Waveforms
39
AP-248
DigitaI fiIteiing exteinaI to the 8096 is used on the en-
codei signaIs. The ideaIized signaIs coming fiom the
encodei and aftei the digitaI fiItei aie shown in Figuie
4-3. The ciicuitiy connecting the encodei to the 8096
iequiies onIy two chips. A one-shot constiucted of
XOR gates geneiates puIses on each edge of each sig-
naI. The puIses geneiated by Phase A aie used to cIock
the signaI fiom Phase B and vice veisa. The haidwaie is
shown in Figuie 4-4. CMOS paits aie used to ieduce
Ioading on the encodei so that buffeis aie not needed.
Note that T2CLK is cIocked on both edges of both
fiIteied phases.
By using this method iepetitive edges on a singIe phase
without an edge on the othei phase wiII not be passed
on to the 8096. Repetitive edges on a phase can occui
when the motoi is stopped and vibiates oi when it is
changing diiection. The digitaI fiIteiing technique caus-
es a IittIe moie deIay in the signaI at sIow speeds than
an anaIog fiItei wouId, but the simpIicity tiade off is
woithwhiIe. The net effect of digitaI fiIteiing is Iosing
the abiIity to deteimine the fiist edge aftei a diiection
change. This does not affect the count since the fiist
edge in both diiections is Iost.
If it is desiied to deteimine when each edge occuis be-
foie fiIteiing, the encodei outputs can be attached di-
iectIy to the 8096. As these wouId be input signaIs, Poit
0 is the most IikeIy choice foi connection. It wouId not
be iequiied to connect these Iines to the HSI unit, as
the infoimation on them wouId onIy be needed when
the motoi is going veiy sIowIy.
The motoi is diiven using the PWM output pin foi
powei contioI and a poit pin foi diiection contioI. The
8096 diives a 7438 which diives 2 opto-isoIatois. These
in tuin diive two VFFTs. A MOV (MetaI Oxide Vaiis-
toi, a type of tiansient absoibei) is used to piotect the
VFFTs, and a capacitoi fiIteis the PWM to get the best
motoi peifoimance. Figuie 4-5 shows the diivei cii-
cuitiy. To avoid noise getting into the 8096 system, the
g15 voIt powei suppIy is isoIated fiom the 8096 Iogic
powei suppIy.
This is the extent of the exteinaI ciicuitiy iequiied foi
this exampIe. AII of the counting and diiection detec-
tion aie done by the 8096. Theie aie two sections to the
exampIe: diiving the motoi and inteifacing to the en-
codei. The motoi diivei uses piopoitionaI contioI with
27006147
NOTES
Phase A is Phase A clocked by Phase B
Phase B is Phase B clocked by Phase A
Figure 4-3 Filtered Encoder Waveforms
40
AP-248
some modifications and a biaking aIgoiithm. Since the
main point of this exampIe is I/O inteifacing, the mo-
toi diivei wiII be biiefIy desciibed at the end of this
section.
In oidei to inteiface to the encodei it is necessaiy to
know the types of wavefoims that can be expected. The
motoi was acceIeiated and deceIeiated many times us-
ing diffeient maximum voItages. It was found that the
27006148
Figure 4-4 Schematic of Optical Encoder to 8096 Interface
27006149
Figure 4-5 Motor Driver Circuitry
41
AP-248
motoi wouId deceIeiate smoothIy untiI the time be-
tween encodei edges was aiound 100 micioseconds. At
this point the motoi wouId eithei continue to deceIeiate
sIowIy, oi wouId suddenIy stop and ieveise. The Iattei
case is the one that was most piobIematic.
Aftei a biief oveiview, each section of the piogiam wiII
be desciibed sepaiateIy, with the compIete Iisting in-
cIuded in the Appendix D. In oidei to make debugging
easiei, as weII as to piovide insight into how the pio-
giam is woiking, I/O poit 1 is used to indicate the
piogiam status. This infoimation consists of which iou-
tine the piogiam is in and undei which mode it is opei-
ating. The main piogiam sections aie: Main Ioop, HSI
inteiiupt, Timei 2 check, and Motoi diive. Theie aie
aIso minoi sections such as initiaIization, timei ovei-
fIow handIing, and softwaie timei handIing. Tying ev-
eiything togethei is some oveihead and gIue. Wheie the
gIue is not obvious it wiII be discussed, otheiwise it can
be deiived fiom the Iistings.
The piogiam is a main Ioop which does nothing except
seive as a pIace foi the piogiam to go when none of the
inteiiupt ioutines aie being iun. AII of the piocessing is
done on an inteiiupt basis.
Theie aie thiee basic softwaie modes which aie in-
voked depending on the speed of the motoi. The modes
iefeiied to as 0, 1 and 2, in oidei fiom sIowest to fastest
opeiation. When the piogiam is iunning the opeiating
mode is indicated by the Iowei 2 bits of Poit 1, with the
foIIowing coding:
P10 P11 Mode Description
0 0 0 HSI looks at every edge
1 0 1 HSI looks at Phase A edges only
0 1 2 Timer 2 used instead of HSI
1 1 2 (alternate form of above)
The exampIe is easiest to see if mode 2 is desciibed fiist,
foIIowed by mode 1 then mode 0. In mode 2 Timei 2 is
used to count edges on the incoming signaI. A softwaie
timei ioutine, which is actuaIIy iun using HSO.0, uses
the Timei 2 vaIue to update a LONO (32-bit) softwaie
countei IabeIed POSITION The HSO ioutine iuns ev-
eiy 260 micioseconds. The HSO.0 inteiiupt is used in-
stead of an actuaI softwaie timei because of the abiIity
to easiIy unmask it whiIe othei softwaie timei ioutines
aie iunning.
In the code in Listing 4-7, the mode is fiist deteimined.
Foi the fiist pass ignoie the code staiting with the IabeI
in

mode

1. Staiting with in

mode

2 the countei is
inciemented oi deciemented based on bit zeio of DI-
RFCT. If DIRFCT.0
e
0 the motoi is going back-
waid, if it is a 1 the motoi is going foiwaid. Next the
count diffeience is checked to see if it is sIow enough to
go into mode 1. If not the ioutine ietuins to the code it
was iunning when the inteiiupt occuiied.
27006150
Listing 4-7 Motor Control HSO0 Timer Routine
42
AP-248
27006151
Listing 4-7 Motor Control HSO0 Timer Routine (Continued)
If the puIse iate is sIow enough to go to mode 1, the
tiansition is made by enabIing HSI.0 and HSI.1. Both
of these Iines aie connected to the same encodei Iine,
with HSI.0 Iooking foi iising edges and HSI.1 Iooking
foi faIIing edges. The HSI

TIME iegistei is iead to

speed up cIeaiing the HSI FIFO and the LAST1

TIME vaIue is set up so the mode 1 ioutine does not

immediateIy put the piogiam into anothei mode. The
HSI FIFO is then cIeaied, the Timei 2 vaIue used
thioughout this ioutine is saved, and the ioutine ie-
tuins.
This ioutine stiII iuns in modes 0 and 1, but in an
abbieviated foim. The section of code staiting with the
IabeI in

mode1 checks to see if the puIses aie coming

in so sIowIy that both HSI Iines can be checked. If this
is the case then aII of the HSIs aie enabIed and the
piogiam ietuins. This ioutine is the secondaiy method
foi going fiom mode 1 to mode 0, the piimaiy method
is by checking the time between edges duiing the HSI
ioutine, which wiII be desciibed Iatei.
The HSO ioutine wiII enabIe mode 0 fiom mode 1 if
two edges aie not ieceived eveiy 260 micioseconds. The
piimaiy method, (undei the HSI ioutine), can onIy
enabIe mode 0 aftei an edge is ieceived. This couId
cause a piobIem if the Iast 2 edges on Phase A befoie
the encodei stops weie too cIose to enabIe mode 0. If
this happened, mode 0 wouId not be enabIed untiI aftei
the encodei staited again, iesuIting in missed edges on
Phase B. Using the HSO ioutine to switch fiom mode 1
to mode 0 eIiminates this piobIem.
Figuie 4-6 shows a state diagiam of how the mode
switching is done. As can be seen, theie aie two souices
foi most of the mode decisions. This heIps avoid piob-
Iems such as the one mentioned above.
When eithei Mode 1 oi Mode 0 is enabIed the HSI
inteiiupt ioutine peifoims the counting of edges, whiIe
the HSO ioutine onIy ensuies that the coiiect mode is
iunning. The ioutines foi modes 0 and 1 shaie the same
initiaIization and compIetion sections, with the main
body of code being diffeient.
The initiaIization ioutine is simiIai to many HSI iou-
tines. The fIags aie checked to ensuie that the HSI
FIFO data is vaIid, and then the FIFO is iead. Next,
the main body of code (foi eithei mode 0 oi mode 1) is
43
AP-248
27006152
NOTES
Mode 0 HSI Examines edges on Phase A and B
Mode 1 HSI Examines edges on Phase A only
Mode 2 TIMER 2 stores edgecount
Figure 4-6 Mode State Diagram
27006153
Listing 4-8 Motor Control HSI Data Available Routine
44
AP-248
iun. At the end time and count vaIues aie saved and the
hoIding iegistei is checked foi anothei event. Listing 4-
8 contains the initiaIization and compIetion sections of
the HSI ioutine.
Listing 4-9 is the main body of the Mode 1 ioutine.
Befoie any caIcuIations aie done in Mode 1, the incom-
ing puIse peiiod is measuied to see if it is too fast oi too
sIow foi mode 1. The time peiiod between two edges is
used so that the duty cycIe of the wavefoim wiII not
affect mode switching. If it is deteimined that Mode 2
shouId be set, Poit 1.1 is set, aII of the HSI Iines aie
disabIed, and the HSI fifo is cIeaied. If Mode 0 is to be
set aII of the HSI Iines aie enabIed and the vaiiabIe
LAST

STAT is cIeaied. LAST

-
STAT
e
0 is used as
a fIag to indicate the fiist HSI inteiiupt in Mode 0 aftei
Mode 1. Aftei the mode checking and setting aie com-
pIete the inciementaI vaIue in Timei 2 is used to update
POSITION. The piogiam then ietuins to the compIe-
tion section of the ioutine.
Theie is a Iot moie code used in Mode 0 than in Mode
1, most of which is due to the muItipIe jump statements
that deteimine the cuiient and pievious state of the
HSI pins. In oidei to save execution time seveiaI bIocks
of code aie iepeated as can be seen in Listing 4-10. The
fiist deteimination is that of which edge had occuiied.
If a Phase A edge was detected the LAST1

TIME and
LAST2

TIME vaiiabIes aie updated so a iefeience to

the puIse fiequency wiII be avaiIabIe. These aie the
same vaiiabIes used undei Mode 1. A test is aIso made
to see if the edges aie coming fast enough to waiiant
being in Mode 1, if they aie, the switch is made. If the
Iast edge detected was on Phase B, the infoimation is
used onIy to deteimine diiection.
27006154
Listing 4-9 Motor Control Mode 1 Routines
45
AP-248
27006155
Listing 4-10 Motor Control Mode 0 Routines
46
AP-248
Aftei mode coiiectness is confiimed and the LASTx

TIME vaIues aie updated the LAST

STAT (Last
Status) vaiiabIe is used to deteimine the cuiient diiec-
tion of tiaveI. The POSITION vaIue is then updated in
the diiection specified by the Iast two edges and the
status is stoied. Note that the fiist time in Mode 0 aftei
being in Mode 1, the Mode 1 done

chk ioutine is used

to update POSITION, instead of the ioutines going

fwd and going

rev fiom the Mode 0 section of code.

The compIetion section of code is then executed.
Pioviding the PWM vaIue to diive the motoi is done by
a ioutine iunning undei Softwaie Timei 1. The fiist
section of code, shown in Listing 4-11a, has to do with
caIcuIating the position and timei eiiois. Listing 4-11b
shows the next section of code wheie the powei to be
suppIied to the motoi is caIcuIated. Fiist the diiection
is checked and if the diiection is ieveise the absoIute
vaIue of the eiioi is taken. If the eiioi is gieatei than
64K counts, the PWM ioutine is Ioaded with the maxi-
mum vaIue. The next check is made to see if the motoi
is cIose enough to the desiied Iocation that the powei to
it shouId be ieveised, (i.e., entei the Biaking mode). If
the motoi is veiy cIose to the position oi has sIowed to
the point that is IikeIy to tuin aiound, the Hold

Posi-
tion mode is entered
The deteimination of which modes aie seIected undei
what conditions was done empiiicaIIy. AII of the pa-
iameteis used to deteimine the mode aie kept in RAM
so they can be easiIy changed on the fIy instead of by
ie-assembIing the piogiam. The paiameteis in the Iist-
ing have been seIected to make the motoi iun, but have
not been optimized foi speed oi stabiIity. A diagiam of
the modes is shown in Figuie 4-7.
In the Hold

Position mode powei is eased onto the

motoi to Iock it into position. Since the motoi couId be
stopped in this mode, some integiaI contioI is needed,
as piopoitionaI contioI aIone does not woik weII when
the eiioi is smaII and the Ioad is Iaige. The BOOST
vaiiabIe piovides this integiaI contioI by incieasing the
output a fixed amount eveiy time peiiod in which the
Listing 4-11 Motor Control Software Timer 1 Routine
27006156
Listing 4-11a Motor Control Software Position Counter
47
AP-248
27006157
Listing 4-11b Motor Control Power Algorithm
48
AP-248
27006158
Figure 4-7 Motor Control Modes
eiioi does not get smaIIei. Once the eiioi does get
smaIIei, usuaIIy because the motoi staits moving,
BOOST is cIeaied.
A sanity check can be peifoimed at this point to doubIe
check that the 8096 has piopei contioI of the motoi. In
the exampIe the woist that can happen is the pioto-
27006159
Listing 4-12 Motor Control Next Position Lookup
49
AP-248
type wiII need to be ieset, so the sanity check was not
used. If one weie desiied, it couId be as simpIe as
checking a haidwaie geneiated diiection indicatoi, oi
as compIex as checking motoi condition and othei en-
viionmentaI factois.
Aftei aII checks have been made, the powei vaIue is
Ioaded to the RPWR iegistei using a softwaie inveision
to compensate foi the haidwaie inveision. Diiection is
deteimined next and the powei and diiection aie
changed in adjacent instiuctions with inteiiupts dis-
abIed to pievent changing powei without diiection and
vice veisa.
To exeicise the piogiam Iogic the desiied position is
changed based on the time vaIue using the code and
Iookup tabIe shown in Listing 4-12.
The iemaining sections of the piogiam aie ieIativeIy
simpIe, but woith discussing biiefIy. The initiaIization
ioutine initiaIizes the I/O featuies and pIaces seveiaI
vaiiabIes fiom ROM into RAM. Having these vaiiabIes
in RAM makes it easiei to tweak the aIgoiithm. Timei
1 is expanded into a 32-bit timei by the inteiiupt iou-
tine shown in Listing 4-13.
Softwaie timei oveihead is handIed by the ioutine
shown in Listing 4-14. In this ioutine the status of each
timei bit is checked in a shadow iegistei. If any of the
timeis have expiied the appiopiiate ioutine is caIIed.
27006160
Listing 4-13 Motor Control Timer Interrupt Routine
270061B2
Listing 4-14 Motor Control Software Timer Interrupt Handler
50
AP-248
27006161
Listing 4-15 Motor Control Software Timer 2 Routine
The Iast ioutine, shown in Listing 4-15, is the Softwaie
Timei 2 ioutine which outputs some vaiiabIes to extei-
naI RAM. It aIso keeps LAST1
-
Time within 1800H
of Timei1 to pievent oveifIows fiom occuiiing when
the Mode 0 and Mode 1 softwaie check this vaiiabIe.
A compIete Iisting of the piogiam as it is used in oui
Iab can be found in Appendix D. Foi a given motoi oi
encodei it wiII piobabIy be necessaiy to change some of
the time constants on the fiist page of the Iisting. With
the motoi used in oui expeiimentation, puIses aie
missed fiom time to time when diiection changes
quickIy. If the motoi weie not as fast to tuin aiound oi
the encodei weie mounted bettei these piobIems shouId
disappeai. The missing puIses occui when switching
fiom Mode 1 to Mode 0, othei than that no anomaIies
weie found in the Iab.
Piioi to the veision of code just discussed, seveiaI at-
tempts weie made, one of which couId be used undei
ceitain constiaints. It is possibIe to use onIy modes 2
and 0 to monitoi the encodei, piovided the encodei
aIways opeiates smoothIy and piovides at Ieast 200 mi-
cioseconds between the Iast seveiaI edges of Phase A
befoie ieveising. This idea was oiiginaIIy tiied because
the motoi was not chaiacteiized thoioughIy at fiist,
and caused piobIems because of the motois tendency to
stop suddenIy when its speed was Iow.
If an encodei has a Iowei Iine count and theiefoie moie
time between output puIses the two mode soIution can
be used. The softwaie foi the two mode veision can be
easiIy extiacted foim the thiee mode veision, so it wiII
not be piesented.
50 HARDWARE EXAMPLE
51 EPROM Only Minimum System
The diagiam in Figuie 5-1 iIIustiates how to connect an
8096 in a minimum configuiation system. Fithei 2764s
oi 27128s can be used in the system. Note that the
Iowei FPROM contains the even bytes whiIe the uppei
51
AP-248
27006162
Figure 5-1 (1 of 2)
one contains the odd bytes, and the addiessing is not
fuIIy decoded. This means that the addiessing on a
2764 wiII be such that the Iowei 4K of each FPROM is
mapped at 0000H and 4000H whiIe the uppei
4K is mapped at 2000H. If the piogiam being Ioaded is
16 Kbytes Iong the fiist haIf is Ioaded into the second
haIf of the 2764s and vice veisa. A simiIai situation
exists when using 27128s.
52
AP-248
27006163
Figure 5-1 (2 of 2)
This ciicuit wiII aIIow most of the softwaie piesented in
this ap-note to be iun. In a system designed foi pioto-
typing in the Iab it may be desiiabIe to buffei the I/O
poits to ieduce the iisk of buining out the chip duiing
expeiimentation. One may aIso want to enhance the
system by pioviding RC fiIteis on the A to D inputs, a
piecision VRFF powei suppIy, and additionaI RAM.
52 Port Reconstruction
If it is desiied to fuIIy emuIate a 8396 then I/O poits 3
and 4 must be ieconstiucted. It is easiest to do this if
the usage of the Iines can be iestiicted to inputs oi
outputs on a poit by poit iathei than Iine by Iine basis.
The poits aie ieconstiucted by using standaid memoiy-
mapped I/O techniques, (i.e., addiess decodeis and
Iatches), at the appiopiiate addiesses. If no exteinaI
RAM is being used in the system then the addiess de-
coding can be paitiaI, iesuIting in Iess compIex Iogic.
The ieconstiucted I/O poits wiII woik with the same
code as the on chip poits. The onIy diffeience wiII be
the piopagation deIay in the exteinaI ciicuitiy.
53
AP-248
60 CONCLUSION
An oveiview of the MCS-96 famiIy has been piesented
aIong with seveiaI simpIe exampIes and a few moie
compIex ones. The souice code foi aII of these pio-
giams aie avaiIabIe in the Insite Useis Libiaiy using
oidei code AF-16. AdditionaI infoimation on the 8096
can be found in the MiciocontioIIei Handbook and it is
iecommended that this book be in youi possession be-
foie attempting any woik with the MCS-96 famiIy of
pioducts. Youi IocaI InteI saIes office can assist you in
getting moie infoimation on the 8096 and its haidwaie
and softwaie deveIopment tooIs.
70 BIBLOGRAPHY
1. MSC-96 Macio AssembIei Useis Ouide, InteI Coi-
poiation, 1983.
Oidei numbei 122048-001.
2. MiciocontioIIei Handbook (1985), InteI Coipoia-
tion, 1984.
Oidei numbei 210918-002.
3. MSC-96 UtiIities Useis Ouide, InteI Coipoiation,
1983.
Oidei numbei 122049-001.
4. PL/M-96 Useis Ouide, InteI Coipoiation, 1983.
Oidei numbei 122134-001.
54
AP-248
APPENDIX A
BASIC SOFTWARE EXAMPLES
A1 Table Lookup 1
2
7
0
0
6
1

6
4
A-1
AP-248
A1 Table Lookup 1 (Continued)
2
7
0
0
6
1

6
5
A-2
AP-248
A2 Table Lookup 2
2
7
0
0
6
1

6
6
A-3
AP-248
A2 Table Lookup 2 (Continued)
2
7
0
0
6
1

6
7
A-4
AP-248
A3 PLM-96 Code with Expansion (Continued)
2
7
0
0
6
1

6
9
2
7
0
0
6
1

7
0
A-6
AP-248
A3 PLM-96 Code with Expansion (Continued)
2
7
0
0
6
1

7
1
A-7
AP-248
A3 PLM-96 Code with Expansion (Continued)
2
7
0
0
6
1

7
2
A-8
AP-248
A3 PLM-96 Code with Expansion (Continued)
2
7
0
0
6
1

7
3
A-9
AP-248
A3 PLM-96 Code with Expansion (Continued)
2
7
0
0
6
1

7
4
A-10
AP-248
A4 Pulse Measurement
2
7
0
0
6
1

7
5
A-11
AP-248
A4 Pulse Measurement (Continued)
2
7
0
0
6
1

7
6
A-12
AP-248
A5 Enhanced Pulse Measurement
2
7
0
0
6
1

7
7
A-13
AP-248
A5 Enhanced Pulse Measurement (Continued)
2
7
0
0
6
1

7
8
A-14
AP-248
A6 PWM Using the HSO
2
7
0
0
6
1

7
9
A-15
AP-248
A6 PWM Using the HSO (Continued)
2
7
0
0
6
1

8
0
A-16
AP-248
A6 PWM Using the HSO (Continued)
2
7
0
0
6
1

8
1
A-17
AP-248
A6 PWM Using the HSO (Continued)
2
7
0
0
6
1

8
2
A-18
AP-248
A7 Serial Port
2
7
0
0
6
1

8
3
A-19
AP-248
A7 Serial Port (Continued)
2
7
0
0
6
1

8
4
A-20
AP-248
A8 A to D Converter
2
7
0
0
6
1

8
5
A-21
AP-248
A8 A to D Converter (Continued)
2
7
0
0
6
1

8
6
A-22
AP-248
APPENDIX B
HSO AND A TO D UNDER INTERRUPT CONTROL
2
7
0
0
6
1

8
7
B-1
AP-248
2
7
0
0
6
1

8
8
B-2
AP-248
2
7
0
0
6
1

8
9
B-3
AP-248
2
7
0
0
6
1

9
0
B-4
AP-248
APPENDIX C
SOFTWARE SERIAL PORT
2
7
0
0
6
1

9
1
C-1
AP-248
2
7
0
0
6
1

9
2
C-2
AP-248
2
7
0
0
6
1

9
3
C-3
AP-248
2
7
0
0
6
1

9
4
C-4
AP-248
2
7
0
0
6
1

9
5
C-5
AP-248
2
7
0
0
6
1

9
6
C-6
AP-248
APPENDIX D
MOTOR CONTROL PROGRAM
2
7
0
0
6
1

9
7
D-1
AP-248
2
7
0
0
6
1

9
8
D-2
AP-248
2
7
0
0
6
1

9
9
D-3
AP-248
2
7
0
0
6
1

A
0
D-4
AP-248
2
7
0
0
6
1

A
1
D-5
AP-248
2
7
0
0
6
1

A
2
D-6
AP-248
2
7
0
0
6
1

A
3
D-7
AP-248
2
7
0
0
6
1

A
4
D-8
AP-248
2
7
0
0
6
1

A
5
D-9
AP-248
2
7
0
0
6
1

A
6
D-10
AP-248
2
7
0
0
6
1

A
7
D-11
AP-248
2
7
0
0
6
1

A
8
D-12
AP-248
2
7
0
0
6
1

A
9
D-13
AP-248
2
7
0
0
6
1

B
0
D-14
AP-248
2
7
0
0
6
1

B
1
D-15
INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080
INTEL CORPORATION (UK) Ltd Swindon United Kingdom Tel (0793) 696 000
INTEL JAPAN kk Ibaraki-ken Tel 029747-8511
Printed in USAxxxx0296B10MRP SM
Microcontroller Operation