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Birla Institute of Technology and Science II Semester 2012-13 MEL G641 CAD For IC Design Lab Assignement-1

This document describes an assignment to perform VHDL coding of a circuit using a structural style of modeling. The circuit contains multiple full adders in a tree structure, with inputs A0-A3 and B0-B3. The outputs are labeled P0-P7. The student is asked to identify the circuit operation and write VHDL code to model it structurally. Additional questions ask the student to model a D flip-flop with timing specifications, and comment on violations that may occur when connecting flip-flops in a loop structure.

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Nirneya Gupta
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67 views2 pages

Birla Institute of Technology and Science II Semester 2012-13 MEL G641 CAD For IC Design Lab Assignement-1

This document describes an assignment to perform VHDL coding of a circuit using a structural style of modeling. The circuit contains multiple full adders in a tree structure, with inputs A0-A3 and B0-B3. The outputs are labeled P0-P7. The student is asked to identify the circuit operation and write VHDL code to model it structurally. Additional questions ask the student to model a D flip-flop with timing specifications, and comment on violations that may occur when connecting flip-flops in a loop structure.

Uploaded by

Nirneya Gupta
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Birla Institute of Technology and Science II semester 2012-13 MEL G641 CAD for IC Design Lab Assignement-1 ______________________________________________________________________________

For the following circuit perform the VHDL coding using structural style of modeling. Identify the circuit operation.
B0 A3 AB A2 AB A1 A.B A0 A.B B1 P0 A3 AB 0 A2 A.B A1 A.B 0 A0 A.B 0

FA
A3 AB A2 A.B A1

FA

FA
P1 A0

B2

A.B

A.B

FA
A3 A2 A3 B3 AB AB A1 AB

FA

FA
P2 A0 AB B3

FA

FA

FA

FA

B3

A3

FA
Cout P7

FA
P6

FA
P5

FA
P4

FA
P3

Q2: (Choice: VHDL/Verilog) (A) Write a module for positive edge triggered D flip-flop with setup and hold time limit violation specification. Module must report, if any violations are present. Chose setup time limit= 3 ns and Hold time limit of 7 ns, clock to q delay is 2 ns. Write test benches that verify all such violation. (B) If Q2 is connected back to D1 through an inverter having delay of 1ns and Q1 connected to D2 through an buffer having delay 1ns, also Hold time limit of Flip-Flop changed to 7 ns (keeping setup & clock to q delay unchanged) then comment on any time violations. In case any violations suggest suitable modifications in combinational circuit delays to remove timing violations and maximum clock frequency. Write the corresponding test benches.
1 ns

Q1 D1 D F/F

D2 D

Clk

1 ns

Clk

F/F

Q2

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