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Sequence Detector: Experiment No: 10 Activity: To Design and Simulate ' Sequence Detector of 101'' Using VHDL

The document describes a VHDL code for designing and simulating a sequence detector for the sequence "101" using a finite state machine. The code defines an entity with inputs for a reset, clock, sequence and an output. The architecture contains a process that defines the state transitions - it starts in state A, and transitions to states B and C depending on the input sequence, outputting a '1' only when the full sequence "101" is detected before returning to state A.

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Saurabh Khandelwal
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74 views2 pages

Sequence Detector: Experiment No: 10 Activity: To Design and Simulate ' Sequence Detector of 101'' Using VHDL

The document describes a VHDL code for designing and simulating a sequence detector for the sequence "101" using a finite state machine. The code defines an entity with inputs for a reset, clock, sequence and an output. The architecture contains a process that defines the state transitions - it starts in state A, and transitions to states B and C depending on the input sequence, outputting a '1' only when the full sequence "101" is detected before returning to state A.

Uploaded by

Saurabh Khandelwal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SEQUENCE DETECTOR 1901

EXPERIMENT NO: 10 Activity: To design and simulate Sequence Detector of 101 using VHDL. CODING:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity seq_dect is Port ( reset,clk,seq : in std_logic; z : out std_logic); end seq_dect; architecture Behavioral of seq_dect is type state_type is (A,B,C); signal state : state_type := A; begin process(clk,reset) begin if( reset = '1' ) then z <= '0'; state <= A; elsif ( rising_edge(clk) ) then case state is when A => z<= '0'; if ( seq = '0' ) then state <= A; else state <= B; end if; when B => if ( seq = '0' ) then state <= C; else state <= B; end if; when C => if ( seq = '0') then state <= A; else state<=A; z <= '1'; end if; when others => NULL; end case; end if; end process; end Behavioral;

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NAME: SANDEEP KUMAR

SEQUENCE DETECTOR 1901

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NAME: SANDEEP KUMAR

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