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Changes Need To Do: "Count: Buffer Integer 0 To 15 And: "If Clear 1 or Count 5) Then

The document describes a counter module that counts from 0 to 15 on each clock cycle, resetting the count to 0 if a clear signal is asserted or the count reaches 5. It also describes a second counter module that counts from 0 to 4 on each clock cycle, resetting the count to 0 if the clear signal is asserted or the count reaches 4.

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Atit Patel
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42 views

Changes Need To Do: "Count: Buffer Integer 0 To 15 And: "If Clear 1 or Count 5) Then

The document describes a counter module that counts from 0 to 15 on each clock cycle, resetting the count to 0 if a clear signal is asserted or the count reaches 5. It also describes a second counter module that counts from 0 to 4 on each clock cycle, resetting the count to 0 if the clear signal is asserted or the count reaches 4.

Uploaded by

Atit Patel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Changes need to do: count : buffer integer 0 to 15; And: if clear = 1 or count >= 5) then

Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity mod5_counter is Port (rst, clk: in bit; count: buffer integer range 0 to 15); End mod5_counter;

Architecture test of mod5_counter is

Begin Process Begin

Wait until clk' event and clk = '1';

If (clr= '1' or count >= 5) then Count <=0;

Else Count <= count + 1; End if;

End process;

End test;

Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity mod5 is Port (clr, clk: in bit; count: buffer integer range 0 to 4); End mod5;

Architecture test of mod5 is

Begin Process Begin

Wait until clk' event and clk = '1';

If (clr= '1' or count >= 4) then Count <=0;

Else Count <= count + 1;

End if;

End process;

End test;

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