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How To Create Simulation Environment On Linux

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16 views

How To Create Simulation Environment On Linux

Uploaded by

UNETI
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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How to create simulation environment INTC on Linux

Semicon IC Design Training Center http://www.semiconvn.com

Simulation Environment
top.v

intc.v cpu.v MOVT() MOVF() 9 interrupt excption handling program

sub_intc.v

Working Directory Tree


intc_env
rtl
INTC RTL

testbench
top.v (etc)

testcases
Tests

sim
Makefile compile_rtl.f and compile_tb.f

vip
cpu.v

compile_rtl.f and compile_tb.v


This file consists of the path of RTL & testbench Content of compile_rtl.f
../rtl/intc.v .

Content of compile_tb.f
../testbench/top.v

cpu.v
module cpu_module (); .. task MOVT; .. endtask .. task MOVF; .. endtask .. task IRQ0_exception_handling(); // repeat 9 times for this tasks --$display(I am in IRQ0 exception handling); MOVT(.); // clear status bit on register of INTC for completing the exception handling. endtask endmodule

top.v
module top (); .. intc intc(.); // instance INTC to TOP test `include run_test.vt // include file testcase to here cpu cpu (.); // instance CPU to TOP test . Initial begin reset(); #500; run_test(); #50000; report_test(); end task reset; // this task is used to reset system . endtask // creat clock for system in this block .. task report_test; // this task is used to reset system . endtask endmodule

R e f f f f f f

E b b b b b b b

G c u u u u u u

R _ _ _ _ _ _ _

E r r t t t t t

S e e e e e e e

S g g s s s s s

I _ _ t t t t t

O r c _ _ _ _ _

N w o a n n n n

_ n l i i i i

L \ f l f f f f

I i 1 2 3 4

S g \

= \

\ \ \

task report_test;
task report_test; input exit; begin $display ("******************************************** \n"); $display ("* Value of test_status variable: %h", test_status); $display ("******************************************** \n\n"); if (test_status === 32'hABABABAB) report_miss_test (exit); else if (test_status === 32'hCAFECAFE) report_pass_test (exit); else if (test_status === 32'hDEADDEAD) report_fail_test (exit); else report_unknow_test(exit); end endtask // report_test

task report_pass_test; input exit; begin $display ("******************************************** "); $display ("* * "); $display ("* PPP AAA SSSS SSSS EEEE DDDD * "); $display ("* P P A A S S E D D * "); $display ("* PPP AAAAA SSSSSS EEE D D * "); $display ("* P A A S S E D D * "); $display ("* P A A SSSS SSSS EEEE DDDD * "); $display ("* * "); $display ("******************************************** "); $display("\n\n=======================================================\n"); $display("== =="); $display("== =="); $display("=======================================================\n\n"); if (exit) $finish; end endtask

sample_test.vt (example)
task run_test; .. begin MOVT(); MOVF(); .. end endtask

makefile
Next Slide

ifdef TEST_LIST include ${TEST_LIST} endif CMP_CMD = sv_cmp CMP_FILE = compile.f normal: clean $(CMP_CMD) /tools/Modelsim/v6.2b/modeltech/linuxle/vsim -l ${TEST_NAME}.log -c test_top -voptargs=+acc -novopt -assertdebug -do "log -r /*; run -all" echo 'Test Name: $(TEST_NAME)' >> $(TEST_NAME).log gui: clean $(CMP_CMD) /tools/Modelsim/v6.2b/modeltech/linuxle/vsim ${DENALI_OPTION} -novopt -assertdebug -voptargs=+acc TB_tp -do wave.do sv_cmp: sv_lib /tools/Modelsim/v6.2b/modeltech/linuxle/vlog +incdir+../rtl +incdir+../testbench -f $(CMP_FILE) sv_lib: test -e work || /tools/Modelsim/v6.2b/modeltech/linuxle/vlib work clean: rm -f run_test.vt cp -f ../testcases/$(TEST_NAME).vt run_test.vt rm -rf *.tmp transcript work *.wlf vsim.fcdb regress: sed '/^#/d' $(TEST_LIST) > ./tmp.lst make regress_core TEST_LIST=tmp.lst regress_core: for i in ${REGRESSION_LIST}; do \ echo $$i ; \ make "TEST_NAME=$$i"; \ done make report TEST_LIST=tmp.lst rm -f ./tmp.lst report: rm -f regress_report.list for i in ${REGRESSION_LIST}; do \ echo -n $$i " : " >> regress_report.list; \ sed -n -e '/TEST PASSED/p' $$i.log >> regress_report.list ;\ sed -n -e '/TEST FAILED/p' $$i.log >> regress_report.list ;\ done cat regress_report.list

Format of test.list
REGRESSION_LIST= \ ebc_reg_rw \ fbu_reg_config \ fbu_test_all \ fbu_test_nif1 \ fbu_test_nif2 \ fbu_test_nif3 \ fbu_test_nif4

How to run simulation environment?


Go to directory simulation
cd sim Simulation
Single test
make TEST_NAME=sample_test

Multiple tests
make regress TEST_LIST=test_list

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