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Verilog Code

This module defines a 3-bit up/down counter with start and end values. It uses a finite state machine with states for initialization, up counting, down counting, and loading start or end values. The counter value is updated on each clock cycle based on the current state and control signals to count up or down, load new values, or remain at the current value.

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Sunil Tolanur
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192 views3 pages

Verilog Code

This module defines a 3-bit up/down counter with start and end values. It uses a finite state machine with states for initialization, up counting, down counting, and loading start or end values. The counter value is updated on each clock cycle based on the current state and control signals to count up or down, load new values, or remain at the current value.

Uploaded by

Sunil Tolanur
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module counter (input load_start, load_end, clock, updn,reset, input [2:0] start_val, end_val, output reg [2:0] count);

localparam [2:0] INITIAL=3'b000, upcounter=3'b001, downcounter=3'b010, start_val ue=3'b011, end_value=3'b100; reg [1:0] current_state, next_state; always @(posedge clock) if (reset==1) current_state<=INITIAL; else current_state<=next_state;

always @(current_state,load_start,load_end,updn,start_value,end_value) case(current_state) INITIAL:begin if(load_start==1) next_state<=start_value; else if(load_end==1) next_state<=end_value; else if(updn==1) next_state<=upcounter; else if(updn==0) next_state<=downcounter; else next_state<=current_state; end upcounter:begin if(load_start==1) next_state<=start_value; else if(load_end==1) next_state<=end_value; else if(updn==0) next_state<=downcounter; else next_state<=current_state; end downcounter:begin if(load_start==1) next_state<=start_value; else if(load_end==1) next_state<=end_value; else if(updn==1) next_state<=upcounter; else next_state<=current_state; end start_value:begin if(updn==1) next_state<=upcounter;

else if (updn==0) next_state<=downcounter; else if(load_end==1) next_state<=end_value; else next_state<=current_state; end end_value:begin if(updn==1) next_state=upcounter; else if(updn==0) next_state=downcounter; else if(load_start==1) next_state=start_value; else next_state=current_state; end endcase always @(posedge clock) if(next_state==INITIAL) count=0; else if((updn==1)&(count!==end_val)&(load_start==0)&(load_end==0)) count=count+1; else if((updn==0)&(count!==start_val)&(load_start==0)&(load_end==0)) count=count-1; else if((updn==1)&(count==end_val)&(load_start==0)&(load_end==0)) begin count=start_val; count=count+1; end else if((updn==0)&(count==start_val)&(load_start==0)&(load_end==0)) begin count=end_val; count=count-1; end else if((load_start==1)&(updn==1)&(load_end==0)) begin count=start_val; count=count+1; end else if((load_start==1)&(updn==1)&(load_end==1)) begin count=start_val; count=count+1; end else if((load_start==1)&(updn==0)&(load_end==0)) begin count=start_val; count=count-1; end else if((load_start==1)&(updn==0)&(load_end==1)) begin count<=start_val;

count<=count-1; end

else if((load_end==1)&(updn==1)&(load_start==0)) begin count=end_value; count=count+1; end else if((load_end==1)&(updn==1)&(load_start==1)) begin count=end_value; count=count+1; end else if((load_end==1)&(updn==0)&(load_start==0)) begin count=end_value; count=count-1; end else if((load_end==1)&(updn==0)&(load_start==1)) begin count=end_value; count=count-1; end

endmodule

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