Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400
Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400
Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400
Product Overview 1
Configuration and Elements of
Function Block Diagram 2
SIMATIC S7 Addressing 3
Jump Instructions 14
10/98 Appendix
C79000-G7076-C566
Glossary, Index
Release 01
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Purpose of the This manual is your guide to creating user programs in the Function Block
Manual Diagram (FBD) programming language.
This manual also includes a reference section that describes the syntax and
functions of the language elements of Function Block Diagram.
Where is this This manual is valid for release 5.0 of the STEP 7 programming software
Manual Valid? package.
Which Standards FBD corresponds to the “Function Block Diagram” language defined in the
Does the Software International Electrotechnical Commission’s standard IEC 1131-3. For
Comply With? further details, refer to the table of standards in the STEP 7 file
NORM_TBL.WRI.
Requirements To use this Function Block Diagram manual effectively, you should already
be familiar with the theory behind S7 programs which is documented in the
online help for STEP 7. The language packages also use the STEP 7 standard
software, so you should be familiar with handling this software and have read
the accompanying documentation.
Accessing the You can display the online help in the following ways:
Online Help
Context-sensitive help about the selected object with the menu command
Help > Context-Sensitive Help, with the F1 function key, or by clicking
the question mark symbol in the toolbar.
Help on STEP 7 via the menu command Help > Contents.
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Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 Configuration and Elements of Function Block Diagram . . . . . . . . . . . . . . . . . . . 2-1
2.1 Elements and Box Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Boolean Logic and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 Significance of the CPU Registers in Statements . . . . . . . . . . . . . . . . . . . . 2-9
3 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Types of Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
4 Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 AND Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 AND-before-OR Logic Operation and OR-before-AND Logic Operation . 4-5
4.5 Exclusive OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.6 Insert Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.7 Negate Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.8 Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.9 Midline Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.10 Save RLO to BR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.11 Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.12 Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.13 Set Counter Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.14 Up Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.15 Down Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.16 Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.17 Extended Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
The FBD The Function Block Diagram programming language has all the elements
Programming necessary for creating a complete user program. It contains a wide range of
Language instructions. These include the various basic instructions and a wide range of
addresses and address types. Functions and function blocks allow you to
structure your FBD program clearly.
The Programming The FBD programming package is an integral part of the STEP 7 Standard
Package Software. This means that following the installation of your STEP 7 software,
all the editor functions, compiler functions, and test/debug functions for FBD
are available to you.
Using FBD, you can create your own user program. With the Incremental
Editor, the input of the local data structure is made easier with the help of
table editors.
There are three programming languages in the standard software, STL, FBD,
and LAD. You can switch from one language to the other almost without
restriction and choose the most suitable language for the particular block you
are programming.
If you write programs in LAD or FBD, you can always switch over to the
STL representation. If you convert LAD programs into FBD programs and
vice versa, program elements that cannot be represented in the destination
language are displayed in STL.
FBD Instructions FBD instructions consist of elements and boxes that are connected
graphically to form networks. The elements and boxes can be classified in
the following groups:
Instructions as STEP 7 represents some of the FBD instructions as individual elements that
Elements do not require addresses or parameters (see Table 2-1).
Instruction as a STEP 7 represents some of the FBD instructions as boxes for which you must
Box with Address specify an address (see Table 2-2). For more detailed information about
addressing, refer to Chapter 3.
<Address>
Assign 4.8
=
Instruction as a STEP 7 represents some of the FBD instructions as boxes for which you
Box with Address specify an address and a value (for example a timer or counter value, see
and Value Table 2-3).
For more detailed information about addressing, refer to Chapter 3.
Instruction as Box STEP 7 represents some of the FBD instructions as boxes with inputs and
with Parameters outputs (see Table 2-4). The inputs are on the left of the box and the outputs
on the right. You specify the input parameters and some of the output
parameters. Most outputs are provided by the STEP 7 software. To assign
parameters, you must use the specific notation of the data types.
The parameters of the Enable input (EN) and the Enable output (ENO) are
described below. For further information about input and output parameters,
refer to the descriptions of the individual instructions in this manual.
DIV_R
EN
Divide real 8.5
IN1 OUT
IN2 ENO
Enable Input and If the Enable input (EN) of an FBD box is activated, the box carries out a
Enable Output specific function. If the function is executed by the box without errors, the
Parameters Enable output (ENO) is activated. The parameters EN and ENO of an FBD
box are of the BOOL data type and can be located in the I, Q, M, D, or L
memory areas (see Table 2-5 and 2-6).
How EN and ENO function is described below:
If EN is not activated (its signal state is 0), the box does not execute its
function and ENO is not activated (its signal state is also 0).
If EN is activated (its signal state is 1) and if the box executes its function
without errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and if an error occurs during the
execution of the function, ENO is not activated (its signal state remains
0).
Memory Areas and The majority of the addresses in FBD refer to memory areas. The following
Functions table shows the types and their functions.
Access to Area
Name of Area Function of Area Using Units of the Abbr.
Following Size:
Process input At the beginning of the scan cycle, the operating system reads Input bit I
image the inputs from the process and records the values in this area. Input byte IB
The program uses these values when it is running cyclically. Input word IW
Input double word ID
Process output During the scan cycle, the program calculates output values and Output bit Q
image enters them in this area. At the end of the scan cycle, the Output byte QB
operating system reads the calculated output values from this Output word QW
area and sends them to the process outputs. Output double word QD
Bit memory This area provides memory space for interim results calculated Memory bit M
in the program. Memory byte MB
Memory word MW
Memory double word MD
I/Os Using this area, your program has direct access to input and Peripheral input byte PIB
output modules (peripheral inputs and outputs). Peripheral input word PIW
Ext. inputs Peripheral input double PID
word
I/Os: Peripheral output byte PQB
Peripheral output word PQW
Ext. outputs Peripheral output double PQD
word
Timers Timers are function elements in FBD. This area provides Timer (T) T
memory space for timer cells. In this area, the clock timing
accesses the timer cells and updates them by decrementing the
timer value. Timer operations access these timer cells.
Counters Counters are function elements in FBD. This area provides Counter (C) C
memory space for counters. Count instructions access the cells
in this area.
Data block This area contains data that can be accessed from within any Data block opened with
block. If it is necessary to open two data blocks at the same the “OPN DB”
time, you can open one with the “OPN DB” instruction and the instruction:
other with the “OPN DI” instruction. The notation of the Data bit DBX
addresses, for example L DBWi and L DIWi identifies the data Data byte DBB
block to be accessed. Data word DBW
Although you can access any data block with the “OPN DI” Data double word DBD
i
instruction,
i this
hi iinstruction
i iis mainly
i l used
d to open iinstance ddata Data block opened with
blocks that are assigned to function blocks (FBs) and system the “OPN DI”
function blocks (SFBs). For more detailed information about instruction:
FBs and SFBs, refer to the STEP 7 Online Help. Data bit DIX
Data byte DIB
Data word DIW
Data double word DID
Local data This area contains temporary local data belonging to a logic Temporary local data bit L
block (FB or FC). This type of data is also called dynamic local Temporary local data LB
data. This area is used as a buffer. When the logic block is byte
closed, the data are lost. These data are located in the local data Temporary local data LW
stack (L stack). word
Temporary local data LD
double word
Table 2-6 lists the maximum address ranges for the various memory areas.
For more detailed information about the address ranges on your CPU, refer to
the corresponding manual /70/ or /101/.
Access Using
Name of Area M i
Maximum Address
Add Range
R
Units of the Following Sizes: Abbr.
Process input image Input bit I 0.0 to 65 535.7
Input byte IB 0 to 65 535
Input word IW 0 to 65 534
Input double word ID 0 to 65 532
Process output Output bit Q 0.0 to 65 535.7
image Output byte QB 0 to 65 535
Output word QW 0 to 65 534
Output double word QD 0 to 65 532
Bit memory Memory bit M 0.0 to 255.7
Memory byte MB 0 to 255
Memory word MW 0 to 254
Memory double word MD 0 to 252
I/Os: Peripheral input byte PIB 0 to 65 535
External inputs Peripheral input word PIW 0 to 65 534
Peripheral input double word PID 0 to 65 532
I/Os: Peripheral output byte PQB 0 to 65 535
External outputs Peripheral output word PQW 0 to 65 534
Peripheral output double word PQD 0 to 65 532
Timers Timer T 0 to 255
Counters Counter C 0 to 255
Data block Data block opened with the DB [OPN]
instruction
1) With FBD instructions, you can only use an address in the L memory area when
you declare it as VAR_TEMP in the variable declaration table.
Boolean Logic The FBD programming language is based on the binary logic of Boolean
algebra in which variables can adopt the values “true” (1) or “false” (0).
Each logic instruction checks the signal state of a variable for 1 (true,
satisfied) or 0 (false, not satisfied) and then produces a result. The instruction
then either saves the result or uses it to perform a Boolean logic operation.
The result of the logic operation is known as the RLO.
To represent the logic, the logic boxes known from Boolean algebra are used.
The results of the logic instructions for all possible combinations of logical
variables are listed in truth tables.
The rules of Boolean logic are illustrated below based on the AND, OR, and
exclusive OR logic operations.
AND Logic In an AND logic operation, the signal states of two or more specified
Operation addresses are checked. If the signal state of the address is 1 the condition is
satisfied and the instruction produces the result 1. If the signal state of the
address is 0, the condition is not satisfied and the operation produces the
result 0.
Figure 2-1 illustrates an AND logic operation in the FBD programming
language.
OR Logic In an OR logic operation, the signal states of two or more specified addresses
Operation are checked. If the signal state of one of the addresses is 1, the condition is
satisfied and the instruction provides the result 1. If the signal state of all
addresses is 0, the condition is not satisfied and the instruction produces the
result 0.
Figure 2-2 shows an OR logic operation in the FBD programming language.
If the result of the sig- and the result of the the result of the logic instruction
nal state check at ad- signal state check at is as follows:
dress I1.0 is as below address I1.1 is as below
1 0 1
0 1 1
1 1 1
0 0 0
Exclusive OR In an exclusive OR logic operation, the signal states of two or more specified
Logic Operation addresses are checked. If the signal state of one of the addresses is 1 the
condition is satisfied and the instruction provides the result 1. If the signal
state of all addresses is 0 or 1, the condition is not satisfied and the
instruction produces the result 0.
Figure 2-3 shows an exclusive OR logic operation in the FBD programming
language.
If the result of the and the result of the the result of the logic instruction
signal state check at signal state check at is as follows:
address I1.0 is as below address I1.1 is as below
1 0 1
0 1 1
1 1 0
0 0 0
Explanation Registers help the CPU perform logic, math, shift, or conversion instructions.
These registers are described below.
Accumulators The accumulators are general-purpose registers that you use to process bytes,
words, and double-words. The accumulators are 32-bits wide.
31 24 23 16 15 8 7 0
Status Word The status word contains bits that you can reference in the address of bit
logic instructions. The following sections explain the significance of bits
0 through 8.
215... ...29 28 27 26 25 24 23 22 21 20
BR CC1 CC0 OV OS OR STA RLO FC
First Check Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5).
At the start of an FBD network, the signal state of the FC bit is always 0,
unless the previous network ended with the SAVE box
Each logic instruction checks the signal state of the FC bit as well as the
signal state of the contact that the instruction addresses. The signal state of
the FC bit determines the sequence of a logic string. If the FC bit is 0 (at the
start of an FBD network), the instruction stores the result in the result of
logic operation bit (RLO) of the status word and sets the FC bit to 1. This is
known as the first check. The 1 or 0 that is set in the RLO bit after the first
check is then referred to as the result of first check.
If the signal state of the FC bit is 1, an instruction then combines the result of
its signal state check at the addressed contact with the RLO formed at the
addressed contact after the first check, and sets the result in the RLO bit.
A logic string made up of FBD instructions always ends with an output
instruction (for example set output, reset output, assign) or with a jump
instruction dependent on the result of the logic operation (RLO). These
instructions reset the FC bit to 0.
Result of Logic Bit 1 of the status word is called the result of logic operation bit (RLO bit,
Operation see Figure 2-5). This bit stores the result of a string of logic instructions or
compare instructions. The signal state of the RLO bit provides information
about signal flow.
The first instruction in an FBD network checks the signal state of an address
and produces a result of 1 or 0. The instruction enters the result of this signal
state in the RLO bit. The second instruction in a string of logic operations
also checks the signal state of an address and produces a result. The
instruction now combines this result with the value of the RLO bit of the
status word according to the rules of Boolean logic (see First Check above).
The result of the logic operation is entered in the RLO bit of the status word
and replaces the previous value in the RLO bit. Each subsequent instruction
in the string of logic operations combines two values: the result of the signal
check at the specified address and the current RLO.
You can, for example, assign the state of a bit memory location to the RLO
during a first check using a Boolean logic operation or trigger a jump
instruction.
Status Bit Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). The
status bit stores the value of a bit that is referenced. The status of a logic
instruction that reads memory is always the same as the value of the bit that
this instruction checks (the bit on which it performs its logic operation). The
status of a bit instruction that writes to memory (Set Output, Reset Output, or
Assign) is the same as the value of the bit to which the instruction writes. If
no writing takes place, the value is the same as the value of the bit that the
instruction references. The status bit has no significance for bit instructions
that do not access memory. These instructions set the status bit to 1 (STA=1).
The status bit is not checked by an instruction. It is interpreted during
program test (program status) only.
OR Bit Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit is
required to execute an AND before OR logic operation. An AND logic
operation can contain the instructions AND input and AND NOT input. The
OR bit indicates to the instructions that a previously executed AND logic
operation produced the value 1 so that the result of the OR logic operation
has already been determined. Any other bit-processing instruction resets the
OR bit.
Overflow Bit Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5).
The OV bit indicates an error. It is set by a math instruction or a compare
floating-point numbers instruction after an error has occurred (overflow,
illegal instruction, illegal floating-point number). The bit is set or reset
according to the result of the math or compare instruction (error).
Stored Overflow Bit 4 of the status word is called the store overflow bit (OS bit, see Figure
Bit 2-5). The OS bit is set together with the OV bit when an error occurs. Since
the OS bit is unchanged when math instructions are executed without errors
(in contrast to the OV bit), this indicates whether or not an error occurred in
one of the previously executed instructions. The following instructions reset
the OS bit: JOS (jump if stored overflow bit = 1, must be programmed in
STL), block calls and block end statements.
CC1 and CC0 Bits 7 and 6 of the status word are called condition code 1 and condition
code 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provide
information about the following results or bits:
Result of a math instruction
Result of a compare instruction
Result of a digital instruction
Bits that have been shifted out of the address by a shift or rotate
instruction.
Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program has
executed certain instructions.
Table 2-10 CC1 and CC0 after Math Instructions, without Overflow
Table 2-11 CC1 and CC0 after Integer Math Instructions, with Overflow
Table 2-12 CC1 and CC0 after Floating-Point Math Instructions, with Overflow
Table 2-14 CC1 and CC0 after Shift and Rotate Instructions
Binary Result Bit Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5).
The BR bit forms a link between the processing of bits and words. This bit is
an efficient method with which you can interpret the result of a word
instruction as a binary result and include this result in a binary string of logic
operations. The BR bit represents an internal memory bit in which the RLO
can be saved prior to a word instruction that changes the RLO so that the old
RLO is available again after the operation when the interrupted series of bit
instructions is resumed.
With the BR bit, you can, for example, program a function block (FB) or a
function (FC) in Statement List (STL) and call the FB or FC in FBD.
If you write a function block or a function that you want to call in FBD,
regardless of whether you write the FB or FC in STL or FBD, you must take
into account the BR bit. The BR bit corresponds to the Enable output (ENO)
of an FBD box. You save the RLO in the BR bit using the SAVE instruction
(in STL) or with the SAVE FBD box according to the following criteria:
Save an RLO of 1 in the BR bit when the FB or FC is processed without
errors.
Save an RLO of 0 in the BR bit if an error occurs during the processing of
an FB or FC.
Program these instructions at the end of the FB or FC so that they are the last
instructions executed in the block.
Warning
! The BR bit can be reset to 0 unintentionally.
When you write FBs or FCs in FBD and do not handle the BR bit as
described above, an FB or FC might overwrite the BR bit of another FB or
FC.
To avoid this problem, save the RLO at the end of each FB or FC as
described above.
Meaning of The Enable input (EN) and Enable output (ENO) parameters of an FBD box
EN/ENO function as explained below:
If EN is not activated (its signal state is 0), the box does not execute its
function and ENO is not activated (it also has a signal state of 0).
If EN is activated (its signal state is 1) and the box executes its function
without errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and an error occurs while the
function is being executed, ENO is not activated (its signal state is 0).
When you call a system function block (SFB) or a system function (SFC) in
your program, the SFB or SFC indicates whether or not the CPU executed the
function without errors by setting the signal state of the BR bit:
If an error occurred during execution, the BR bit is set to 0.
If the function was executed without errors, the BR bit is 1.
3.1 Overview
What is Many FBD instructions operate with one or more addresses. The address
Addressing? specifies a constant or a location at which the instruction finds a variable
which it uses to perform a logic operation. This location can be a bit, byte,
word, or double word.
Examples of possible addresses are as follows:
A constant, the value of a timer or counter, or an ASCII character string
A bit in the status word of the programmable controller
A data block and a location within the data block area
CMP
<= I
50 IN1
MW200 IN2
Table 3-1 Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types
Type and Size in Format Options Range and Number Notation Example
Description Bits (Lowest Value to Highest Value)
BOOL 1 Boolean Text TRUE/FALSE TRUE
(Bit)
BYTE 8 Hexadecimal B#16#0 to B#16#FF B#16#10
(Byte) byte#16#10
WORD 16 Binary 2#0 to 2#0001_0000_0000_0000
(Word) 2#1111_1111_1111_1111
Hexadecimal W#16#0 to W#16#FFFF W#16#1000
word16#1000
BCD C#0 to C#999 C#998
Unsigned decimal B#(0,0) to B#(255,255) B#(10,20)
byte#(10,20)
DWORD 32 Binary 2#0 to 2#1000_0001_0001_1000_
(Double 2#1111_1111_1111_1111_ 1011_1011_0111_1111
word) 1111_1111_1111_1111
Hexadecimal DW#16#0000_0000 to DW#16#00A2_1234
Unsigned decimal DW#16#FFFF_FFFF dword#16#00A2_1234
B#(0,0,0,0) to B#(1,14,100,120)
B#(255,255,255,255) byte#(1,14,100,120)
INT 16 Signed decimal -32768 to 32767 1
(Integer)
DINT 32 Signed decimal L#-2147483648 to L#2147483647 L#1
(Double
integer)
REAL 32 IEEE Upper limit: ±3.402823e+38 1.234567e+13
(Floating floating point Lower limit: ±1.175495e-38 )
point)
S5TIME 16 S5 Time in S5T#0H_0M_0S_10MS to S5T#0H_1M_0S_0MS
(SIMATIC 10-ms units (as S5T#2H_46M_30S_0MS and S5TIME#0H_1M_0S_0MS
time) default value) S5T#0H_0M_0S_0MS
TIME 32 IEC time in 1-ms T#-24D_20H_31M_23S_648MS to T#0D_1H_1M_0S_0MS
(IEC time) units, signed T#24D_20H_31M_23S_647MS TIME#0D_1H_1M_0S_0MS
integer
DATE 16 IEC date D#1990-1-1 to D#1994-3-15
(IEC date) in 1-day units D#2168-12-31 DATE#1994-3-15
TIME_OF_ 32 Time of day in TOD#0:0:0.0 to TOD#1:10:3.3
DAY 1-ms units TOD#23:59:59.999 TIME_OF_DAY#1:10:3.3
(Time of
day)
CHAR 8 Character ’A’,’B’, etc. ’E’
(Character)
Possible One of the following elements can be used as the address of an FBD
Addresses instruction:
A bit whose signal state will be checked
A bit to which the signal state of the logic operation string will be
assigned
A bit to which the result of logic operation (RLO) will be assigned
A bit that will be set or reset
A number that indicates a counter that will be incremented or
decremented
A number that indicates a timer to be used
An edge memory bit that saves the previous RLO
An edge memory bit that saves the previous signal state of a different
address
A byte, word, or double word containing a value with which the FBD
element or box will work
The number of a data block (DB or DI) that will be opened or created
The number of a function (FC), system function (SFC), a function block
(FB), or system function block (SFB) that will be called
A label as the destination for a jump
Address Identifiers Variables as addresses consist of an address identifier and an address within
the memory area indicated by the address identifier. An address identifier can
be one of the following two basic types:
An address identifier that indicates the following two data objects:
– The memory area in which the instruction finds a value (data object)
with which it can perform a logic operation (for example “I” for
process input image, see Table 2-5).
– The size of a value (data object) with which the instruction will
perform a logic operation (for example B for “Byte”, W for “Word”
and D for “Double Word”, see Table 2-5).
An address identifier that indicates a memory area but not the size of the
data object in the area (for example an identifier for the T area (timers), C
(counters), or DB or DI (data block) and the number of the timer, counter,
or data block, see Table 2-5).
Working with If you are working with an instruction whose address identifier indicates a
Words or Double memory area of your programmable controller and a data object that is either
Words as the Data a word or double word in size, remember that the memory location is always
Object referenced as a byte address. This byte address is the smallest byte number or
the number of the high byte within the word or double word. The address in
the instruction shown in Figure 3-2, for example, references four successive
bytes in the memory area M starting at byte 10 (MB10) through to byte 13
(MB13).
Instruction: L MD10
MW10 MW12
MW11
MD10
4.1 Overview
Explanation Bit logic instructions work with two digits, 1 and 0. These two digits form
the base of a number system called the binary system. The two digits 1 and 0
are called binary digits or simply bits. In conjunction with AND, OR, XOR
and outputs, a 1 stands for logical YES and a 0 for logical NO.
The bit logic instructions interpret the signal states 1 and 0 and combine
them according to the rules of Boolean logic. These combinations produce a
result of 1 or 0 known as the result of logic operation (RLO, see Section 2.2).
The logic operations triggered by the bit logic instructions execute a variety
of functions.
Functions Bit logic instructions are available for the following functions:
AND, OR, and XOR: these instructions check the signal state and
produce a result that is either copied to the RLO bit or combined with it.
With AND logic operations, the result of the signal state check is
combined according to the AND truth table (see Table 2-7). With OR
logic operations, the result of the signal state check is combined
according to the OR truth table (see Table 2-8), with exclusive OR logic
operations, according to the exclusive OR truth table (see Table 2-9).
Assign and Midline Output: these instructions assign the RLO or store it
temporarily.
The following instructions react to an RLO of 1:
– Set Output and Reset Output
– Set_Reset Flip Flop and Reset_Set Flip Flop
Some instructions react to a rising or falling edge so that you can execute
the following functions:
– Increment or decrement the value of a counter
– Start a timer
– Produce an output of 1
The remaining instructions affect the RLO directly in the following ways:
– Negate the RLO
– Save the RLO in the binary result bit of the status word
In this chapter, the counter and timer instructions are shown in the
international and SIMATIC forms.
Description With the AND instruction, you can check the signal states of two or more
specified addresses at the inputs of an AND box.
If the signal state of all addresses is 1, the condition is satisfied and the
instruction provides the result 1. If the signal state of an address is 0, the
condition is not satisfied and the instruction produces the result 0.
If the AND instruction is the first instruction in a string of logic operations, it
saves the result of its signal state check in the RLO bit.
Every AND instruction that is not the first instruction in the string of logic
operations, combines the result of its signal state check with the value stored
in the RLO bit. These values are combined according to the AND truth table.
&
I0.0 Q4.0
Output Q4.0 is set when the signal state is 1 at input
I0.1 = I0.0 AND I0.1.
Description With the OR instruction, you can check the signal states of two or more
specified addresses at the inputs of an OR box.
If the signal state of one of the addresses is 1, the condition is satisfied and
the instruction produces the result 1. If the signal state of all addresses is 0,
the condition is not satisfied and the instruction produces the result 0.
If the OR instruction is the first instruction in a string of logic operations, it
saves the result of its signal state check in the RLO bit.
Each OR instruction that is not the first instruction in the string of logic
operations combines the result of its signal state check with the value stored
in the RLO bit. These values are combined according to the OR truth table.
I0.0 >=1
Q4.0 Output Q4.0 is set when the signal state is 1 at input I0.0 OR at input
I0.1 = I0.1.
Description With the AND-before-OR instruction, you can check the result of a signal
state according to the OR truth table.
With an AND-before-OR logic operation the signal state is 1 when at least
one AND logic operation is satisfied.
I0.0 &
The signal state is 1 at output Q3.1 when
I0.1 >=1 at least one AND logic operation is satisfied.
Description With the OR-before-AND instruction, you can check the result of a signal
state check according to the AND truth table.
With an OR-before-AND logic operation the signal state is 1 when all OR
logic operations are satisfied.
I1.0 >=1
The signal state is 1 at output Q3.1 when
I1.1 & both OR logic operations are satisfied.
Description With the Exclusive OR instruction, you can check the result of a signal state
check according to the Exclusive OR truth table.
With an Exclusive OR logic operation, the signal state is 1 when the signal
state of one of the two specified addresses is 1.
XOR The signal state is 1 at output Q3.1 when the signal state is 1 at
I0.0 Q3.1 either input I0.0 OR at input I0.2 (exclusively, in other
I0.2 = words not at both).
Description The Insert Binary Input instruction inserts a further binary input to an AND,
OR, or XOR box.
Q4.0
I1.4 =
4.8 Assign
Description The Assign instruction produces the result of logic operation. The box at the
end of a logic operation has the signal 1 or 0 according to the following
criteria:
The output has the signal 1 when the conditions of the logic operation
before the output box are satisfied
The output has the signal 0 when the conditions of the logic operation
before the output box are not satisfied.
The FBD logic operation assigns the signal state to the output that is
addressed by the instruction (to achieve the same effect, the signal state of
the RLO bit could also be assigned to the address). If the conditions of the
FBD logic operations are satisfied, the signal state at the output box is 1.
Otherwise the signal state is 0. The Assign instruction is influenced by the
Master Control Relay (MCR).
For more detailed information about the functions of the MCR, refer to
Section 16.4.
You can only place the Assign box at the right-hand end of the string of logic
operations. You can, however, use several Assign boxes.
You can create a negated assignment with the Negate Input instruction.
I0.0 & The signal state at output Q4.0 is 1 when the signal
state is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0.
I0.1 >=1
Q4.0
I0.2 =
Description The Midline Output instruction is an intermediate element that buffers the
RLO. More precisely, this element buffers the bit logic operation of the last
branch to be opened before the Midline Output.
The Midline Output instruction is influenced by the Master Control Relay
(MCR). For more information about the MCR functions, see Section 16.4.
You can create a negated Midline Output by negating the input of the
Midline Output.
1 With the Connector instruction you can only use an address in the L memory area if you declare the address in
VAR_TEMP; you cannot use the L memory area for absolute addresses.
The Midline Outputs buffer the following results of the logic operations:
M0.0 buffers the negated I1.0 & M1.1 the negated I1.2 &
RLO of I1.1 RLO of I1.3
Description The Save RLO to BR Memory instruction saves the RLO in the BR bit of the
status word. The first check bit FC is not reset.
For this reason, if there is an AND logic operation in the next network, the
state of the BR bit is included in the logic operation.
Using the “Save RLO to BR Memory” instruction in conjunction with
checking the BR bit in the same block or on subordinate blocks is not
recommended, because the BR bit can be modified by many instructions
occurring inbetween. It is advisable to use the SAVE instruction before
exiting a block, since the ENO output (=BR bit) is then set to the value of the
RLO bit and you can then check for errors in the block.
With the “Save RLO to BR Memory” instruction, the RLO of a network can
form part of a logic operation in a subordinate block. The CALL instruction
in the calling block resets the first check bit.
SAVE None – – –
I1.2 & The result of logic operation (RLO) is written to the BR bit.
I1.3 SAVE
Description The Set Output instruction is only executed when the RLO is 1. If the RLO is
1, this instruction sets the specified address to 1. If the RLO is 0, the
instruction does not affect the specified address which remains unchanged.
The Set Output instruction is influenced by the Master Control Relay (MCR).
For more detailed information about the MCR, refer to Section 16.4.
Description The Reset Output instruction is only executed when the RLO is 1. If the RLO
is 1, this instruction resets the specified address to 0. If the RLO is 0, the
instruction does not affect the specified address which remains unchanged.
The Reset Output instruction is influenced by the Master Control Relay
(MCR). For more detailed information about the MCR, refer to Section 16.4.
Description With the Set Counter Value instruction, you assign a default value to the
counter you have specified. This instruction is executed only when there is a
rising edge at the RLO (change from 0 to 1 in the RLO).
You can only place the Set Counter Value box at the right-hand end of the
string of logic operations. You can, however, use several Set Counter Value
boxes.
Table 4-11 Set Counter Value Box and Parameters, with SIMATIC Mnemonics
Table 4-12 Set Counter Value Box and Parameters with International Mnemonics
C5 The counter C5 has the value 100 preset when the signal
SC state of I0.0 changes from 0 to 1 (rising edge in the RLO).
C# specifies that you are entering a value in BCD format.
I0.0
If there is no rising edge, the value of counter C5 is not
C#100 CV changed.
Table 4-13 Up Counter Boxes and Parameters with SIMATIC and International Mnemonics
<address>
C
CU
Description The Down Counter instruction decrements the value of a specified counter by
1 when there is a rising edge at the RLO (change from 0 to 1) and the value
of the counter is higher than 0. If there is no rising edge at the RLO, or if the
counter has already reached the value 0, the value of the counter is not
decremented.
The Set Counter Value instruction sets the value of the counter (see
Section 4.13).
You can only place the Down Counter box at the right-hand end of the string
of logic operations. You can, however, use more than one Down Counter
boxes.
Table 4-14 Down Counter Boxes and Parameters with SIMATIC and International Mnemonics
<address>
C
CD
Description The Pulse Timer instruction starts a timer with a specified value when there
is a rising edge at the RLO (change from 0 to 1). As long as the RLO is
positive, the timer continues to run for the specified time. A signal state
check for 1 produces 1 as long as the timer is running. If the RLO changes
from 1 to 0 before the time has expired, the timer is stopped. In this case, a
signal state check for 1 produces a result of 0.
The time units used for timers are d (days), h (hours), m (minutes), s
(seconds) and ms (milliseconds).
For more detailed information about the memory area and the components of
a timer, refer to Section 5.1.
You can only place the Pulse Timer box at the right-hand end of the string of
logic operations. You can, however, use more than one Pulse Timer box.
Table 4-15 Pulse Timer Box and Parameters with SIMATIC Mnemonics
Table 4-16 Pulse Timer Box and Parameters with International Mnemonics
Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at
T5 the RLO), timer T5 is started. As long as the signal state is 1, the
SP timer continues to run for the specified time of 2 seconds. If the
signal state at I0.0 changes from 1 to 0 before this time has
I0.0
expired, the timer is stopped.
As long as the timer is running, the signal state at output Q4.0 is 1.
S5T#2s TV
Examples of timer values:
S5T#2s = 2 seconds
Network 2:
Q4.0 S5T#12m_18s = 12 minutes and 18 seconds
T5 =
Description The Extended Pulse Timer instruction starts a timer with a specified value if
there is a rising edge at the RLO (change from 0 to 1). The timer continues to
run for the specified time even if the RLO changes to 0 before this time has
expired. A signal state check for 1 produces 1 as long as the timer is running.
The timer is restarted with the specified time if the RLO changes from 0 to 1
while the timer is running.
For more detailed information about the memory area and the components of
a timer, refer to Section 5.1.
You can only place the Extended Pulse Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one Extended
Pulse Timer box.
Table 4-17 Extended Pulse Timer Box and Parameters with SIMATIC Mnemonics
Table 4-18 Extended Pulse Timer Box and Parameters with International Mnemonics
Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at
T5 the RLO), timer T5 is started. The timer continues to run without
SE being influenced by a falling edge at the RLO. If the signal state of
I0.0 input I0.0 changes from 0 to 1 before the specified time has
expired, the timer is retriggered.
S5T#2s TV
Description The On-Delay Timer instruction starts a specified timer when there is a rising
edge at the RLO (change from 0 to 1). A signal state check for 1 produces 1
when the specified time has expired without an error occurring and the RLO
is still 1. If the RLO changes from 1 to 0 while the timer is running, the timer
is stopped. In this case, a signal state check for 1 always produces the result
0.
For more detailed information about the address of a timer in memory and
the components of a timer, refer to Section 5.1.
You can only place the On-Delay Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one On-Delay
Timer box.
Table 4-19 On-Delay Timer Box and Parameters with SIMATIC Mnemonics
Table 4-20 On-Delay Timer Box and Parameters with International Mnemonics
Network 1:
T5 If the signal state of input I0.0 changes from 0 to 1
SD (rising edge at the RLO), timer T5 is started. When the
time expires, and the signal state is still 1, output Q4.0
I0.0
has the value 1. If the signal state changes from 1 to 0,
the timer is stopped.
S5T#2s TV
Network 2:
Q4.0
T5 =
Description The Retentive On-Delay Timer instruction starts the specified timer when
there is a rising edge at the RLO (change from 0 to 1). The timer continues to
run for the specified time if the RLO changes to 0 before the time has
expired. A signal state check for 1 produces the result 1 regardless of the
RLO if the time has expired. If the RLO changes from 0 to 1 while the timer
is running, the timer is restarted with the specified value.
Fore more detailed information about the address of a timer in memory and
the components of a timer, refer to Section 5.1.
You can only place the Retentive On-Delay Timer box at the right-hand end
of the string of logic operations. You can, however, use more than one
Retentive On-Delay Timer box.
Table 4-21 Retentive On-Delay Timer Box and Parameters with SIMATIC Mnemonics
Table 4-22 On-Delay Timer Box and Parameters with International Mnemonics
Network 1:
T5 If the signal state of input I0.0 changes from 0 to 1 (rising
edge at the RLO), timer T5 is started. The timer continues to
SS
run regardless of whether the signal state at I0.0 changes
I0.0 from 1 to 0. If the signal state changes from 0 to 1 before the
time has expired, the timer is retriggered.
S5T#2s TV Output Q4.0 has the value 1 when the time has expired.
Network 2:
Q4.0
T5 =
Description The Off-Delay Timer instruction starts the specified timer when the RLO has
a falling edge (change from 1 to 0). A signal state check for 1 produces 1
when the RLO is 1 or when the timer is running. The timer is reset when the
RLO changes from 0 to 1 while the timer is running. The time is only
restarted when the RLO changes from 1 to 0.
For more detailed information about the address of a timer in memory and
the components of a timer, refer to Section 5.1.
You can only place the Off-Delay Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one Off-Delay
Timer box.
Table 4-23 Off-Delay Timer Box and Parameters with SIMATIC Mnemonics
Table 4-24 Off-Delay Timer Box and Parameters with International Mnemonics
Network 1:
T5 The timer is started when the signal state at I0.0 changes from
SF 1 to 0.
I0.0
S5T#2s
TV If the signal state changes from 0 to 1, the timer is reset.
Description The Positive RLO Edge Detection instruction detects a change from 0 to 1
(rising edge) at the specified address and indicates this with an RLO of 1
after the instruction. The current signal state at the RLO is compared with the
signal state of the address (the edge memory bit). If the signal state of the
address is 0 and the RLO is 1 before the instruction, the RLO will be 1
(pulse) after the instruction, in all other cases the RLO is 0. The RLO prior to
the instruction is stored in the address.
M1.1
I1.2 &
N >=1
I1.3
M2.2 M3.3 Q4.0
&
I1.4 P N =
Description The Negative RLO Edge Detection instruction detects a change from 1 to 0
(falling edge) at the specified address and indicates this by setting the RLO to
1 after the instruction. The current signal state of the RLO is compared with
the signal state of the address (the edge memory bit). If the signal state of the
address is 1 and the RLO prior to the instruction was 0, the RLO is 1 (pulse)
after the instruction, in all other cases it is 0. The RLO prior to the instruction
is stored in the address.
I1.0 M0.0
& The edge memory bit M3.3 stores the
I1.1 P & signal state of the previous RLO.
M1.1
I1.2 &
N >=1
I1.3
M2.2 M3.3 Q4.0
&
I1.4 P N =
Description The Address Positive Edge Detection instruction compares the signal state of
<address1> with the signal state of the previous signal check that is stored in
the parameter M_BIT. If there has been a change from 0 to 1, output Q has
the value 1, in all other cases it has the value 0.
I0.3
Output Q4.0 is 1 when:
POS
there is a rising edge at input I0.3
AND the signal state is 1 at input I0.4.
&
M0.0 M_BIT Q
Q4.0
I0.4 =
Description The Address Negative Edge Detection instruction compares the signal state of
<address1> with the signal state of the previous check that is stored in the
M_BIT parameter. If a change from 1 to 0 occurred, output Q has the value
1, in all other situations it has the value 0.
I0.3
Output Q4.0 is 1 when:
NEG
there is a falling edge at input I0.3
AND the signal state at input I0.4 is 1.
&
M0.0 M_BIT Q
Q4.0
I0.4 =
Description The Set_Reset Flip Flop instruction executes Set (S) or Reset (R) instructions
only when the RLO is 1. An RLO of 0 has no effect on these instructions, the
address specified in the instruction remains unchanged.
Set_Reset Flip Flop is set when the signal state at input S is 1 and the signal
state at input R is 0. If input S is 0 and input R is 1, the flip flop is reset. If
the RLO at both inputs is 1 the flip flop is reset.
The Set_Reset Flip Flop instruction is influenced by the Master Control
Relay (MCR). For more detailed information about how the MCR functions,
refer to Section 16.4.
Description The Reset_Set Flip Flop instruction executes instructions such as Set (S) or
Reset (R) only when the RLO is 1. An RLO of 0 does not affect these
instructions, the address specified in the instruction is not changed.
Reset_Set Flip Flop is reset when the signal state at input R is 1 and the
signal state at input S is 0. If input R is 0 and input S is 1, the flip flop is set.
If the RLO at both inputs is 1, the flip flop is set.
The Reset_Set Flip Flop instruction is affected by the Master Control Relay
(MCR). For more detailed information about the way in which the MCR
functions, refer to Section 16.4.
Memory Area Timers have an area reserved for them in the memory of your CPU. This
memory area reserves one 16-bit word for each timer address. When you
program in FBD, 256 timers are supported. Please refer to your CPU’s
technical information to check the number of timer words available.
The following functions access the timer memory area:
Timer instructions
Updating of timer words by the clock timing. In the RUN mode, this CPU
function decrements a given time value by one unit at the interval
specified by the time base until the time value is zero.
Time Value Bits 0 through 9 of the timer word contain the time value in binary code. The
time value specifies a number of units. When the timer is updated, the time
value is decremented by one unit at intervals specified by the time base. The
time value is decremented until it is equal to zero.
You can load a predefined time value with the following syntax.
S5T#aH_bbM_ccS_dddMS
– where: a = hours, bb = minutes, cc = seconds and ddd = milliseconds
– The time base is selected automatically, and the value is rounded
down to the next lower number with that time base.
The maximum time value you can enter is 9,990 seconds, or 2H_46M_30S.
Time Base Bits 12 and 13 of the timer word contain the time base in binary code. The
time base defines the interval at which the time value is decremented by one
unit (see Table 5-1 and Figure 5-1). The smallest time base is 10 ms; the
largest is 10 s.
Because time values are saved at only one time interval, values that are not
exact multiples of a time interval are truncated. Values with a resolution too
high for the required range are rounded down to within the required range but
not to the desired resolution. The following table shows the possible
resolutions and the corresponding ranges.
Bit Configuration When a timer is started, the contents of the timer cell are used as the time
in the Timer Cell value. Bits 0 through 11 of the timer cell contain the time value in binary
coded decimal format (BCD format: each group of four bits contains the
binary code for one decimal value). Bits 12 and 13 contain the time base in
binary code (see Table 5-2). Figure 5-1 shows the contents of the timer cell
loaded with timer value 127 with a time base of 1 second.
1 2 7
Figure 5-1 Contents of the Timer Cell for Timer Value 127, Time Base 1 Second
Reading the Time Each timer box provides two outputs, BI and BCD, for which you can specify
and the Time Base a word location. The BI output provides the time value in binary format, the
time base is not displayed. The BCD output provides the time base and the
time value in binary coded decimal (BCD) format.
Description The Pulse S5 Timer instruction starts a specified timer if there is a rising edge
(a change in signal state from 0 to 1) at the Start (S) input. A signal change is
always necessary to start a timer. The timer continues to run for the time
specified at the Time Value (TV) input until the programmed time elapses, as
long as the signal state at input TV is 1. While the timer is running, a signal
state check for 1 at output Q produces a result of 1. If there is a change from
1 to 0 at the S input before the time has elapsed, the timer is stopped. Then a
signal state check for 1 at output Q produces a result of 0.
While the timer is running, a change from 0 to 1 at the Reset (R) input of the
timer resets the timer. This change also resets the time and the time base to
zero. A signal state of 1 at the R input of the timer has no effect if the timer
is not running.
The current time value can be scanned at outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-3 Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics
Table 5-4 Pulse S5 Timer Box and Parameters with International Mnemonics
Example Figure 5-3 illustrates the Pulse S5 Timer instruction, describes the status word
bits, and shows the characteristics of the instruction.
Timing Diagram
–– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Description The Extended Pulse S5 Timer instruction starts a specified timer if there is a
rising edge (change in signal state from 0 to 1) at the Start (S) input. A signal
change is always necessary to start a timer. The timer continues to run for the
time specified at the Time Value (TV) input, even if the signal state at the S
input changes to 0 before the time has elapsed. A signal state check for 1 at
output Q produces a result of 1 as long as the timer is running. The timer is
restarted with the specified time if the signal state at input S changes from 0
to 1 while the timer is running.
A change from 0 to 1 at the Reset (R) input of the timer while the timer is
running resets the timer. This change also resets the time and the time base to
zero.
The current time value can be scanned at the outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-5 Extended Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics
S_VIMP
_ S BOOL E, A, M, D, L, T, Z Start input
E, A, M, D, L or
S DUAL TW S5TIME Preset time value (range 0 to 9999)
constant
TW DEZ R BOOL E, A, M, D, L, T, Z Reset input
Table 5-6 Extended Pulse S5 Timer Box and Parameters with International Mnemonics
Example Figure 5-4 illustrates the Extended Pulse S5 Timer instruction, describes the
status word bits, and shows the characteristics of the instruction.
Timing Diagram
–– t –– –– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Description The On-Delay S5 Timer instruction starts a specified timer if there is a rising
edge (change in signal state from 0 to 1) at the Start (S) input. A signal
change is always necessary to start a timer. The timer continues to run for the
time specified at the Time Value (TV) input as long as the signal state at
input S is 1. A signal state check for 1 at output Q produces a result of 1
when the time has elapsed without error and when the signal state at input S
is still 1. When the signal state at input S changes from 1 to 0 while the timer
is running, the timer is stopped. In this case, a signal state check for 1 at
output Q always produces the result 0.
A change from 0 to 1 at the Reset (R) input of the timer while the timer is
running resets the timer. This change also resets the time and the time base to
zero. The timer is also reset if the signal state is 1 at the R input while the
timer is not running.
The current time value can be scanned at the outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-7 On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics
Table 5-8 On-Delay S5 Timer Box and Parameters with International Mnemonics
Example Figure 5-5 illustrates the On-Delay S5 Timer instruction, describes the bits in
the status word and shows the characteristics of the instruction.
Timing Diagram
–– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Description The Retentive On-Delay S5 Timer instruction starts a specified timer if there
is a rising edge (change in signal state from 0 to 1) at the Start (S) input. A
signal change is always necessary to start a timer. The timer continues to run
for the time specified at the Time Value (TV) input, even if the signal state at
input S changes to 0 before the timer has expired. A signal state check for 1
at output Q produces a result of 1 when the time has elapsed, regardless of
the signal state at input S when the reset input (R) remains at 0. The timer is
restarted with the specified time if the signal state at input S changes from 0
to 1 while the timer is running.
A change from 0 to 1 at the Reset (R) input of the timer resets the timer
regardless of the RLO at the S input.
The current time value can be scanned at the outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-9 Retentive On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics
Table 5-10 Retentive On-Delay S5 Timer Box and Parameters with International Mnemonics
Example Figure 5-6 illustrates the Retentive On-Delay S5 Timer instruction, describes
the status word bits, and shows the characteristics of the instruction.
Timing Diagram
–– t –– –– t –– –– t –– –t–
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Description The Off-Delay S5 Timer instruction starts a specified timer if there is a falling
edge (change in signal state from 1 to 0) at the Start (S) input. A signal
change is always necessary to start a timer. The result of a signal state check
for 1 at output Q is 1 when the signal state at the S input is 1 or when the
timer is running. The timer is reset when the signal state at input S changes
from 0 to 1 while the timer is running. The timer is not restarted until the
signal state at input S changes again from 1 to 0.
A change from 0 to 1 at the Reset (R) input of the timer while the timer is
running resets the timer.
The actual time value can be scanned at the outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-11 Off-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics
Table 5-12 Off-Delay S5 Timer Box and Parameters with International Mnemonics
Example Figure 5-7 illustrates the Off-Delay S5 Timer instruction, describes the status
word bits, and shows the characteristics of the instruction.
T5
S_OFFDT
BI If the signal state at input I0.0 changes from 1 to 0,
I0.0 S
the timer is started. Output Q4.0 is 1 when I0.0 is 1 or
the timer is running. If the signal state at I0.1 changes
S5T# 2s TV BCD from 0 to 1, while the timer is running, the timer is
reset.
Q4.0
I0.1 R Q =
Timing Diagram
–– t –– –– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Memory Area Counters have an area reserved for them in the memory of your CPU. This
memory area reserves one 16-bit word for each counter address. When you
program in FBD, 256 counters are supported.
The counter instructions are the only functions that can access the counter
memory area.
Count Value Bits 0 through 9 of the counter word contain the count value in binary code.
The count value is taken from the accumulator and entered in the counter
word when a counter is set. The range of the count value is 0 to 999. You can
increment/decrement the count value within this range using the Up-Down
Counter, Up Counter, and Down Counter instructions.
Bit Configuration A counter is set to a required value by loading a number between 0 and 999
in the Counter as the count value, for example 127, in the following format:
C# 127
The C# stands for binary coded decimal format (BCD format: each group of
four bits contains the binary code for one decimal value).
Bits 0 through 11 of the counter contain the count value in binary coded
decimal format . Figure 6-1 shows the contents of the counter after you have
loaded the count value 127 and the contents of the counter cell after the
counter has been set.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0 0 1 1 1
irrelevant 1 2 7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1 1 1
Figure 6-1 Contents of the Counter Cell after the Counter has been Set with Count
Value 127
Description A rising edge (change in signal state from 0 to 1) at input S of the Up-Down
Counter instruction sets the counter with the value at the Preset Value (PV)
input. The counter is incremented by 1 if the signal state at input CU changes
from 0 to 1 (rising edge) and the value of the counter is less than 999. The
counter is decremented by 1 if the signal state at input CD changes from 0 to
1 (rising edge) and the value of the counter is higher than 0. If there is a
rising edge at both count inputs, both operations are executed and the count
remains the same. The counter is reset if there is a rising edge at input R.
Resetting the counter sets the count value to 0.
A signal state check for 1 at output Q produces a result of 1 when the count is
greater than 0; the check produces a result of 0 when the count is equal to 0.
Table 6-1 Up-Down Counter Box and Parameters with SIMATIC Mnemonics
Table 6-2 Up-Down Counter Box and Parameters with International Mnemonics
C10
S_CUD A change in signal state from 0 to 1 at
input I0.2 sets counter C10 with the value
I0.0 CU
55. If the signal state of input I0.0
changes from 0 to 1, the value of counter
I0.1 CD C10 is incremented by 1, except when
the value of counter C10 is already 999.
If input I0.1 changes from 0 to 1, counter
I0.2 S CV
C10 is decremented by 1, except when
the value of counter C10 is already 0. If
C#55 PV CV_BCD I0.3 changes from 0 to 1, the value of
Q4.0 C10 is set to 0.
I0.3 R Q = Q4.0 is 1, when C 10 is not equal to 0.
6.3 Up Counter
C10
S_CU
Description A rising edge (change in signal state from 0 to 1) at input S of the Down
Counter instruction sets the counter with the value at the Preset Value input
(PV). With a rising edge at input CD, the counter is decremented by 1 when
the count value is greater than 0. The counter is reset by rising edge at input
R.
A signal state check for 1 at output Q produces a result of 1 when the count is
greater than 0; the check produces a result of 0 when the count is equal to 0.
Table 6-5 Down Counter Box and Parameters with SIMATIC Mnemonics
Table 6-6 Down Counter Box and Parameters with International Mnemonics
Z10
S_CD
Description A signal state of 1 at the Enable (EN) input activates the Add Integer
instruction. This instruction adds inputs IN1 and IN2. The result can be
scanned at O. If the result is outside the permissible range for an integer, the
OV and OS bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Add Double Integer
instruction. This instruction adds inputs IN1 and IN2. The result can be
scanned at O. If the result is outside the permissible range for a double
integer, the OV and the OS bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Subtract Integer
instruction. This instruction subtracts input IN2 from IN1. The result can be
scanned at O. If the result is outside the permitted range for an integer, the
OV and the OS bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Subtract Double
Integer instruction. This instruction subtracts input IN2 from IN1. The result
can be scanned at O. If the result is outside the permitted range for a double
integer, the OV and the OS bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Multiply Integer
instruction. This instruction multiplies input IN1 by IN2. The result is a
32-bit integer that can be scanned at O. If the result is outside the permitted
range for a 16-bit integer, the OV and the OS bit of the status word are 1 and
the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Multiply Double
Integer instruction. This instruction multiplies inputs IN1 and IN2. The result
can be scanned at O. If the result is outside the permitted range for a double
integer, the OV and the OS bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Divide Integer
instruction. This instruction divides input IN1 by IN2. The integer quotient
(truncated result) can be scanned at O. The remainder cannot be scanned. If
the quotient is outside the permitted range for an integer, the OV and the OS
bit of the status word are 1 and the ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Divide Double
Integer instruction. This instruction divides input IN1 by IN2. The quotient
(truncated result) can be scanned at O. The Divide Double Integer instruction
stores the quotient as a single 32-bit value in DINT format. This instruction
does not produce a remainder. If the quotient is outside the permitted range
for a double integer, the OV and the OS bit of the status word are 1 and the
ENO is 0.
Description A signal state of 1 at the Enable (EN) input activates the Return Fraction
Double Integer instruction. This instruction divides input IN1 by IN2. The
remainder (fraction) can be scanned at O. If the result is outside the permitted
range for a double integer, the OV and the OS bit of the status word are 1 and
the ENO is 0.
7.10 Evaluating the Bits of the Status Word with Integer Math
Instructions
Description The integer math instructions influence the following bits in the status word:
CC1 and CC0
OV
OS
A dash (-) in the table means that the bit is not affected by the result of the
instruction.
Table 7-10 Signal State of the Status Word Bits (Result in Valid Range)
Valid Range of the Result Status Word Bits
Integers (16 and 32 bits) CC1 CC0 OV OS
0 (zero) 0 0 0 -
16 bits: -32 768 result 0 (negative number)
0 1 0 -
32 bits: -2 147 483 648 result 0 (negative number)
16 bits: 32 767 result 0 (positive number)
1 0 0 -
32 bits: 2 147 483 647 result 0 (positive number)
Table 7-11 Signal State of the Status Word Bits (Result not in Valid Range)
Invalid Range for the Result Status Word Bits
Integers (16 and 32 bits) CC1 CC0 OV OS
16 bits: result 32 767 (positive number)
1 0 1 1
32 bits: result 2 147 483 647 (positive number)
16 bits: result -32 768 (negative number)
0 1 1 1
32 bits: result -2 147 483 648 (negative number)
Table 7-12 Signal State of the Status Word Bits (Math Instructions with Integers
(32 Bits) +D, /D and MOD)
Operation Status Word Bits
CC1 CC0 OV OS
+D: result = -4 294 967 296 0 0 1 1
/D or MOD: division by 0 1 1 1 1
8.1 Overview
You can use the floating-point math instructions to perform the following
math operations using two 32-bit IEEE floating-point numbers:
Add
Subtract
Multiply
Divide
The IEEE 32-bit floating-point numbers belong to the data type known as
REAL. Using floating-point math, you can carry out the following operations
with one 32-bit IEEE floating-point number:
Form the absolute value (ABS) of a floating-point number
Form the square (SQR) or square root (SQRT) of a floating-point number
Form the natural logarithm (LN) of a floating-point number
Form the exponential value of a floating-point number (EXP) to
base e (= 2.71828...)
Form the following trigonometric functions of an angle, represented as a
32-bit floating-point number:
– Form the sine of a floating-point number (SIN) and form the arc sine
of a floating-point number (ASIN)
– Form the cosine of a floating-point number (COS) and form the arc
cosine of a floating-point number (ACOS)
– Form the tangent of a floating-point number (TAN) and form the arc
tangent of a floating-point number (ATAN)
Description A signal state of 1 at the Enable input (EN) activates the Add Real
instruction. This instruction adds inputs IN1 and IN2. The result can be
scanned at output OUT. If either of the inputs or the result is not a
floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.
For more detailed information about evaluating the bits in the status word,
refer to Section 8.6.
Description A signal state of 1 at the Enable input (EN) activates the Subtract Real
instruction. This instruction subtracts input IN2 from IN1. The result can be
scanned at output OUT. If either of the inputs or the result is not a
floating-point number, the OV bit and the OS bit are set to 1 and ENO is set
to 0.
For more detailed information about evaluating the bits in the status word,
refer to Section 8.6.
Description A signal state of 1 at the Enable input (EN) activates the Multiply Real
instruction. This instruction multiplies input IN1 by IN2. The result can be
scanned at output OUT. If either of the inputs or the result is not a
floating-point number, the OV bit and the OS bit are set to 1 and ENO is set
to 0.
For more detailed information about evaluating the bits in the status word,
refer to Section 8.6.
Description A signal state of 1 at the Enable input (EN) activates the Divide Real
instruction. This instruction divides input IN1 by IN2. The result can be
scanned at output OUT. If either of the inputs or the result is not a
floating-point number, the OV bit and the OS bit are set to 1 and ENO is set
to 0.
For more detailed information about evaluating the bits in the status word,
refer to Section 8.6.
Description Floating-point instructions affect the following bits in the status word:
CC1 and CC0
OV
OS
A dash (–) in the table means that the bit is not affected by the result of the
instruction.
Table 8-5 Signal State of the Status Word Bits for Results of Instructions with
Floating-Point Numbers (Result in the Valid Range)
Table 8-6 Signal State of the Status Word Bits for Results of Instructions with
Floating-Point Numbers (Result outside the Valid Range)
Description With the Form the Absolute Value of a Floating-Point Number instruction,
you can form the absolute value of floating-point number.
Description With the Form the Square of a Floating-Point Number instruction, you can
square a floating-point number. If either of the inputs or the result is not a
floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.
Parameter Table 8-8 shows the SQR box and describes the parameters.
Description With the Form the Square Root of a Floating-Point Number instruction, you
can extract the square root of a floating-point number. This instruction
returns a positive result, if the value at the address is greater than “0”. If
either of the inputs or the result is not a floating-point number, the OV bit
and OS bit are set to 1 and ENO is set to 0.
Parameter Table 8-9 shows the SQRT box and describes the parameters.
Description With the following instructions, you can form trigonometric functions of
angles represented as 32-bit IEEE floating-point numbers.
Instruction Meaning
SIN Form the sine of a floating-point number of an angle specified in
radians.
ASIN Form the arc sine of a floating-point number . The result is an angle
specified in radians. The value is in the following range:
/ 2 arc sine + / 2, where = 3.14...
COS Form the cosine of a floating-point number of an angle specified in
radians.
ACOS Form the arc cosine of a floating-point number . The result is an angle
specified in radians. The value is in the following range:
0 arc cosine + , where = 3.14...
TAN Form the tangent of a floating-point number of an angle specified in
radians.
ATAN Form the arc tangent of a floating-point number . The result is an angle
specified in radians. The value is in the following range:
/ 2 arc tangent + / 2, where = 3.14...
Parameter Tables 8-12 through 8-17 show the SIN, ASIN, COS, ACOS, TAN and ATAN
boxes and describe the parameters.
Description The Compare Integer instruction compares two values on the basis of 16-bit
floating-point numbers. This instruction compares inputs IN1 and IN2
according to the type of comparison you select from the list box. The
following table lists the available types of comparison.
If the comparison is true, the result of logic operation (RLO) of the
comparison is 1. Otherwise, it is 0. You cannot negate the comparison result
itself, but you can achieve the same effect as negation by using the opposite
compare function.
Table 9-2 Compare Integer Box and Parameters (Example using Equal)
Comparison is true:
BR CC1 CC0 OV OS OR STA RLO FC
writes x x x 0 – 0 1 x 1
Description The Compare Double Integer instruction compares two values on the basis of
32-bit floating-point numbers. This instruction compares inputs IN1 and IN2
according to the type of comparison you select from the list box. The
following table lists the available types of comparison.
If the comparison is true, the result of logic operation (RLO) of the
comparison is 1. Otherwise, it is 0. You cannot negate the comparison result
itself, but you can achieve the same effect as negation by using the opposite
compare function.
Table 9-4 Compare Double Integer Box and Parameters (Example using Not Equal)
Description The Compare Real instruction compares two values on the basis of
floating-point numbers. This instruction compares inputs IN1 and IN2
according to the type of comparison you select from the list box. The
following table lists the available types of comparison.
If the comparison is true, the result of logic operation (RLO) of the
comparison is 1. Otherwise, it is 0. You cannot negate the comparison result
itself, but you can achieve the same effect as negation by using the opposite
compare function.
Table 9-6 Compare Real Box and Parameters (Example using Less Than)
Description With the Assign Value instruction, you can assign specific values to variables.
The value specified at the IN input is copied to the address specified at the
OUT output. ENO has the same signal state as EN.
With the MOVE box, the Assign Value instruction can copy all data types
with lengths of 8, 16, or 32 bits. User-defined data types such as arrays or
structures must be be copied with the system function SFC20 “BLKMOV”
(see the Reference Manual /235/).
The Assign Value instruction is affected by the Master Control Relay (MCR).
For more information on how the MCR functions, see Section 16.5.
Assigning Values For information about integrated system functions that can be used as move
to Variables instructions and that can assign a specific value to a variable or can copy
variables of varying types, refer to the Reference Manual /235/.
Description The BCD to Integer instruction reads the content of the input parameter IN as
a three-digit number in binary coded decimal format (BCD, 999) and
converts this number to an integer value. The output parameter OUT contains
the result.
ENO always has the same signal state as EN.
If any of the individual decimal numbers in the BCD number is in the invalid
range between 10 and 15, a BCD error occurs when the conversion is
attempted, causing the following reaction:
The CPU changes to the STOP mode. “BCD conversion error” is entered
in the diagnostic buffer with event ID number 2521.
If OB121 is programmed, it is called.
For more detailed information about programming OB121, refer to the
Reference Manual /235/.
Description The Integer to BCD instruction reads the content of the input parameter IN as
an integer value and converts this value to a three-digit number in binary
coded decimal format (BCD, 999). The output parameter OUT contains
the result. If an overflow occurs, ENO is set to 0.
Description The Integer to Double Integer instruction reads the content of the input
parameter IN as an integer and converts the integer to a double integer. The
output parameter OUT contains the result. ENO always has the same signal
state as EN.
Description The BCD to Double Integer instruction reads the content of the input
parameter IN as a seven-digit number in binary coded decimal format (BCD,
9,999,999) and converts this number to a double integer value. The output
parameter OUT contains the result.
ENO always has the same signal state as EN.
If any of the individual decimal numbers in the BCD number is in the invalid
range between 10 and 15, a BCD error occurs when the conversion is
attempted, causing the following reaction:
The CPU changes to the STOP mode. “BCD conversion error” is entered
in the diagnostic buffer with event ID number 2521.
If OB121 is programmed, it is called.
For more detailed information about programming OB121, refer to the
Reference Manual /235/.
Description The Double Integer to BCD instruction instruction reads the content of the
input parameter IN as a double integer value and converts this value to a
seven-digit number in BCD format ( 9 999 999). The output parameter
OUT contains the result. If an overflow occurs, ENO is set to 0.
Description The Double Integer to Real instruction reads the content of the input
parameter IN as a double integer value and converts this value to a real
number. The output parameter OUT contains the result. ENO always has the
same signal state as EN.
Description The Ones Complement Integer instruction reads the content of the input
parameter IN and performs the Boolean word logic instruction Exclusive Or
Word (see Section 11.6) masked by FFFFH, so that the value of every bit is
inverted. The output parameter OUT contains the result. ENO always has the
same signal state as EN.
Description The Ones Complement Double Integer instruction reads the content of the
input parameter IN and performs the Boolean word logic operation Exclusive
Or Word (see Section 11.6) masked by FFFF FFFFH, so that the value of
every bit is inverted. The output parameter OUT contains the result. ENO
always has the same signal state as EN.
Description The Twos Complement Integer instruction reads the content of the input
parameter IN and changes the sign (for example, from a positive value to a
negative value). The output parameter OUT contains the result. The signal
state of EN is and ENO is always the same except when the signal state of
EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.
Description The Twos Complement Double Integer instruction reads the content of the
input parameter IN and changes the sign (for example, from a positive value
to a negative value). The output parameter OUT contains the result. The
signal state of EN is and ENO is always the same except when the signal
state of EN is 1 and an overflow occurs. In this case, the signal state of ENO
is 0.
Description The Negate Real Number instruction reads the content of the input parameter
IN and inverts the sign bit (the instruction changes the sign of the number. for
example, from 0 for plus to 1 for minus). The bits of the exponent and
mantissa remain the same. The output parameter OUT provides the result.
ENO always has the same signal state as EN except when the signal state of
EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.
Description The Round to Double Integer instruction reads the content of the input
parameter IN as a real number and converts this number to a double integer.
The result is the nearest integer and is contained in output parameter OUT. If
the fraction is x.5, the number is rounded to the even number (for example:
2.5 –> 2, 1.5 –> 2). If an overflow occurs, ENO is set to 0. If the input value
is not a real number, the OV bit and the OS bit have the value 1 and ENO has
the value 0.
Description The Truncate Double Integer Part instruction reads the content of the input
parameter IN as a real number and converts this number to a double integer
(for example 1.5 becomes 1). The result is the integer component of the real
number). The output parameter OUT contains the result. If an overflow
occurs, ENO is set to 0. If the input value is not a real number, the OV bit
and the OS bit have the value 1 and ENO has the value 0.
10.15 Ceiling
Description The Ceiling instruction reads the content of the input parameter IN as a real
number and converts this number to a double integer (for example: +1.2 –>
+2; –1.5 –> –1). The result is the lowest integer which is greater than or
equal to the specified real number. The output parameter OUT contains the
result. If an overflow occurs, ENO is 0. If the input value is not a real
number, the OV bit and the OS bit have the value 1 and ENO has the value 0.
10.16 Floor
Description The Floor instruction reads the content of the input parameter IN as a real
number and converts this number to a double integer. The result is the
highest integer which is lower than or equal to the specified real number. The
output parameter OUT contains the result. If an overflow occurs, ENO is set
to 0. If the input value is not a real number, the OV bit and the OS bit have
the value 1 and ENO has the value 0.
11.1 Overview
What Are Word logic instructions compare pairs of words (16 bits) and double words
Word Logic (32 bits) bit by bit, according to Boolean logic. The following instructions
Instructions? are available for performing word logic operations:
(Word) AND Word: This instruction combines two words bit by bit,
according to the AND truth table.
(Word) AND Double Word: This instruction combines two double words
bit by bit, according to the AND truth table.
(Word) OR Word: This instruction combines two words bit by bit,
according to the OR truth table.
(Word) OR Double Word: This instruction combines two double words bit
by bit, according to the OR truth table.
(Word) Exclusive OR Word: This instruction combines two words bit by
bit, according to the Exclusive OR truth table.
(Word) Exclusive OR Double Word: This instruction combines two
double words bit by bit, according to the Exclusive OR truth table.
Description The (Word) AND Word instruction is activated by signal state 1 at the Enable
input (EN) and combines the two digital values at inputs IN1 and IN2 bit by
bit according to the AND truth table. The values are interpreted as pure bit
patterns. The result can be scanned at output OUT. ENO has the same signal
state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit of the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit of the status
word is set to 1 .
If the result at output OUT is 0, the CC1 bit of the status word is set to 0.
Table 11-1 (Word) AND Word Box and Parameters
Description The (Word) AND Double Word instruction is activated by signal state 1 at the
Enable input (EN) and combines the two digital values at inputs IN1 and IN2
bit by bit according to the AND truth table. The values are interpreted as
pure bit patterns. The result can be scanned at output OUT. ENO has the
same signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit of the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit of the status
word is set to 1 .
If the result at output OUT is 0, the CC1 bit of the status word is set to 0.
Table 11-2 (Word) AND Double Word Box and Parameters
Description The (Word) OR Word instruction is activated by signal state 1 at the Enable
input (EN) and combines the two digital values at inputs IN1 and IN2 bit by
bit according to the OR truth table. The values are interpreted as pure bit
patterns. The result can be scanned at output OUT. ENO has the same signal
state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit of the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit of the status
word is set to 1 .
If the result at output OUT is 0, the CC1 bit of the status word is set to 0.
Table 11-3 (Word) OR Word Box and Parameters
Description The (Word) OR Double Word instruction is activated by signal state 1 at the
Enable input (EN) and combines the two digital values at inputs IN1 and IN2
bit by bit according to the OR truth table. The values are interpreted as pure
bit patterns. The result can be scanned at output OUT. ENO has the same
signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit of the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit of the status
word is set to 1 .
If the result at output OUT is 0, the CC1 bit of the status word is set to 0.
Table 11-4 (Word) OR Double Word Box and Parameters
Description The (Word) Exclusive OR Word instruction is activated by signal state 1 at the
Enable input (EN) and combines the two digital values at inputs IN1 and IN2
bit by bit according to the EXCLUSIVE OR truth table. The values are
interpreted as pure bit patterns. The result can be scanned at output OUT.
ENO has the same signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit in the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit in the status
word is set to 1.
If the result at output OUT is 0, the CC1 bit in the status word is set to 0.
Table 11-5 (Word) Exclusive OR Word Box and Parameters
Description The (Word) Exclusive OR Double Word instruction is activated by signal state
1 at the Enable input (EN) and combines the two digital values at inputs IN1
and IN2 bit by bit according to the EXCLUSIVE OR truth table. The values
are interpreted as pure bit patterns. The result can be scanned at output OUT.
ENO has the same signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit in the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit in the status
word is set to 1.
If the result at output OUT is 0, the CC1 bit in the status word is set to 0.
Table 11-6 (Word) Exclusive OR Double Word Box and Parameters
Description You can use the Shift instructions to move the contents of input IN bit by bit
to the left or the right (see Section 2.3). Shifting n bits to the left multiplies
the contents of input IN by 2 to the power n (2n); shifting n bits to the right
divides the contents of input IN by 2 to the power n (2n). For example, if you
shift the binary equivalent of the decimal value 3 to the left by 3 bits, you
obtain the binary equivalent of the decimal value 24. If you shift the binary
equivalent of the decimal value 16 to the right by 2 bits, you obtain the
binary equivalent of the decimal value 4.
The number that you supply for input parameter N indicates the number of
bits by which the value is shifted. The bit places that are vacated by the Shift
instruction are either padded with zeros or with the signal state of the sign bit
(0 stands for positive and 1 stands for negative). The signal state of the bit
that is shifted last is loaded into the CC1 bit of the status word (see
Section 2.3). The CC0 and OV bits of the status word are reset to 0. You can
use jump instructions to evaluate the CC1 bit.
The following Shift instructions are available:
Shift Left Word, Shift Left Double Word
Shift Right Word, Shift Right Double Word
Shift Right Integer, Shift Right Double Integer
Shift Left Word A signal state of 1 at the Enable input (EN) activates the Shift Left Word
instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the
left.
Input N specifies the number of bits by which to shift the value. If N is
higher than 16, the command writes 0 to output OUT and sets the CC0 and
OV bits of the status word to 0. The bit positions at the right are padded with
zeros. The result of the shift operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if the value of N is not equal to 0. ENO has the same
signal state as EN.
N 6 places
OUT 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0
Figure 12-1 Shifting the Bits of Input IN Six Bits to the Left
Shift Left Double A signal state of 1 at the Enable input (EN) activates the Shift Left Double
Word Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to
the left. Input N specifies the number of bits by which the value will be
shifted. If N is greater than 32, the command writes 0 to output OUT and sets
the CC0 and OV bits of the status word to 0. The vacated bit positions at the
right are padded with zeros. The result of the shift operation can be scanned
at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if the value of N is not equal to 0. ENO has the same
signal state as EN.
Shift Right Word A signal state of 1 at the Enable input (EN) activates the Shift Right Word
instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the
right. Bits 16 to 31 are not affected. Input N specifies the number of bits by
which the value will be shifted. If N is greater than 16, the command writes 0
to output OUT and resets the CC0 and OV bits of the status word to 0. The
vacated bit positions at the left are padded with zeros. The result of the shift
operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
Shift Right Double A signal state of 1 at the Enable input (EN) activates the Shift Right Double
Word Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to
the right. Input N specifies the number of bits by which the value will be
shifted. If N is higher than 32, the command writes 0 to output OUT and
resets the CC0 and OV bits of the status word to 0. The vacated bit positions
at the left are padded with zeros. The result of the shift operation can be
scanned at output OUT.
The operation triggered by this instruction always resets the CC1 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
N 3 places
OUT 0001 1111 1110 1010 1011 0101 0101 1111 111
Shift Right Integer A signal state of 1 at the Enable input (EN) activates the Shift Right Integer
instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the
right. Input N specifies the number of bits by which the value will be shifted.
If N is higher than 16, the command behaves as if N were 16. The bit
positions at the left are padded according to the signal state of bit 15 (the sign
of an integer number). They are filled with zeros if the number is positive,
and with ones if it is negative. The result of the shift operation can be
scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
IN 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0
OUT 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0
Figure 12-7 Shifting Bits of Input IN Four Bits to the Right with Sign
Shift Right Double A signal state of 1 at the Enable input (EN) activates the Shift Right Double
Integer Integer instruction. This instruction shifts the entire contents of input IN bit
by bit to the right. Input N specifies the number of bits by which the value
will be shifted. If N is higher than 32, the command behaves as if N were 32.
The bit positions at the left are padded according to the signal state of bit 31
(the sign of a double integer number). They are filled with zeros if the
number is positive, and with ones if it is negative. The result of the shift
operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
Description You can use the Rotate instructions to rotate the entire contents of input IN
bit by bit to the left or to the right. The vacated bit positions are filled with
the signal states of the bits that are shifted out of input IN.
The number that you specify for input parameter N is the number of bits by
which the value will be rotated.
Depending on the instruction, rotation uses the CC1 bit of the status word
(see Section 2.3). The CC0 bit of the status word is reset to 0.
The following Rotate instructions are available:
Rotate Left Double Word
Rotate Right Double Word
Rotate Left Double A signal state of 1 at the Enable input (EN) activates the Rotate Left Double
Word Word instruction. This instruction rotates the entire contents of input IN bit
by bit to the left. Input N specifies the number of bits by which to rotate. If N
is higher than 32, the double word is rotated ((N–1) modulo 32) +1) places.
The bit positions at the right are filled with the signal states of the bits
rotated. The result of the rotate operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
N 3 places
OUT 111 1000 0101 0101 0000 0111 1000 0111 1111
Rotate Right A signal state of 1 at the Enable input (EN) activates the Rotate Right Double
Double Word Word instruction. This instruction rotates the entire contents of input IN bit
by bit to the right. Input N specifies the number of bits by which the value
will be rotated. The value of N can be between 0 and 31. If N is higher than
32, the double word is rotated ((N–1) modulo 32) +1) places. The bit
positions at the left are filled with the signal states of the bits rotated. The
result of the rotate operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
N 3 places
OUT 1011 0101 0100 0001 1110 0001 1110 1010 101
Description You can use the Open Data Block instruction to open an existing data block
as a shared data block (DB) or instance data block (DI). The number of the
data block is transferred to the DB or DI register. The subsequent DB and DI
commands access the corresponding blocks depending on the register
contents.
Table 13-1 Open Data Block Box and Parameters with SIMATIC Mnemonics
Table 13-2 Open Data Block Box and Parameters with International Mnemonics
Network 1
DB10 is the currently opened data block. The
DB10 scan at DBX0.0 therefore refers to bit 0 of
OPN data byte 0 of data block DB10. The signal
state of this bit is assigned to output Q 4.0.
Network 2
Q 4.0
DBX 0.0 =
The instruction does not change the bits in the status word.
14.1 Overview
Jump Label as The address of a Jump instruction is a label. A label consists of a maximum
Address of four characters. The first character must be a letter; the other characters
can be letters or numbers (for example, SEG3). The jump label indicates the
destination to which you want the program to jump.
You enter the label above the jump box (see Figure 14-1).
Jump Label as The destination label must be at the beginning of a network. You enter the
Destination destination label at the beginning of the network by selecting LABEL from
the FBD list box. An empty box appears. In the box, you type the name of
the label (see Figure 14-1).
Network1
SEG3
JMP
Network 2
Q4.0
I0.1 =
.
.
.
Network X
SEG3
Q4.1
I0.4 R
Network 1
CAS1
JMP The jump is always executed. None of the instructions between
??.?
the jump instruction and the label is executed.
.
.
.
Network X
CAS1
Q4.1
I0.4 R
The instruction does not change the bits in the status word.
Network 1
CAS1
I0.0 JMP
If the signal state of input I0.0 is 1, the jump to label CAS1
is executed. The instruction to reset output Q4.0 is not
executed, even if the signal state of input I0.3 is 1.
Network 2
Q4.0
I0.3 R
Network 3
CAS1
Q4.1
I0.4 R
14.4 Jump-If-Not
Network 1
CAS1
I0.0 JMPN If the signal state of input I0.0 is 0, the jump to label CAS1
is executed. The instruction to reset output Q4.0 is not
executed, even if the signal state of input I0.3 is 1.
Network 2
None of the instructions between the jump operation and
Q4.0
the label is executed.
I0.3 R
Network 3
CAS1
Q4.1
I0.4 R
Description The jump label is the identifier for the destination of a jump instruction. A
jump label must exist for every jump or jump-if-not instruction (JMP or
JMPN).
Format Description
4 characters: first character must be a letter
LABEL remaining characters can be letters or numbers
Network 1
CAS1
I0.0 JMP If I0.0 = 1, the jump to label CAS1 is executed.
Network 3
CAS1
Q4.1
I0.4 R
15.1 Overview
Description The status bit instructions are bit logic instructions (see Chapter 4) that work
with the bits of the status word (see Section 2.3). Each of these instructions
reacts to one of the following conditions that is indicated by one or more bits
of the status word:
The binary result bit is set (has a signal state of 1).
The result of a math function is relative to 0 in one of the following ways:
– Greater than 0 (>0)
– Less than 0 (<0)
– Greater than or equal to 0 (>=0)
– Less than or equal to 0 (<=0)
– Equal to 0 (==0)
– Not equal to 0 (<>0)
The result of a math function is unordered (invalid).
A math function produced an overflow.
In an AND operation, the status bit instructions combine the result of their
signal state checks with the previous result of logic operation according to
the And truth table (see Section 2.2 and Table 2-7). In an OR operation, the
OR truth table is used (see Section 2.2 and Table 2-8).
In this section, the Exception Bit Binary Result element, which checks the
signal state of the BR (Binary Result) bit of the status word, is shown in its
international and SIMATIC form.
Status Word The status word is a register in the memory of your CPU that contains bits
that you can reference in the address of bit and word logic instructions.
Figure 15-1 shows the structure of the status word. For more information on
the individual bits of the status word, see Section 2.3.
215... ...29 28 27 26 25 24 23 22 21 20
BR CC1 CC0 OV OS OR STA RLO FC
Parameters The FBD elements described in the following sections do not have any
selectable parameters.
Description You can use the Exception Bit Binary Result instruction to check the signal
state of the BR bit (Binary Result) of the status word (see Section 2.3). In an
AND operation, the result of the check is combined with the previous RLO
according to the AND truth table (see Section 2.2 and Table 2-7). In an OR
operation, the OR truth table is used (see Section 2.2 and Table 2-8).
FBD Box Figure 15-2 shows the Exception Bit Binary Result box with SIMATIC and
international short names.
BIE BR
Description You can use the Result Bit instructions to determine the relationship of the
result of a math function to zero, in other words, whether the result is >0, <0,
>=0, <=0, ==0, or <>0 (see Table 15-1). The condition code bits of the status
word (CC 1 and CC 0, see Section 2.3) are evaluated. If the comparison
condition indicated in the address is fulfilled, the result of this signal state
check is 1.
In an AND operation, this instruction combines the result of its check with
the previous result of logic operation (RLO) according to the AND truth table
(see Section 2.2 and Table 2-7). In an OR operation, this instruction
combines the result of its check with the previous RLO according to the OR
truth table (see Section 2.2 and Table 2-8).
Figure 15-4 Result Bit for Greater than 0 and Negated Result Bit for Greater than 0
Description You can use the Exception Bit Unordered instruction to check whether or not
the result of a floating-point math function is unordered (in other words,
whether one of the values in the math function is not a valid floating-point
number). The condition code bits of the status word (CC 1 and CC 0, see
Section 2.3) are evaluated. If the result of the math function is unordered
(UO) the signal state check produces a result of 1. If the combination in CC 1
and CC 0 does not indicate unordered, the result of the signal state check is
0.
In an AND operation, this instruction combines the result of its check with
the previous result of logic operation (RLO, see Section 2.3) according to the
AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR
truth table is used (see Section 2.2 and Table 2-8).
FBD Box
UO
Description You can use the Exception Bit Overflow instruction to detect an overflow
(OV) in the last math function. If, after the system executes a math function,
the result is outside the permitted negative range or outside the permitted
positive range, the OV bit in the status word (see Section 2.3) is set. The
instruction checks the signal state of this bit. This bit is reset if the math
functions were free of errors
In an AND operation, this instruction combines the result of its check with
the previous result of logic operation according to the AND truth table (see
Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used
(see Section 2.2 and Table 2-8).
FBD Box
OV
I0.1 &
I0.2 >=1
I0.3 M 3.3
Network 3:
Q4.0
OV S
Description You can use the Exception Bit Overflow Stored instruction to recognize a
previous overflow (overflow stored, OS) in a math function. If, after the
system executes a math function, the result is outside the permitted negative
range or outside the permitted positive range, the OS bit in the status word
(see Section 2.3) is set. The instruction checks the signal state of this bit.
Unlike the OV (overflow) bit, the OS bit remains set even if later math
functions were executed free of errors (see Section 15.5).
In an AND operation, this instruction combines the result of its check with
the previous result of logic operation according to the AND truth table (see
Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used
(see Section 2.2 and Table 2-8).
FBD Box
OS
Network 1:
Network 3:
OS Q4.0
S
Description With the Call FC/SFC without Parameters instruction, you can call a
function (FC) or a system function (SFC) that has no parameters. The call is
conditional or unconditional depending on the preceding logic operation (see
the example).
In the code section of a function (FC), you cannot specify any parameter of
the type BLOCK_FC as the address for a conditional call. You can, however,
specify a parameter of the type BLOCK_FC as the address in a function
block (FB).
A conditional call is executed only if the RLO is 1. If a conditional call is not
executed, the RLO after the call instruction is 0. If the instruction is
executed, the following functions are performed:
The address required to return to the calling block is saved.
The data block registers are saved (data block and instance data block).
The previous local data area is replaced by the current local data area.
The MA bit (active MCR bit) is written to the block stack (BSTACK).
The new local data area is created for the called FC or SFC.
Program execution is then continued in the called block.
For more detailed information about transferring parameters, refer to the
STEP 7 Online Help.
DB10
OPN
MCRA
FC10
CALL
Q4.0
I0.0 =
MCRD
FC11
I0.1 CALL
If the unconditional call for FC10 is executed, the CALL instruction performs the following
functions:
Saves the address required to return to the current FB.
Saves the selectors for DB10 and for the instance data block of the FB.
Pushes the MA bit, set to 1 in the MCRA instruction, to the block stack (BSTACK) and
resets this bit to 0 for the called FC10
Program execution continues in FC10. If you want to use the MCR function in FC10, you must
reactivate it there. When FC10 is completed, program execution returns to the calling FB. The
MA bit is restored. DB10 and the instance data block of the user-defined FB are the current
DBs again, regardless of which DBs were used by FC10.
After the return jump from FC10, the signal state of input I0.0 is assigned to output Q4.0. The
call for FC11 is a conditional call. It is executed only if the signal state of input I0.1 is 1. If the call
is executed, the function is the same as for calling FC10.
Conditional call
BR CC1 CC0 OV OS OR STA RLO FC
writes – – – – 0 0 1 1 0
Description You can call function blocks (FBs), functions (FCs), system function blocks
(SFBs), and system functions (SFCs), and multiple instances by selecting
them from the “Program Elements” list box. They are at the end of the list of
instruction families under the following names:
FB Blocks
FC Blocks
SFB Blocks
SFC Blocks
Multiple Instances
Libraries
When you select one of these blocks, a box appears on your screen with the
number or symbolic name of the function or function block and the
parameters that belong to it.
The block that you call must have been compiled and must already exist in
your program file, in the library, or on the CPU.
If the call FB, FC, SFB, SFC, and multiple instances instruction is executed,
it performs the following functions:
It saves the address required to return to the calling block.
It saves both data block registers (data block and instance data block).
It replaces the previous local data area with the current local data area.
It shifts the MA bit (active MCR bit) to the block stack (BSTACK).
It creates the new local data area for the called FC or SFC.
Note
When the DB and DI registers are saved, it is possible that they do not point
to the data blocks that you opened. Because of the copy mechanisms for
transferring parameters, especially where function blocks are concerned, the
compiler sometimes overwrites the DB register. See the STEP 7 Online Help
for more details.
Enable Output The Enable output (ENO) of an FBD box corresponds to the BR bit of the
status word (see Section 2.3). When you write a function block or function
that you want to call from FBD regardless of whether you write the FB or FC
in STL, LAD or FBD, keep in mind the BR bit. You save the RLO in the BR
bit with the SAVE instruction according to the following criteria:
Save an RLO of 1 in the BR bit when the FB or FC is executed without
error.
Save an RLO of 0 in the BR bit when an error occurs in the execution of
the FB or FC.
You should program these instructions at the end of the FB or FC so that
these are the last instructions that are executed in the block.
Warning
! Unintentionally resetting the BR bit to 0
When writing FBs and FCs in FBD, if you do not handle the BR bit as
described above, one FB or FC may overwrite the BR bit of another FB
or FC.
To avoid this problem, store the RLO at the end of each FB or FC as
described above.
Effect of the Call Figure 16-2 shows the effects of a conditional and an unconditional call of a
on the Bits of the block on the bits of the status word (see Section 2.3).
Status Word
Figure 16-2 Effect of a Block Call on the Bits of the Status Word
Parameters The parameters that have been defined in the VAR section of the block will
be displayed in the FBD box. Supplying parameters differs depending on the
type of block as follows:
For a function (FC), you must supply actual parameters for all of the
formal parameters.
The entry of actual parameters is optional with function blocks (FBs).
You must, however, attach an instance data block (instance DB) to the
FB. If an actual parameter has not been attached to a formal parameter,
the FB works with the values that exist in its instance DB.
With multiple instances, you do not need to specify the instance DB since
the box that is called has already been assigned the DB number (for more
information about declaring multiple instances, refer to STEP 7 Online
Help
For structured IN/OUT parameters and parameters of the types “Pointer” and
“Array”, you must make an actual parameter available (at least during the
first call).
Every actual parameter that you make available when calling a function
block must have the same data type as its formal parameter.
For information on how to program a function or how to work with its
parameters, see the STEP 7 Online Help.
Table 16-2 shows a box for calling FBs, FCs, SFBs, SFCs and describes the
parameters common to the box for all these blocks. The block number
appears automatically at the top of the block (number of the FB, FC, SFB, or
SFC, for example, FC10).
Table 16-2 Box and Parameters for Calling FBs, FCs, SFBs, SFCs
DB13
Calls FB10 (using
FB10 instance DB13)
Actual addresses, EN ENO
The value of this parameter is
the values of which I 1.0 Start Run M2.1
copied from DB13 into M 2.1 after
are copied into I 1.1 Stop processing FB10.
instance data block
DB13 before MW20 Length
processing FB10.
Formal parameters of the FB
16.3 Return
Description You can use the Return instruction to exit blocks. You can exit a block
conditionally.
RET None – – –
Definition of the The Master Control Relay (MCR, see also Section 16.5) is used to activate
Master Control and deactivate signal flow. A deactivated signal flow corresponds to an
Relay instruction sequence that writes a zero value instead of the calculated value,
or to an instruction sequence that leaves the existing memory value
unchanged. Operations triggered by the instructions shown in Table 16-4 are
dependent on the MCR.
The Assign and Midline Output instructions write a 0 to the memory if the
MCR is 0. The Set Output and Reset Output instructions leave the existing
value unchanged (see Table 16-5).
= Assign 4.8
Table 16-5 Instructions Dependent on MCR and How They React to Its Signal State
Signal State of Assign, Midline Output Set or Reset Output Assign a Value
MCR
= S R
MOVE
# SR RS
(Imitates a relay that falls to its (Imitates a latching relay that (Imitates a component that
quiet state when power is remains in its current state produces a value of 0 when
turned off) when power is turned off) power is turned off)
1 Normal execution Normal execution Normal execution
Take care with blocks in which the Master Control Relay was activated with
MCRA:
If the MCR is deactivated, the value 0 is written by all assignments in
program segments between (MCR<) and (MCR>)!
The MCR is deactivated if the RLO was =0 before an MCR< instruction.
Danger
! PLC in STOP or undefined runtime characteristics!
The compiler also uses write access to local data behind the temporary varia-
bles defined in VAR_TEMP for calculating addresses. This means the follo-
wing command sequences will set the PLC to STOP or lead to undefined
runtime characteristics:
Formal parameter access
Access to components of complex FC parameters of the type STRUCT,
UDT, ARRAY, STRING
Access to components of complex FB parameters of the type STRUCT,
UDT, ARRAY, STRING from the IN_OUT area in a version 2 block.
Access to parameters of a version 2 function block if its address is
greater than 8180.0.
Access in a version 2 function block to a parameter of the type
BLOCK_DB opens DB0. Any subsequent data access sets the CPU to
STOP. T 0, C 0, FC0, or FB0 are also always used for TIMER,
COUNTER, BLOCK_FC, and BLOCK_FB.
Parameter passing
Calls in which parameters are transferred.
KOP/FUP
T branches and midline outputs in Ladder or FBD starting with RLO = 0.
Remedy
Free the above commands from their dependence on the MCR:
1. Deactivate the Master Control Relay using the Master Control Relay
Deactivate instruction before the statement or network in question.
2. Activate the Master Control Relay again using the Master Control Relay
Activate instruction after the statement or network in question.
MCR Activate With the Activate Master Control Relay, instruction, you make subsequent
commands dependent on the MCR. After entering this command, you can
program the MCR zones with these instructions (see Section 16.6). When
your program activates an MCR area, all MCR actions depend on the content
of the MCR stack (see Figure B-4).
MCR Deactivate With the Deactivate Master Control Relay instruction, subsequent commands
are no longer dependent on the MCR. After this instruction, you cannot
program any more MCR zones. When your program deactivates an MCR
area, the MCR is always energized irrespective of the entries in the MCR
stack.
The MCR stack and the bit that controls its dependency (the MA bit) relate to
individual levels and must be saved and fetched every time you change the
sequence level. They are preset at the beginning of every sequence level
(MCR input bits 1 to 8 are set to 1, the MCR stack pointer is set to 0 and the
MA bit is set to 0).
The MCR stack is transferred from block to block and the MA bit is saved
and set to 0 every time a block is called. It is fetched back at the end of the
block.
The MCR can be implemented in such a way that it optimizes the run time of
code-generating CPUs. The reason for this is that the dependency of the
MCR is not passed on by the block; it must be explicitly activated by an
MCR instruction. A code-generating CPU recognizes this instruction and
generates the additional code necessary for the evaluation of the MCR stack
until it recognizes an MCR instruction or reaches the end of the block. With
instructions outside the MCRA/MCRD range, there is no increase of the run
time.
The instructions MCRA and MCRD must always be used in pairs within your
program.
ÀÀÀÀÀÀÀ
OB1
ÀÀÀÀÀÀÀ MCRA
MCRA
ÀÀÀÀÀÀÀ
ÀÀÀÀÀÀÀ
MCRD Call FCy
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ
Call FBx
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ
MCRD
ÀÀÀÀÀÀÀ MCRA
BEU
BEU
MCRA
I0.0 MCR<
Q4.0
I0.3 S
Q4.1
I0.4 =
MCR>
MCRD
The MCRA instruction activates the MCR function until the next MCRD. The instructions
between MCR< and MCR> are processed dependent on the MA bit (here I0.0):
You must program the dependency of the functions (FCs) and function blocks
(FBs) in the blocks yourself. If this function or function block is called from
an MCRA/MCRD sequence, not all instructions within this sequence are
automatically dependent on the MCR bit. To achieve this, use the instruction
MCRA of the block called.
Warning
! Risk of personal injury and damage to equipment:
Never use the instruction MCR as an EMERGENCY OFF or safety device
for personnel.
MCR is not a substitute for a hardwired master control relay.
MCR On The Master Control Relay On (MCR<) instruction triggers an operation that
saves the RLO in the MCR stack and opens an MCR zone. The instructions
shown in Table 16-4 are influenced by this RLO saved in the MCR stack
when the MCR zone is opened. The MCR stack works like a LIFO (Last In,
First Out) buffer. Only eight entries are possible. If the stack is already full,
the Master Control Relay On instruction produces an MCR stack error
(MCRF).
MCR Off The Master Control Relay Off (MCR>) instruction closes the MCR zone that
was opened last. The instruction does this by removing the RLO entry from
the MCR stack. The RLO was saved there by the Master Control Relay On
instruction. The entry released at the other end of the LIFO (Last In, First
Out) MCR stack is set to 1. If the stack is already empty, the Master Control
Relay Off instruction produces an MCR stack error (MCRF).
The MCR is controlled by a stack which is one bit wide and eight entries
deep (see Figure 16-7). The MCR is activated as long as all eight entries in
the stack are equal to 1. The MCR< instruction copies the RLO to the MCR
stack. The MCR> instruction removes the last entry from the stack and sets
the released stack address to 1. If an error occurs, for example, if there are
more than eight MCR> instructions in succession, or you attempt to execute
the instruction MCR> when the stack is empty, the MCRF error message is
activated. The monitoring of the MCR stack is based on the stack pointer
(MSP: 0 = empty, 1 = one entry, 2 = two entries, ..., 8 = eight entries).
RLO 1
RLO 2
MSP ! RLO 3
4
5
6
7
8
# "
Shifted bit 1
MA
" "
MCRA 1 0 MCRD
The instructions MCR< and MCR> must always be used in pairs within your
program.
The MCR< instruction adopts the signal state of the RLO and copies it to the
MCR bit.
The MCR> instruction sets the MCR bit to 1 unconditionally. Because of this
characteristic, every other instruction between the instructions MCRA and
MCRD operates independent of the MCR bit (for information about MCRA
and MCRD, see above).
Nesting the You can nest the instructions MCR< and MCR>. The maximum nesting
Instructions MCR< depth is eight, in other words, you can write a maximum of eight MCR<
and MCR> instructions in succession before inserting an MCR> instruction. You must
program an equal number of MCR< and MCR> instructions.
If the MCR< instructions are nested, the MCR bit of the lower nesting level
is formed. The MCR< instruction then combines the current RLO with the
current MCR bit according to the AND truth table.
When an MCR> instruction completes a nesting level, it fetches the MCR bit
from the next highest level.
MCRA
I0.0 MCR<
I0.1 MCR<
Q4.0
I0.3 S
MCR>
Q4.1
I0.4 =
MCR>
MCRD
When the MCRA instruction activates the MCR function, you can create up to eight nested MCR
zones. In the example, there are two MCR zones. The first MCR> instruction works together with the
second MCR< instruction. All instructions between the second set of MCR brackets (MCR<MCR>)
belong to the second MCR zone. The operations are executed as follows:
If I0.0 = 1: the signal state of input I0.4 is assigned to output Q4.1.
If I0.0 = 0: the signal state of output Q4.1 is 0 regardless of the signal state of input I0.4. Output
Q4.0 remains unchanged regardless of the signal state of input I0.3.
If I0.0 and I0.1 = 1: output Q4.0 is set to 1 if I0.3 = 1 and Q4.1 = I0.4.
If I0.1 = 0: output Q4.0 remains unchanged regardless of the signal state of input I0.3 and input
I0.0.
References
C
Function Block Diagram (FBD) for S7-300 and S7-400
P-18 C79000-G7076-C566-01
Alphabetical Lists of Instructions A
Chapter Section Description Page
Overview A.1 List of Instructions with International Names A-2
A.2 List of Instructions with International (English) Names and A-6
German Equivalents
A.3 List of Instructions with German SIMATIC Names A-10
A.4 List of Instructions with German Names and International A-14
(English) Equivalents
Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with Short
Names
Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with Short
Names, cont.
Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with Short
Names, cont.
Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with Short
Names, cont.
Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with German
Equivalents
Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with German
Equivalents, cont.
Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with German
Equivalents, cont.
Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with German
Equivalents, cont.
Table A-3 contains an alphabetical list of FBD instructions with the German
full names, the corresponding short name or mnemonic, and the reference to
the page on which the instruction is described.
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont.
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont.
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont.
Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)
Equivalents
Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)
Equivalents, cont.
Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)
Equivalents, cont.
Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)
Equivalents, cont.
Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and their
SIMATIC Short Names
Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and their
SIMATIC Short Names, continued
B.1 Overview
Practical Each FBD instruction described in this manual executes a specific function.
Applications When you combine these instructions into a program, you can accomplish a
wide variety of automation tasks. This chapter provides the following
examples of practical applications of the FBD instructions:
Controlling a conveyor belt using bit logic instructions
Detecting direction of movement on a conveyor belt using bit logic
instructions
Generating a clock pulse using timer instructions
Keeping track of storage space using counter and comparison instructions
Solving a problem using integer math instructions
Setting the length of time for heating an oven
Instructions Used The examples in this chapter use the following instructions:
Add Integer (ADD_I)
AND
Assign (=)
Assign a Value (MOVE)
Compare Integer (CMP_I>=)
Compare Integer (CMP_I<=)
Divide Integer (DIV_I)
Down Counter (S_CD)
Extended Pulse Timer (SE)
Jump-If-Not (JMPN)
Multiply Integer (MUL_I)
OR
Positive RLO Edge Detection (P)
Reset Output (R)
Return (RET)
Set Output (S)
Up Counter (S_CU)
(Word) AND Word (WAND_W)
(Word) OR Word (WOR_W)
Controlling a Figure B-1 shows a conveyor belt that can be activated electrically. There are
Conveyor Belt two push button switches at the beginning of the belt: S1 for START and S2
for STOP. There are also two push button switches at the end of the belt: S3
for START and S4 for STOP. It it possible to start or stop the belt from either
end. Sensor S5 stops the belt when an item on the belt reaches the end.
Symbolic You can write a program to control the conveyor belt shown in Figure B-1
Programming using symbols that represent the various components of the conveyor system.
If you choose this method, you need to make a symbol table to correlate the
symbols you choose with absolute values (see Table B-1). You define the
symbols in the symbol table (see the STEP 7 Online Help).
Absolute
System Component Symbol Symbol Table
Address
Start button I1.1 S1 I1.1 S1
Stop button I1.2 S2 I1.2 S2
Start button I1.3 S3 I1.3 S3
Stop button I1.4 S4 I1.4 S4
Sensor I1.5 S5 I1.5 S5
Motor Q4.0 MOTOR_ON Q4.0 MOTOR_ON
Sensor S5
S1 ` Start S3 ` Start
S2 ` Stop S4 ` Stop
MOTOR_ON
Absolute You can write a program to control the conveyor belt shown in Figure B-1
Programming using absolute values that represent the different components of the conveyor
system (see Table B-2). Figure B-2 shows an FBD program to control the
conveyor belt.
I1.1 >=1
Q4.0
S
I1.3
Network 2: Pressing either stop button or the sensor at the end of the belt responding turns the
motor off.
I1.2 >=1
I1.4
Q4.0
E1.5 R
Detecting the Figure B-3 shows a conveyor belt that is equipped with two photoelectric
Direction of a barriers (PEB1 and PEB2) that are designed to detect the direction in which a
Conveyor Belt package is moving on the belt.
Symbolic You can write a program to activate a direction display for the conveyor belt
Programming system shown in Figure B-3 using symbols that represent the various
components of the conveyor system, including the photoelectric barriers that
detect direction. If you choose this method, you need to make a symbol table
to correlate the symbols you choose with absolute values (see Table B-3).
You define the symbols in the symbol table (see the STEP 7 Online Help).
Absolute
System Component Symbol Symbol Table
Address
Photoelectric barrier 1 I0.0 PEB1 I0.0 PEB1
Photoelectric barrier 2 I0.1 PEB2 I0.1 PEB2
Display for movement to right Q4.0 RIGHT Q4.0 RIGHT
Display for movement to left Q4.1 LEFT Q4.1 LEFT
Clock memory bit 1 M0.0 PM1 M0.0 PM1
Clock memory bit 2 M0.1 PM2 M0.1 PM2
Absolute You can write a program to activate the direction display for the conveyor
Programming belt shown in Figure B-3 using absolute values that represent the
photoelectric barriers that detect direction (see Table B-4). Figure B-4 shows
an FBD program to control the direction display for the conveyor belt.
Figure B-3 Conveyor Belt System with Photoelectric Light Barriers for Detecting
Direction
Network 1: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.0 and, at the same
time, the signal state at input I0.1 is 0, then the package on the belt is moving to the left.
M 0.0
P &
I0.0
Q4.1
I0.1 S
Network 2: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.1 and, at the same
time, the signal state at input I0.0 is 0, then the package on the belt is moving to the right.
M 0.1
I0.1 P &
Q4.0
I0.0 S
If one of the photoelectric light barriers is interrupted, this means that there is a package between the
barriers.
&
I0.0 Q4.0
I0.1 R
Q4.1
R
Figure B-4 Function Block Diagram for Detecting the Direction of a Conveyor Belt
Clock Pulse You can use a clock pulse generator or flasher relay when you want to
Generator produce a signal that is repeated periodically. Clock pulse generators are
commonly found in signaling systems that control flashing indicator lamps.
When you use the S7-300, you can implement the clock pulse generator
function by using time-driven program execution in special organization
blocks. The example shown in the following FBD program illustrates the use
of timer functions to generate a clock pulse.
The following example shows how to implement a freewheeling clock pulse
generator by using a timer (pulse duty factor 1:1). The frequency is divided
into the values listed in Table B-5.
Network 1: If the signal state of timer T1 is 0, load the time value 250 ms into T1 and start T1 as an
extended-pulse timer.
T1
SE
M0.2 &
S5T#250MS TV
Network 2: The state of the timer is saved temporarily in an auxiliary memory bit.
M0.2
=
T1 &
& JMP
M0.2
Network 4: When the timer T1 expires, the memory word 100 is incremented by 1.
ADD_I
??.? EN
MW100 IN1 OUT MW100
1 IN2 ENO
Network 5: The MOVE instruction allows you to output the different clock frequencies at
outputs Q12.0 through Q13.7.
N001
MOVE
??.? EN OUT QW12
MW100 IN ENO
A signal check of timer T1 produces the result of logic operation (RLO, see
Section 2.3) shown in Figure B-6.
1
0
250 ms
Figure B-6 RLO for the Negated Input Parameter AN T1 in the Clock Pulse Timer
Example
As soon as the time runs out, the timer is restarted. Because of this, the signal
check made by AN M0.2 produces signal state 1 only briefly.
Figure B-7 shows the negated (inverted) RLO bit.
1
0
250 ms
Figure B-7 Negated RLO Bit of Timer T1 in the Clock Pulse Timer Example
Every 250 ms the RLO bit is 0. The jump is ignored and the content of
memory word MW100 is incremented by 1.
Achieving a Table B-5 lists the frequencies that you can achieve from the individual bits
Specific of memory bytes MB101 and MB100. Network 5 in the FBD diagram shown
Frequency in Figure B-5 illustrates how the MOVE instruction allows you to see the
different clock frequencies at outputs Q12.0 through Q13.7.
Table B-6 lists the signal states of the bits of memory byte MB101.
Figure B-8 shows the signal state of memory bit M101.1.
T
1
M101.1 0
Time
0 250 ms 0.5 s 0.75 s 1 s 1.25 s 1.5 s
Frequency 1 1 1Hz
T 1 s
Storage Area with Figure B-9 shows a system with two conveyor belts and a temporary storage
Counter and area in between them. Conveyor belt 1 delivers packages to the storage area.
Comparator A photoelectric barrier at the end of conveyor belt 1 near the storage area
detects how many packages are delivered to the storage area. Conveyor belt 2
transports packages from the temporary storage area to a loading dock where
trucks take the packages away for delivery to customers. A photoelectric
barrier at the end of conveyor belt 2 near the storage area detects how many
packages leave the storage area to go to the loading dock.
A display panel with five lamps indicates the fill level of the temporary
storage area. Figure B-10 shows the FBD program that activates the indicator
lamps on the display panel.
Display panel
Storage area Storage area Storage area Storage area Storage area
empty not empty 50% full 90% full filled to capacity
(Q12.0) (Q12.1) (Q15.2) (Q15.3) (Q15.4)
I0.0 I0.1
Temporary
Packages in storage for 100 Packages out
packages
Network 1: Counter C1 counts up at each signal change from 0 to 1 at input CU and counts down at
each signal change from 0 to 1 at input CD. With a signal change from 0 to ”1” at input S, the counter
value is set to the value PV. A signal change from 0 to 1 at input R resets the counter value to 0.
MW200 contains the current counter value of C1. Q12.1 indicates “storage area not empty”.
C1
S_CUD
I12.0 CU
I12.1 CD
I12.2 S CV MW210
Q12.0
=
Q12.1 &
Network 3: If 50 is less than or equal to the counter value (in other words if the current counter value
is greater than or equal to 50), the indicator lamp for “storage area 50% full” is lit.
CMP
<= I
Q15.2
50 IN1
=
MW200 IN2
Network 4: If the counter value is greater than or equal to 90, the indicator lamp for “storage area 90%
full” is lit.
CMP
>= I
Q15.3
MW200 IN1
=
90 IN2
Network 5: If the counter value is greater than or equal to 100, the indicator lamp for “storage area full”
is lit. Use output Q4.4 to interlock conveyor belt 1.
CMP
>= I
MW200 IN1 Q15.4
100 IN2 =
Figure B-10 Function Block Diagram for Activating Indicator Lamps on a Display Panel
Solving a Math The following sample program shows you how to use three integer math
Problem instructions and the L and T instructions to produce the same result as the
following equation:
(IW0 ) DBW3) 15
MW4 +
MW0
DB1
OPN
Network 2: Input word IW0 is added to shared data word DBW3 (data block must be defined and
opened) and the sum is loaded into memory word MW100. MW100 is then multiplied by 15 and the
answer stored in memory word MW102. MW102 is divided by MW0 with the result stored in MW4. As
long as all results are in the permitted range of each instruction, the ENO passes a signal state of 1 to
the next box.
ADD_I
??.? EN
Heating an Oven The operator of the oven shown in Figure B-12 starts the oven heating by
pushing the start push button. The operator can set the length of time for
heating by using the thumbwheel switches shown in the figure. The value
that the operator sets indicates seconds in binary coded decimal (BCD)
format. Table B-7 lists the components of the heating system and their
corresponding absolute addresses used in the sample program shown in
Figure B-12.
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Oven
4 4 4
Figure B-12 Using the Inputs and Outputs for a Time-Limited Heating Process
Network 1: If the timer is running, then turn on the heater. If the timer is running, the Return instruction
ends the processing here.
Q4.0
& =
T1
Network 2: If the timer is running, the Return instruction ends the processing here.
T1 & RET
Network 3: Mask input bits I0.4 through I0.7 (that is, reset them to 0). These bits of the thumbwheel
inputs are not used. The 16 bits of the thumbwheel inputs are combined with W#16#0FFF according
to the (Word) And Word instruction. The result is loaded into memory word MW1. In order to set the
time base of seconds, the preset value is combined with W#16#2000 according to the (Word) Or
Word instruction, setting bit 13 to 1 and resetting bit 12 to 0.
WAND_W
??.? EN
Network 4: Start timer T1 as an extended pulse timer if the start push button is pressed, loading as a
preset value memory word MW2 (derived from the logic above).
T1
I0.7 & SE
MW2 TV
/800/ DOCPRO
Creating Wiring Diagrams (CD only)
/801/ TeleService for S7, C7 and M7
Remote Maintenance for Automation Systems (CD only)
/802/ PLC Simulation for S7-300 and S7-400 (CD only)
/803/ Reference Manual: Standard Software for S7-300 and S7-400,
STEP 7 Standard Functions, Part 2
Accumulator Accumulators are registers in the CPU which act as intermediate buffers for
load, transfer, comparison, math, and conversion operations.
Actual Parameter Actual parameters replace the formal parameters when function blocks (FBs)
and functions (FCs) are called.
Example: The formal parameter “Start” is replaced by the actual parameter
“I3.6”.
Address An address is part of a STEP 7 statement and specifies what the processor
should execute the instruction on. Addresses can be absolute or symbolic.
Address Identifier An address identifier is the part of the address which contains various data.
The data can include elements such as a value itself (data object) or the size
of a value with which the instruction can, for example, perform a logic
operation. In the instruction statement “L IB10” IB is the address identifier
(“I” indicates the memory input area and “B” indicates a byte in that area).
Array An array is a complex data type which consists of data elements of the same
type. These data elements can be elementary or complex.
Bit Result (BR) The bit result is the link between bit and word-oriented processing. This is an
efficient method to allow the binary interpretation of the result of a word
instruction and to include it in a series of logic operations.
Call Hierarchy All blocks must be called first before they can be processed. The sequence
and nesting of these calls within an organized block is called the call
hierarchy.
Condition Codes The CC 1 and CC 0 bits (condition codes) provide information on the
CC 1 and CC 0 following results or bits:
Result of a math operation
Result of a comparison
Result of a digital operation
Bits that have been shifted out by a shift or rotate command
Current Path Characteristic of the Ladder Logic programming language. Current paths
contain contacts and coils. Complex elements (for example, math functions)
can also be inserted into current paths in the form of “boxes.” Current paths
are connected to power rails.
Data Block (DB) Data blocks (DBs) are areas in a user program which store user data. There
are shared data blocks which can be accessed by all logic blocks and there
are instance data blocks which are associated with a certain function block
(FB) call. In contrast to all other blocks, data blocks do not contain
instructions.
Data, Static Static data are local data of a function block which are stored in the instance
data block and, therefore, remain intact until the function block is processed
again.
Data Type A data type defines how the value of a variable or a constant should be used
in the user program.
In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):
Elementary data types
Complex data types
Data Type, Complex data types are created by the user with the data type declaration.
Complex They do not have their own name and cannot, therefore, be used again. They
can either be arrays or structures. The data types STRING and DATE AND
TIME are classed as complex data types.
Data Type, Elementary data types are preset data types according to IEC 1131–3.
Elementary
Examples:
Data type “BOOL” defines a binary variable (“Bit”)
Data type “INT” defines a 16-bit fixed-point variable.
Declaration The declaration section is used for the declaration of the local data of a logic
block when programming in the Text Editor.
Direct Addressing In direct addressing, the address contains the memory location of a value
which is to be used by the instruction.
Example:
The location Q4.0 defines bit 0 in byte 4 of the process-image output table.
Folder Directory of the user interface of the SIMATIC Manager which can be
opened and can hold other directories or objects.
Formal Parameter A formal parameter is a placeholder for the actual parameter in logic blocks.
In function blocks (FBs) and functions (FCs) the formal parameters are
declared by the user, in system function blocks (SFBs) and system functions
(SFCs) they are already available. When a block is called, formal parameters
are assigned actual parameters, so the called block works with the current
values.
The formal parameters are classed as local data. They can be input, output, or
in/out parameters.
Function Block Function Block Diagram (FBD) is one of the programming languages in
Diagram (FBD) STEP 5 and STEP 7. FBD represents logic in the boxes familiar from
Boolean algebra. In addition, complex functions (for example, math
functions) can be represented in direct connection with the logic box.
Programs created with FBD can also be translated into other programming
languages (for example, Ladder Logic).
Immediate In immediate addressing, the address contains the value with which the
Addressing instruction works.
Example: L.27 means load constant 27 into accumulator.
Input, Incremental When a block is input incrementally, each line or element is checked
immediately for errors (for example, syntax errors). If an error is detected, it
is marked and must be corrected before programming is completed.
Incremental input is possible in STL (Statement List), LAD (Ladder Logic),
and FBD (Function Block Diagram).
Instance Data An instance data block stores the formal parameters and the static data of
Block (DB) function blocks. An instance data block can be assigned to one function
block call or a call hierarchy of function blocks.
Keyword Keywords are used when programming with source files to identify the start
and end of a block and to select sections in the declaration section of blocks,
the start of block comments and the start of titles.
Ladder Logic Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Its
(LAD) representation is standardized in compliance with DIN 19239 (international
standard IEC 1131-1). Ladder Logic representation corresponds to the
representation of relay ladder logic diagrams. In contrast to Statement List
(STL), LAD has a restricted set of instructions.
Logic Block Logic blocks are blocks within SIMATIC S7 that contain a part of the
STEP 7 user program. In contrast, data blocks (DBs) only contain data. There
are the following types of logic blocks: organization blocks (OBs), function
blocks (FBs), functions (FCs), system function blocks (SFBs), and system
functions (SFCs). Blocks are stored in the “Blocks” folder under the “S7
Program” folder.
Logic String A logic string is that portion of a user program which begins with an FC bit
that has a signal state of 0 and which ends when an instruction or event resets
the FC bit to 0. When the CPU executes the first instruction in a logic string,
the FC bit is set to 1. Certain instructions such as output instructions (for
example, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bit
above.
Master Control The Master Control Relay (MCR) is an American relay ladder logic master
Relay switch for energizing and de-energizing power flow (current path). A
de-energized current path corresponds to an instruction sequence that writes a
zero value instead of the calculated value, or, to an instruction sequence that
leaves the existing memory value unchanged.
Network Networks subdivide LAD and FBD blocks into complete current paths and
Statement List (STL) blocks into clear units.
Overflow Bit The status bit OV stands for overflow. An overflow can occur, for example,
after a math operation.
Pointer You can use a pointer to identify the address of a variable. A pointer contains
an identifier instead of a value. If you allocate an actual parameter type, you
provide the memory address. With STEP 7 you can either enter the pointer in
pointer format or simply as an identifier (for example, M 50.0). In the
following example, the pointer format is shown with which data from M 50.0
is accessed:
P#M50.0
Project A project is a folder for all objects in an automation task, irrespective of the
number of stations, modules, and how they are connected in networks.
Reference Data Reference data are used to check your S7 program and include the
cross-reference list, the assignment lists, the program structure, the list of
unused addresses, and the list of addresses without symbols.
Result of Logic The result of logic operation (RLO) is the result of the logic string which is
Operation (RLO) used to process other binary signals. The execution of certain instructions
depends entirely on their preceding RLO.
S7 Program A folder for blocks, source files, and charts for S7 programmable controllers.
The S7 program also includes the symbol table.
Shared Data Block A shared data block is a DB whose address is loaded in the DB address
(DB) register when it is opened. It provides storage and data for all logic blocks
(FCs, FBs, or OBs) that are being executed.
In contrast, an instance DB is designed to be used as specific storage and data
for the FB with which it has been associated.
Source File A source file (text file) is part of a program created either with a graphic or a
text-oriented editor and is compiled into an executable S7 user program or
the machine code for M7.
An S7 source file is stored in the “Sources” folder under the “S7 program”
folder.
Statement List Statement List (STL) is a textual representation of the STEP 7 programming
(STL) language, similar to machine code. STL is the assembler language of STEP 5
and STEP 7. If you program in STL, the individual statements represent the
actual steps in which the CPU executes the program.
Station A station is a device which can be connected to one or more subnets; for
example, the programmable controller, programming device, and operator
station.
Status Bit The status bit stores the value of a bit that is referenced. The status of a bit
instruction that has read access to the memory (A, AN, O, ON, X, XN) is
always the same as the value of the bit that this instruction checks (the bit on
which it performs its logic operation). The status of a bit instruction that has
write access to the memory (S, R, =) is the same as the value of the bit to
which the instruction writes or, if no writing takes place, the same as the
value of the bit that the instruction references. The status bit has no
significance for bit instructions that do not access the memory. Such
instructions set the status bit to 1 (STA=1). The status bit is not checked by
an instruction. It is interpreted during program test (program status) only.
Status Word The status word is part of the register of the CPU. It contains status
information and error information which is displayed when specific STEP 7
commands are executed. The status bits can be read and written on by the
user, the error bits can only be read.
Stored Overflow The status bit OS stands for “stored overflow bit of the status word”. An
Bit overflow can take place, for example, after a math operation.
Symbol A symbol is a name which can be defined by the user subject to syntax
guidelines. After it has been declared (for example, as a variable, data type,
jump label, block etc) the symbol can be used for programming and for
operator interface functions. Example: Address: I 5.0, data type: BOOL,
Symbol: momentary contact switch / emergency stop.
Symbol Table A table in which the symbols of addresses for shared data and blocks are
allocated. Examples: Emergency Stop (symbol) -I 1.7 (address) or
closed-loop control (symbol) - SFB24 (block).
System Function A system function is a function (without a memory) that is integrated in the
(SFC) S7 operating system and can, if necessary, be called from the STEP 7 user
program like a function (FC).
System Function A system function block (SFB) is a function (with a memory) that is
Block (SFB) integrated in the S7 operating system and can, if necessary, be called from
the STEP 7 user program like a function block (FB).
User Data Types User data types are special data structures which you can create yourself and
(UDTs) use in the entire user program after they have been defined. They can be used
like elementary or complex data types in the variable declaration of logic
blocks (FCs, FBs, OBs) or as a template for creating data blocks with the
same data structure.
User Program The user program contains all the statements and declarations and all the data
for signal processing which can be used to control a device or a process. It is
part of a programmable module (CPU, FM) and can be structured with
smaller units (blocks).
User Program The user program structure describes the call hierarchy of the blocks within
Structure an S7 program and provides an overview of the blocks used and their
dependency.
Variable The variable declaration table is used for declaring the local data of a logic
Declaration Table block, when programming takes place in the Incremental Editor.
Variable Table The variable table is used to collect together the variables that you want to
(VAT) monitor and modify and set their relevant formats.
Input Instructions
inserting, 4-7 alphabetical list, A-10–A-24
negating, 4-8 German SIMATIC names and SIMATIC
Input parameter, as part of a box, 2-3 mnemonics, A-10
Instance data block (DI), 16-6 international names and international
Instruction mnemonics, A-2
as box with address, 2-2 international names and SIMATIC
as box with address and value, 2-2 equivalents, A-6
as box with parameters, 2-3 SIMATIC names and international
as element, 2-2 equivalents, A-14
SIMATIC names with SIMATIC
mnemonics and international
mnemonics, A-17
bit logic instructions, 4-2
practical application, B-3
comparison, practical applications,
B-11–B-12
counter, practical applications, B-11–B-12
dependent on Master Control Relay (MCR),
16-8
evaluating the condition code bits (CC1 and
CC0), 7-11, 8-7
evaluating the OS bit, 7-11, 8-7
evaluating the OV bit, 7-11, 8-7
floating-point math, 8-7
effects on the bits of the status word, 8-7
result within the valid range, 8-7
integer math instructions, 7-11
effects on the bits of the status word,
7-11
valid range for results, 7-11
jump instructions, 14-2
math instructions with integers, practical
applications, B-13
practical application, B-2
result bits, 15-4–15-5
rotate instructions, 12-10–12-12
shift instructions, 12-2–12-10
status bit instructions, 15-2–15-10
timer, practical applications, B-7–B-10
word logic, practical applications,
B-14–B-15
word logic instructions, practical
applications, B-14–B-16
Integer (INT), range, 3-3
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