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Basic CVSL

This document summarizes a Cascode Voltage Switch Logic (CVSL) circuit implementation and simulation. The CVSL circuit improves switching times using positive feedback. The document includes the circuit diagram, truth table, SPICE script for simulation, and simulation results showing the logic transitions between 0V and 1.8V in around 5.39 nanoseconds.

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Bangon Kali
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168 views5 pages

Basic CVSL

This document summarizes a Cascode Voltage Switch Logic (CVSL) circuit implementation and simulation. The CVSL circuit improves switching times using positive feedback. The document includes the circuit diagram, truth table, SPICE script for simulation, and simulation results showing the logic transitions between 0V and 1.8V in around 5.39 nanoseconds.

Uploaded by

Bangon Kali
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Gil Michael E.

Regalado CVSL Activity

BS-ECE IV

Cascode Voltage Switch Logic or differential cascode voltage switch logic improves switching times of logic circuits by employing positive feedback. In this exercise we consider the implementation of, = + . This will produce a differential opposite of = + . The following figure shows the circuit diagram. A SPICE script will be created and simulated using 0.18u architecture with 1.8V VDD and logic High.

It has the following truth table. A 0 1 0 1 0 1 0 1 B 0 0 1 1 0 0 1 1 C 0 0 0 0 1 1 1 1 Z 1 0 1 0 1 0 1 1 Z! 0 1 0 1 0 1 0 0

The following is the spice script:


CVSL .PARAM LMIN=0.18u .PARAM WFACTOR=1.5 .PARAM WMIN='LMIN*WFACTOR' .lib "C:\synopsys\rf018.l" TT .global vdd .option post Cout_z Z 0 Cout_!z Z! 0 Vdd vdd 0 1.8 Vin_a Vin_b Vin_c in_a in_b in_c 0 pulse (1.8 0 1.0p 0 0 200n 400n) 0 pulse (1.8 0 1.0p 0 0 400n 800n) 0 pulse (1.8 0 1.0p 0 0 800n 1600n) 100f 100f

Vin_!a in_!a 0 pulse (0 1.8 1.0p 0 0 200n 400n) Vin_!b in_!b 0 pulse (0 1.8 1.0p 0 0 400n 800n) Vin_!c in_!c 0 pulse (0 1.8 1.0p 0 0 800n 1600n) X_cvsl in_a in_b in_c in_!a in_!b in_!c Z Z! cvsl .subckt MN1 MN2 MN3 cvsl in_a in_b in_c in_!a in_!b in_!c Z Z! Z! in_b K 0 nch l=LMIN w='WMIN*2' Z! in_!a 0 0 nch l=LMIN w=WMIN K in_c 0 0 nch l=LMIN w='WMIN*2' in_!b in_a in_!c 0 J 0 0 0 0 nch l=LMIN w=WMIN nch l=LMIN w='WMIN*2' nch l=LMIN w=WMIN

MN4 J MN5 Z MN6 J

MP1 Z Z! MP2 Z! Z .ends .op .tran 1p 1600n .end

vdd vdd pch l=LMIN w='WMIN*1' vdd vdd pch l=LMIN w='WMIN*1'

Using Cosmoscope the simulation results are shown:

If we Zoon a little bit we can see the transition of the logic from 0 to 1.8V

We have determined that the response time for this logic circuit is around: 805.79 800.4 = 5.39

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