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Digital Signal Processing Notes

The document describes CMOS AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) gates. An AOI gate can perform two levels of logic (AND followed by OR) using a single level of transistors. The circuit and truth table of a two-input AOI gate are shown. Similarly, an OAI gate can perform two levels of logic (OR followed by AND) with one level of transistors. AOI and OAI gates have speed and electrical characteristics comparable to NAND and NOR gates, making them appealing for implementing two levels of logic with one gate delay.

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Sannena Govinda
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179 views

Digital Signal Processing Notes

The document describes CMOS AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) gates. An AOI gate can perform two levels of logic (AND followed by OR) using a single level of transistors. The circuit and truth table of a two-input AOI gate are shown. Similarly, an OAI gate can perform two levels of logic (OR followed by AND) with one level of transistors. AOI and OAI gates have speed and electrical characteristics comparable to NAND and NOR gates, making them appealing for implementing two levels of logic with one gate delay.

Uploaded by

Sannena Govinda
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
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1.3.

7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates

CMOS circuits can perform two levels of logic with just a single "level" of transistors. For example, the circuit in Figure 1-17(a) is a two-wide, two-input CMOS AND-OR-INVERT (AOI) gate. . The function table for this circuit is shown in (b) and a logic diagram for this function using AND and NOR gates is shown in Figure 1-18. Transistors can be added to or removed from this circuit to obtain an AOI function with a different number of AND s or a different number of inputs per AND. The contents of each of the Q1-Q8 columns in Figure 1-17(b) depends only on the input signal connected to the corresponding transistor's gate. The last column is constructed by examining each input combination and determining whether Z is connected to VDD or ground by "on" transistors for that input combination. Note that Z is never connected to both VDD and ground for any input combination; in such a case the output would be a non-logic value some-where between LOW and HIGH, and the output structure would consume excessive power due to the lowimpedance connection between VDD and ground.

Fig.1.17 CMOS AND OR INVERT (AOI) gate a) Circuit b) Function table

Fig 1.18 Logic Diagram for CMOS AND OR INVERT gate

A circuit can also be designed to perform an OR-AND-INVERT function. For example, Figure 1-19(a) is a two-wide, two-input CMOS OR-AND-INVERT (OAI) gate. The function table for this circuit is shown in (b); the values in each column are determined just as seen for the CMOS AOI gate. A logic diagram for the OAI function using OR and NAND gates is shown in Figure 1-20.

The speed and other electrical characteristics of a CMOS AOI or OAI gate are quite comparable to those of a single CMOS NAND or NOR gate. As a result, these gates are very appealing because they can perform two levels of logic (AND-OR or OR-AND) with just one level of delay. Most digital designers don't bother to use AOI gates in their discrete designs. However, CMOS VLSI devices often use these gates internally, since many HDL synthesis tools can automatically convert AND/OR logic into AOI gates when appropriate.

Fig.1.19 CMOS OR AND INVERT (OAI) gate a) Circuit b) Function table

Fig 1.20 Logic Diagram for CMOS OR AND INVERT gate

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