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VCO, PLL Principles and Applications

VCO, PLL principles and applications (17.5 – 17.7) • Voltage Controlled Oscillator (VCO) • Phase-Locked Loop (PLL)

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228 views9 pages

VCO, PLL Principles and Applications

VCO, PLL principles and applications (17.5 – 17.7) • Voltage Controlled Oscillator (VCO) • Phase-Locked Loop (PLL)

Uploaded by

Prasit
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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11. VCO, PLL principles and applications (17.5 17.

7)

Voltage Controlled Oscillator (VCO) Phase-Locked Loop (PLL)

EE2603-11

Voltage Controlled Oscillator (VCO)


VCO is a circuit that generates a varying output frequency (square or triangular) which can be adjusted over a range controlled by an input dc voltage.

R1 6
Modulation (control) voltage

VCC 8
S chmit t T r igger Buf f er A mplif ier

Cur r ent S our ce

Output (square)

VCO - 5 6 6
Operating ranges 2k < R1 < 20k 0.75V + VC V + f 1MHz O 10V V + 24V
EE2603-11
Buf f er A mplif ier

C1

7 1

Output (triangular)

2 f = O R1 C1

V + VC V +

Fixed output frequency


1.5kW R2 VC 10kW R3 R1 10kW
6 5 8

VCC 12V
3

f0 f0 VCC

VCO - 5 6 6
4 7 1

VC = VCC

R3 10k = 12 = 10.4V R3 + R2 11.5k


820pF C1

+ 2 V VC f = O R1C1 V +

12 10.4 = 32.5kHz 3 12 12 10 10 820 10

EE2603-11

Variable output frequency

510W R2 5kW R3 VC

R1 10kW
6 5 8

VCC 12V
3

VC (max) = VCC

23k = 12 = 11 .74V 23.51k


2 fO (min) = R1 C1

R3 + R4 R3 + R2 + R4

f0 f0 VCC

VCO - 5 6 6
4 7 1

18kW R4

V + VC (max) + V 2 12 11.74 = = 19.7kHz 3 12 12 10 10 220 10

220pF C1

VC (min) = VCC

R4 18k = 12 = 9.19V R3 + R2 + R4 23.51k


V + VC (min) 2 12 9.19 = = 212.9kHz + 10 103 220 10 12 12 V
EE2603-11 4

2 f (max) = O R1C1

Phase-Locked Loop (PLL)


PLL is a circuit that generates a varying dc (error) output voltage V7 (pin 7) which appears whenever input frequency f0 (pin2 and 3) is different from reference frequency input f5 (pin5) which is usually connected to output frequency of the VCO (pin4)
+ V CC 10
Input 1 Input 2

Output dc pin7
Output

f0 2
3 5 4

Phase D et ect or

L ow- pass f ilt er

A mplif ier

7 V7 6

V7max V7norm V7min fmin f0=f5 fmax

Ref. freq input VCO output

f5

PL L 5 6 5
VCO 8 9 1 R1 C1 - VCC

Reference output

input frequency pin 2,3

EE2603-11

PLL has 3 possible states of operation: 1. free running, 2. capture, 3. locked or tracking.
free running f = f0 = 5 0.3 R1C1
V+ =V 10 fin 2 3
Phas e D et ec t or L ow- pas s f ilt er A mplif ier

C2 R2

lock range fL =

8f0 V+
1 2fL 2 R2C2
f5

7 6

Output

V7

PL L 5 6 5 VCO
R1

capture range fC =

5 4

Reference output

8 9
V+ C1

1
V-

1. If f5 and f0 are too far apart, the PLL free-runs at the nominal VCO frequency f5 2. If f5 and f0 are close enough, the capture process begins and continues until the locked condition is reached. 3. Once locked, the PLL begins the tracking in which it can be locked over a wider range of frequencies than was necessary to achieve capture. The tracking and capture ranges are a function of external resistors and/or capacitors selected by the user.
EE2603-11 6

Example: Given the PLL circuit shown, find (a) Free running frequency f5 = f0 (b) Locked or tracking range fL (c) Capture range fC (d) Output voltage V7 at f0 Sketch the plot of V7 and fin
( a) free running f5 = f0 = = 10 10 3 220 10 12 0.3 0. 3 R1 C1

+6 10 fin 2 3 f0 5 4
10kW Phas e D et ec t or L ow- pas s f ilt er

330pF 3.6kW A mplif ier

C2

R2

7 6

Output

V7
+5V

PL L 5 6 5 VCO
R1

8 9 +6

C1 220pF

-6

= 136.36kHz

(d) f0 =

V 2 (6 VC ) 0.3 = 2 C = 0.3 VC = (2 0.3)3 = 5.1V R1C1 6 R1C1 3

(b) lock range fL =

V+ 181.8kHz fmax = 136.36 + = 136.36k + 90.9k = 227.26kHz 2 181.8kHz fmin = 136.36 + = 136.36k 90.9k = 45.46kHz 2

8f0

8 136.36k = 181.8kHz 6

V7

5.3V 5V 4.7V

(c) capture range fC = fC min = 136.36 + fC max

1 2fL 1 2 181.8k = = 156.1kHz 2 R2 C2 2 3.6k 330 10 12

156.1kHz = 214.41kHz 2 156.1kHz = 136.36 = 46.31kHz 2

fmin f0=f5 fC fL

fmax

fin

EE2603-11

Frequency Synthesis
0.3 0.3 = = 136.36kHz R1C1 10 10 3 220 10 12 Nf 136.36kHz +6V (2) f = f0 = f5 = 0 = = 34.09kHz 1 4 4 10 (1) f4 = Nf0 =
F r equency S ynt hesis S elect or

f0 =

VC = V7 = (2 0.3)3 = 5.1V

V 2 (6 VC ) 0.3 = 2 C = 0.3 R1C1 6 R1C1 3

f1=f0

2 3 5 4

Phase D et ect or

L ow- pass f ilt er

A mplif ier 3 .6 k W

R2

C2
3 3 0 pF

2 4

8 16

+5V 5kW

f5=f0

PL L 5 6 5 VCO
8 10kW 9 1

7 Output 6

( N )

T T L Binar y Count er 7 4 9 0

clock

10kW

f4=Nf0

L ogic L evel S hif t er f r om +6 V/ - 6 V int o 5 V/ 0 V

R1

+6V -6V

C1 220pF

-6V

(4) If V7 = 5.1V is obtained, the input frequency is then 136.36kHz/N

(1) f4 is locked at a center frequency of 136.36kHz (2) Counter will divide f4/4 = f5 = 34.09kHz (3) Thus depending upon the Frequency Synthesis Selector switch, the range of input frequency f1 that can be synthesized is from (136.36/16)=8.5225kHz to EE2603-11 (136.36/2)=68.18kHz

Frequency Shift Keying (FSK) Decoder


( space) 1070Hz or ( mark) 1270Hz
Input

FSK circuit will produce a digital output mark and space levels if two different corresponding input mark and space frequencies are present at the input.
+5V

10 2 3 5 4
Phase D et ect or L ow- pass f ilt er

(2) f0 =

R2
A mplif ier 3 .6 k W

C2
0 .2 m F

600W 600W

7 V7 6 V6 V6 V7

+14 V

VC = 0.3 2.5 VC = V7 = V6 = (2 0.3)2.5 2 = 4.25V


O ut put +14 V - 5 V

2 (5 VC ) 0.3 = R1 C1 5 R1C1

PL L 5 6 5 VCO
9 1
-5V C1 0.05m F -5V

fmin = 1070Hz( space) fmin = 1270Hz (mark)

With no input R1 8 adjusted so that V7 = V6 R1 5kW +5V

- 5 V
10kW 10kW 0.02m F 10kW 0.02m F

+5V

0.02m F

f0 =

2 (5 VC ) R1C1 5

(1) f0 =

0.3 0.3 = = 1200Hz 3 R1C1 5 10 0.05 10 6

V+

f = H
fH = 796Hz fmin = 1070Hz passed fmax = 1270Hz passed f

= 0.796 103 = 796Hz

2 10 103 0.02 10 6

Slope 60dB/decade

Higher freq. produced mixing and harmonics by 1070Hz and 1270Hz rejected EE2603-11

(3) fmax = 1270Hz (mark) will give an output < 4.25V then Comparator output will become low = -5V. (4) Consequently, at fmin = 1070Hz (space) will give an output > 4.25V. Comparator output will become high = +14V. 9

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