Presentation On Gates
Presentation On Gates
What is a gate?
Combination of transistors that perform binary logic So called because one logic state enables or gates another logic state For each gate, the symbol, the truth table, and the formula are shown
44
45
Truth Table
Logic diagram: a graphical representation of a circuit
Each type of gate is represented by a specific graphical symbol
Truth table: defines the function of a gate by listing all possible input combinations that the gate could encounter, and the corresponding output
46
X 0 1
Y 1 0
NOT
Y = ~X Y = !X Y = not X Y = X Y = X Y = X not(Y,X) (Verilog) (ABEL) (VHDL)
(textook) (Verilog)
NOT
X ~X ~~X = X
X ~X ~~X 0 1 0 1 0 1
AND Gate
AND X Z Y Z = X & Y X 0 0 1 1 Y 0 1 0 1 Z 0 0 0 1
AND
X & Y (Verilog and ABEL) X and Y (VHDL) X Y X Y X * Y XY (textbook) and(Z,X,Y) (Verilog)
U V
OR Gate
OR X Y Z = X | Y Z X 0 0 1 1 Y 0 1 0 1 Z 0 1 1 1
OR
X | Y X # Y X or Y X + Y X V Y X U Y or(Z,X,Y) (Verilog) (ABEL) (VHDL) (textbook)
(Verilog)
NAND Gate
NAND X Z Y Z = ~(X & Y) nand(Z,X,Y) X 0 0 1 1 Y 0 1 0 1 Z 1 1 1 0
NAND Gate
NOT-AND
X W Y W = X & Y Z = ~W = ~(X & Y) Z X 0 0 1 1 Y 0 1 0 1 W 0 0 0 1 Z 1 1 1 0
NOR Gate
NOR X Y Z X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 0
Z = ~(X | Y) nor(Z,X,Y)
NOR Gate
NOT-OR X Y W = X | Y Z = ~W = ~(X | Y) W Z X 0 0 1 1 Y 0 1 0 1 W 0 1 1 1 Z 1 0 0 0
NAND Gate
X Y Z = ~(X & Y) X 0 0 1 1 Y 0 1 0 1 W 0 0 0 1 Z 1 1 1 0 Z =
X
Y Z = ~X | ~Y X 0 0 1 1 Y ~X ~Y 0 1 1 1 1 0 0 0 1 1 0 0 Z 1 1 1 0
De Morgans Theorem-1
~(X & Y) = ~X | ~Y
NOT all variables Change & to | and | to & NOT the result
NOR Gate
X
Y Z X Z Y
Z = ~(X | Y) X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 0
Z = ~X & ~Y
X 0 0 1 1 Y ~X ~Y 0 1 1 1 1 0 0 0 1 1 0 0 Z 1 0 0 0
De Morgans Theorem-2
~(X | Y) = ~X & ~Y
NOT all variables Change & to | and | to & NOT the result
De Morgans Theorem
NOT all variables Change & to | and | to & NOT the result -------------------------------------------~X | ~Y = ~(~~X & ~~Y) = ~(X & Y) ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y ~X & !Y = ~(~~X | ~~Y) = ~(X | Y) ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y
Exclusive-OR Gate
XOR X Z Y Z = X ^ Y xor(Z,X,Y)
X Y
0 0 1 1 0 1 0 1
Z
0 1 1 0
XOR
X ^ Y X $ Y X @ Y
X Y
(Verilog) (ABEL)
(textbook)
xor(Z,X,Y)
(Verilog)
Exclusive-NOR Gate
XNOR X Y
Z = ~(X ^ Y)
X Y
Z 0 0 1 1 0 1 0 1
Z
1 0 0 1
Z = X ~^ Y xnor(Z,X,Y)
XNOR
X ~^ Y !(X $ Y) X @ Y
X Y
(Verilog) (ABEL)
xnor(Z,X,Y)
(Verilog)
Multiple-input Gates
Z1 Z2
Z3
Z4
Output Z 1 is HIGH only if all inputs are HIGH An open input will float HIGH
Multiple-input OR Gate
Z2
How to use
B
A B C Q
Q
A
C
0 0 0 1
1 1 1 0
When A = 0, B = C = A = 0 When A = 1, B = C = A = 1
How to use
NOR A B
A 0 0 1 1
B 0 1 0 1
C 1 0 0 0
D 1 0 0 0
E 1 0 0 0
Q 0 1 1 1
Hint 1 : Use 2 NOR gates Hint 2 : From a NOR gate, build a NOT gate
437
How to use
A
A 0 0 1 1
B 0 1 0 1
C 1 1 0 0
D 1 0 1 0
Q 0 0 0 1
Hint 2 : From 2 NOR gates, build 2 NOT gates Hint 3438 : Each NOT gate is an input to the 3rd NOR gate
How to use
A C D
Hint 1 : Use 4 NOR gates Hint 2 : Use 3 NOR gates to build a NAND gate
(previous lesson)
A 0 0 1 1
B 0 1 0 1
C 1 1 0 0
D 1 0 1 0
E 0 0 0 1
Q 1 1 1 0
Hint 3 : Use the 4th NOR gate to build a NOT gate Hint 4 : Insert NOT gate after NAND gate
439
How to use
B A C
A
Q
B 0 1
C 0 1
Q 1 0
0 1
When A = 0, B = C = A = 0 When A = 1, B = C = A = 1
How to use
NAND A B
Hint 1 : Use 2 NAND gates Hint 2 : From a NAND gate, build a NOT gate Hint 3 : Put this NOT gate after a NAND gate Hint 4 441 : NOT-NAND = AND
How to use
A B
Hint 1 : Use 3 NAND gates Hint 2 : Use 2 NAND gates to build 2 NOT gates Hint 3 : Put the 3rd NAND gate after the 2 NOT gates 442
How to use
A B C D
Hint 1 : Use 4 NAND gates Hint 3 : Use a NOR gate to build a NOT gate Hint 4 443 the NOT gate after OR gate : Put