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Testing of Combinational Circuits

The document discusses testing methods for combinational logic circuits. It defines typical digital circuit test setups and fault models. It then covers test generation techniques like the exclusive-OR method and path-sensitizing method. It discusses applying these techniques to common gates and networks, including those with fan-out, and provides examples. It also addresses untestable faults, testing multiple output networks, and how to reduce fault tables to minimum fault detection test sets.

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© Attribution Non-Commercial (BY-NC)
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692 views

Testing of Combinational Circuits

The document discusses testing methods for combinational logic circuits. It defines typical digital circuit test setups and fault models. It then covers test generation techniques like the exclusive-OR method and path-sensitizing method. It discusses applying these techniques to common gates and networks, including those with fan-out, and provides examples. It also addresses untestable faults, testing multiple output networks, and how to reduce fault tables to minimum fault detection test sets.

Uploaded by

binduscribd
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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TESTING OF COMBINATIONAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUIT TESTING DEFINITIONS TYPICAL DIGITAL CIRCUIT TEST SETUP FAULT MODELS COMBINATIONAL LOGIC CIRCUITS TEST GENERATION EXCLUSIVE-OR METHOD PATH-SENSITIZING METHOD PATH-SESITIZING IN POPULAR GATES PATH-SESITIZING IN A NETWORK A NETWORK WITH FAN-OUT COUNTER-EXAMPLE TO SINGLE-PATH SENSITIZING UNTESTABLE FAULTS MULTIPLE OUTPUT NETWORKS FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION CHECK POINTS MINIMUM FDTS ____________________________________________________________________

ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin. Adapted from Digital Logic Circuit Analysis & Design, by Nelson, Nagle, Carroll, Irwin, Prentice-Hall,1995, Chapter 12, pages 739 to 757

TESTING OF COMBINATIONAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUIT TESTING DEFINITIONS

TESTING OF COMBINATIONAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUIT TESTING DEFINITIONS (CONTINUES)

TESTING OF COMBINATIONAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUIT TESTING TYPICAL DIGITAL CIRCUIT TEST SETUP

TESTING OF COMBINATIONAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUIT TESTING TYPICAL DIGITAL CIRCUIT TEST SETUP

TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT MODELS

TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT MODELS

TESTING OF COMBINATIONAL LOGIC CIRCUITS


FAULT MODELS (CONTINUES) Example: Consider the following circuit which has a stuck-atzero at wire 3 ,

TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT MODELS (CONTINUES)

TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS: TEST GENERATION: DEFINITIONS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS: TEST GENERATION: DEFINITIONS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD

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TESTING OF COMBINATIONAL LOGIC CIRCUITS


Example : Find the fault table for all stuck-at faults of the following circuit (circuit 1)
STEP 1
X1 X2 x3 3
Test x1x2x3
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1 4

f = x1 x2 + x3

f
0 1 0 1 0 1 1 1

f1/0
0 1 0 1 0 1 0 1 x3

f1/1
0 0 1 1 0 1 1 1 x2+x3

f2/0
0 1 0 1 0 1 0 1 x3

f2/1
0 1 0 1 1 1 1 1 x1+x3

f3/0
0 0 0 0 0 0 1 1 x1x2

f3/1
1 1 1 1 1 1 1 1 1

f4/0
0 1 0 1 0 1 0 1 x3

f4/1
1 1 1 1 1 1 1 1 1

f5/0
0 0 0 0 0 0 0 0 0

f5/1
1 1 1 1 1 1 1 1 1

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD Example continues (STEP 2)

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN POPULAR GATES

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN POPULAR GATES

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK

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TESTING OF COMBINATIONAL LOGIC CIRCUITS


TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT: ANOTHER EXAMPLE

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT: ANOTHER EXAMPLE

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD COUNTER-EXAMPLE TO SINGLE-PATH SENSITIZING

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

TEST GENERATION: PATH-SENSITIZING METHOD COUNTER-EXAMPLE TO SINGLE-PATH SENSITIZING

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

UNTESTABLE FAULTS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

UNTESTABLE FAULTS (CONTINUES)

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

MULTIPLE OUTPUT NETWORKS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS)

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION CHECK POINTS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION CHECK POINTS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION CHECK POINTS CHECK POINTS ARE: ALL INPUT WIRES THAT ARE NOT FAN-OUT STEMS ALL WIRES THAT ARE FAN-OUT BRANCHES OUTPUTS TO XOR GATES

FAN-OUT STEM REFERS TO THE WIRE PRECEDING THE


FAN-OUT POINT.

THE FAN-OUT POINT. EXAMPLE FOLLOWS

FAN-OUT BRANCHES REFERS TO THE WIRES BEYOND

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION CHECK POINTS EXAMPLE: FOR THE FOLLOWING CIRCUIT, THE CHECK POINTS ARE 1, 3, 4 AND 5

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

EXAMPLE (CONTINUES):

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS) MINIMUM FDTS

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TESTING OF COMBINATIONAL LOGIC CIRCUITS

FAULT DETECTION TEST SETS (FDTS): MINIMUM FDTS: APPLYING THE PROCEDURE TO THE TABLE ON SLIDE 37 YIEDLS {010,011,101,110} AS A MINIMUM TEST SET. THE PETRICK FUNCTION, P, CAN BE USED TO REDUCE THE TABLE: LABELLING THE TESTS ON THE TABLE P0,P1,P2,P3,P4,P5,P6,P7 P = (P6)(P2)(P3)(P2)(P6)(P4+P5)(P3)(P1+P5) P = P6 P2 P3 (P4+P5)(P1+P5) = P6 P2 P3 (P4 P1+P5) P = P6P2P3P4P1 + P6P2P3P5.

THE MINIMAL FDTS IS {P6,P2,P3,P5} = {110,010,011,101}


FOR LARGE FAULT TABLES, THE USE OF PROCEDURES FOR SELECTING A NEAR MINIMAL IS MORE PRACTICAL.
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