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    Adst Jan2010 New

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    Vijay Gurusamy
    This document is an exam paper for an advanced digital systems design course. It contains 15 questions related to topics like sequential circuits, state machines, programmable logic devices, VHDL modeling, and digital testing techniques. The questions cover concepts such as converting between BCD and excess-3 codes, deriving state graphs and tables, eliminating hazards in sequential networks, designing fault-secure PLDs, test generation methods, and modeling digital circuits in VHDL including counters, shift registers, and multiplexers.

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    Adst Jan2010 New

    Uploaded by

    Vijay Gurusamy
    34 views4 pages
    This document is an exam paper for an advanced digital systems design course. It contains 15 questions related to topics like sequential circuits, state machines, programmable logic devices, VHDL modeling, and digital testing techniques. The questions cover concepts such as converting between BCD and excess-3 codes, deriving state graphs and tables, eliminating hazards in sequential networks, designing fault-secure PLDs, test generation methods, and modeling digital circuits in VHDL including counters, shift registers, and multiplexers.

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    This document is an exam paper for an advanced digital systems design course. It contains 15 questions related to topics like sequential circuits, state machines, programmable logic devices, VHDL modeling, and digital testing techniques. The questions cover concepts such as converting between BCD and excess-3 codes, deriving state graphs and tables, eliminating hazards in sequential networks, designing fault-secure PLDs, test generation methods, and modeling digital circuits in VHDL including counters, shift registers, and multiplexers.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as RTF, PDF, TXT or read online from Scribd
    Download as rtf, pdf, or txt
    34 views4 pages

    Adst Jan2010 New

    Uploaded by

    Vijay Gurusamy
    This document is an exam paper for an advanced digital systems design course. It contains 15 questions related to topics like sequential circuits, state machines, programmable logic devices, VHDL modeling, and digital testing techniques. The questions cover concepts such as converting between BCD and excess-3 codes, deriving state graphs and tables, eliminating hazards in sequential networks, designing fault-secure PLDs, test generation methods, and modeling digital circuits in VHDL including counters, shift registers, and multiplexers.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as RTF, PDF, TXT or read online from Scribd
    Download as rtf, pdf, or txt
    of 4

    Reg. No.

    Question Paper Code:

    W7602
    M.E. DEGREE EXAMINATION, JANUARY 2010 First Sem ester A p p lied Electron ics AP 9212 ADVANCED DIGITAL SYSTEM DESIGN (Com m on to M .E. VLSI Design) (Regulations 2009) Time: Three hours Answ er ALL Q uestion s PART A (10 2 = 20 Marks) 1. 2. 3. 4. What is the difference between a mealy machine and a Moore machine? State two reasons why a state table might be incompletely specified. Define a primitive flow table. What is the most important consideration in making state assignments for asynchronous networks? 5. D efine test coverag e. Maximum: 100 Marks

    6. 7. 8. 9.

    What are propagation D-cuts? Differentiate the three basic types of PLD. What are the limitations of PLDs using AND OR structure? Write down the syntax for declaring a package.

    10 .

    Define test bench.

    PART B (5 16 = 80 Marks) Design a sequential circuit to convert BCD to 11. (a) excess codes. Or (b) A Moore sequential network has one input and one output. The output should be 1 if the total num ber of 1s received is odd and the total num ber of 0s received is an even num ber greater than 0. Derive the state graph and table. How can essential hazards be determined and 12. (a) eliminated network? Or (b) Design a vending machine controller with suitable circuits. (16) (16) from a (16) (16)

    Explain the procedure for designing fault-secure suitabl PLA 13. (a) w ith e exam p l e. Or (i) Explain how the Boolean difference method is for (b) used test generation with example. (ii) Explain the logic diagram of built in logic block observer. Design a 4 bit binary counter using PAL 14. (a) chip. Or (b) Explain how FPGA can be program m ed to im plem ent a finite state (8) (8) (16) (16)

    m a ch in e.

    (16)

    Using structural modeling write a VHDL for a 4 bit shift 15. (a) register. Also write a test bench for it. (16)

    Or (b) Write a VHDL code for the following circuits: (i) 8 : multiplexer (4) (12)

    Serial added using finite state machine (ii) approach.

    W 7602

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